{
TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr) :
- paddr(_paddr), vaddr(_vaddr), size(PageBytes), writable(true), user(true),
- uncacheable(false), global(false), patBit(0), noExec(false)
+ paddr(_paddr), vaddr(_vaddr), logBytes(PageShift), writable(true),
+ user(true), uncacheable(false), global(false), patBit(0), noExec(false)
{}
void
{
SERIALIZE_SCALAR(paddr);
SERIALIZE_SCALAR(vaddr);
- SERIALIZE_SCALAR(size);
+ SERIALIZE_SCALAR(logBytes);
SERIALIZE_SCALAR(writable);
SERIALIZE_SCALAR(user);
SERIALIZE_SCALAR(uncacheable);
SERIALIZE_SCALAR(global);
SERIALIZE_SCALAR(patBit);
SERIALIZE_SCALAR(noExec);
+ SERIALIZE_SCALAR(lruSeq);
}
void
{
UNSERIALIZE_SCALAR(paddr);
UNSERIALIZE_SCALAR(vaddr);
- UNSERIALIZE_SCALAR(size);
+ UNSERIALIZE_SCALAR(logBytes);
UNSERIALIZE_SCALAR(writable);
UNSERIALIZE_SCALAR(user);
UNSERIALIZE_SCALAR(uncacheable);
UNSERIALIZE_SCALAR(global);
UNSERIALIZE_SCALAR(patBit);
UNSERIALIZE_SCALAR(noExec);
+ UNSERIALIZE_SCALAR(lruSeq);
}
}
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "base/types.hh"
+#include "base/trie.hh"
class Checkpoint;
+namespace X86ISA
+{
+ struct TlbEntry;
+}
+
+typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
+
namespace X86ISA
{
BitUnion64(VAddr)
// The beginning of the virtual page this entry maps.
Addr vaddr;
- // The size of the page this entry represents.
- Addr size;
+ // The size of the page this represents, in address bits.
+ unsigned logBytes;
// Read permission is always available, assuming it isn't blocked by
// other mechanisms.
bool patBit;
// Whether or not memory on this page can be executed.
bool noExec;
+ // A sequence number to keep track of LRU.
+ uint64_t lruSeq;
+
+ TlbEntryTrie::Handle trieHandle;
TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
TlbEntry() {}
#include "arch/x86/tlb.hh"
#include "arch/x86/vtophys.hh"
#include "base/bitfield.hh"
+#include "base/trie.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/PageTableWalker.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
-#include "sim/system.hh"
namespace X86ISA {
}
Fault
-Walker::startFunctional(ThreadContext * _tc, Addr &addr, Addr &pageSize,
+Walker::startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes,
BaseTLB::Mode _mode)
{
funcState.initState(_tc, _mode);
- return funcState.startFunctional(addr, pageSize);
+ return funcState.startFunctional(addr, logBytes);
}
bool
}
Fault
-Walker::WalkerState::startFunctional(Addr &addr, Addr &pageSize)
+Walker::WalkerState::startFunctional(Addr &addr, unsigned &logBytes)
{
Fault fault = NoFault;
assert(started == false);
state = nextState;
nextState = Ready;
} while(read);
- pageSize = entry.size;
+ logBytes = entry.logBytes;
addr = entry.paddr;
return fault;
}
if (!pte.ps) {
// 4 KB page
- entry.size = 4 * (1 << 10);
+ entry.logBytes = 12;
nextRead =
((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * dataSize;
nextState = LongPTE;
break;
} else {
// 2 MB page
- entry.size = 2 * (1 << 20);
+ entry.logBytes = 21;
entry.paddr = (uint64_t)pte & (mask(31) << 21);
entry.uncacheable = uncacheable;
entry.global = pte.g;
}
if (!pte.ps) {
// 4 KB page
- entry.size = 4 * (1 << 10);
+ entry.logBytes = 12;
nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 * dataSize;
nextState = PAEPTE;
break;
} else {
// 2 MB page
- entry.size = 2 * (1 << 20);
+ entry.logBytes = 21;
entry.paddr = (uint64_t)pte & (mask(31) << 21);
entry.uncacheable = uncacheable;
entry.global = pte.g;
}
if (!pte.ps) {
// 4 KB page
- entry.size = 4 * (1 << 10);
+ entry.logBytes = 12;
nextRead =
((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
nextState = PTE;
break;
} else {
// 4 MB page
- entry.size = 4 * (1 << 20);
+ entry.logBytes = 21;
entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22;
entry.uncacheable = uncacheable;
entry.global = pte.g;
break;
}
// 4 KB page
- entry.size = 4 * (1 << 10);
+ entry.logBytes = 12;
nextRead = ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
nextState = PTE;
break;
void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
bool _isTiming = false);
Fault startWalk();
- Fault startFunctional(Addr &addr, Addr &pageSize);
+ Fault startFunctional(Addr &addr, unsigned &logBytes);
bool recvPacket(PacketPtr pkt);
bool isRetrying();
bool wasStarted();
Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
RequestPtr req, BaseTLB::Mode mode);
Fault startFunctional(ThreadContext * _tc, Addr &addr,
- Addr &pageSize, BaseTLB::Mode mode);
+ unsigned &logBytes, BaseTLB::Mode mode);
MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
protected:
namespace X86ISA {
-TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
+TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size),
+ lruSeq(0)
{
+ if (!size)
+ fatal("TLBs must have a non-zero size.\n");
tlb = new TlbEntry[size];
std::memset(tlb, 0, sizeof(TlbEntry) * size);
- for (int x = 0; x < size; x++)
+ for (int x = 0; x < size; x++) {
+ tlb[x].trieHandle = NULL;
freeList.push_back(&tlb[x]);
+ }
walker = p->walker;
walker->setTLB(this);
}
+void
+TLB::evictLRU()
+{
+ // Find the entry with the lowest (and hence least recently updated)
+ // sequence number.
+
+ unsigned lru = 0;
+ for (unsigned i = 1; i < size; i++) {
+ if (tlb[i].lruSeq < tlb[lru].lruSeq)
+ lru = i;
+ }
+
+ assert(tlb[lru].trieHandle);
+ trie.remove(tlb[lru].trieHandle);
+ tlb[lru].trieHandle = NULL;
+ freeList.push_back(&tlb[lru]);
+}
+
TlbEntry *
TLB::insert(Addr vpn, TlbEntry &entry)
{
//TODO Deal with conflicting entries
TlbEntry *newEntry = NULL;
- if (!freeList.empty()) {
- newEntry = freeList.front();
- freeList.pop_front();
- } else {
- newEntry = entryList.back();
- entryList.pop_back();
- }
+ if (freeList.empty())
+ evictLRU();
+ newEntry = freeList.front();
+ freeList.pop_front();
+
*newEntry = entry;
+ newEntry->lruSeq = nextSeq();
newEntry->vaddr = vpn;
- entryList.push_front(newEntry);
+ newEntry->trieHandle =
+ trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
return newEntry;
}
-TLB::EntryList::iterator
-TLB::lookupIt(Addr va, bool update_lru)
-{
- //TODO make this smarter at some point
- EntryList::iterator entry;
- for (entry = entryList.begin(); entry != entryList.end(); entry++) {
- if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
- DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
- "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
- if (update_lru) {
- entryList.push_front(*entry);
- entryList.erase(entry);
- entry = entryList.begin();
- }
- break;
- }
- }
- return entry;
-}
-
TlbEntry *
TLB::lookup(Addr va, bool update_lru)
{
- EntryList::iterator entry = lookupIt(va, update_lru);
- if (entry == entryList.end())
- return NULL;
- else
- return *entry;
+ TlbEntry *entry = trie.lookup(va);
+ if (entry && update_lru)
+ entry->lruSeq = nextSeq();
+ return entry;
}
void
TLB::invalidateAll()
{
DPRINTF(TLB, "Invalidating all entries.\n");
- while (!entryList.empty()) {
- TlbEntry *entry = entryList.front();
- entryList.pop_front();
- freeList.push_back(entry);
+ for (unsigned i = 0; i < size; i++) {
+ if (tlb[i].trieHandle) {
+ trie.remove(tlb[i].trieHandle);
+ tlb[i].trieHandle = NULL;
+ freeList.push_back(&tlb[i]);
+ }
}
}
TLB::invalidateNonGlobal()
{
DPRINTF(TLB, "Invalidating all non global entries.\n");
- EntryList::iterator entryIt;
- for (entryIt = entryList.begin(); entryIt != entryList.end();) {
- if (!(*entryIt)->global) {
- freeList.push_back(*entryIt);
- entryList.erase(entryIt++);
- } else {
- entryIt++;
+ for (unsigned i = 0; i < size; i++) {
+ if (tlb[i].trieHandle && !tlb[i].global) {
+ trie.remove(tlb[i].trieHandle);
+ tlb[i].trieHandle = NULL;
+ freeList.push_back(&tlb[i]);
}
}
}
void
TLB::demapPage(Addr va, uint64_t asn)
{
- EntryList::iterator entry = lookupIt(va, false);
- if (entry != entryList.end()) {
- freeList.push_back(*entry);
- entryList.erase(entry);
+ TlbEntry *entry = trie.lookup(va);
+ if (entry) {
+ trie.remove(entry->trieHandle);
+ entry->trieHandle = NULL;
+ freeList.push_back(entry);
}
}
return new PageFault(vaddr, true, Write, inUser, false);
}
- Addr paddr = entry->paddr | (vaddr & (entry->size-1));
+ Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
req->setPaddr(paddr);
if (entry->uncacheable)
#include "arch/x86/regs/segment.hh"
#include "arch/x86/pagetable.hh"
+#include "base/trie.hh"
#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/X86TLB.hh"
EntryList freeList;
EntryList entryList;
+ TlbEntryTrie trie;
+ uint64_t lruSeq;
+
Fault translateInt(RequestPtr req, ThreadContext *tc);
Fault translate(RequestPtr req, ThreadContext *tc,
public:
+ void evictLRU();
+
+ uint64_t
+ nextSeq()
+ {
+ return ++lruSeq;
+ }
+
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
vtophys(ThreadContext *tc, Addr vaddr)
{
Walker *walker = tc->getDTBPtr()->getWalker();
- Addr size;
+ unsigned logBytes;
Addr addr = vaddr;
- Fault fault = walker->startFunctional(tc, addr, size, BaseTLB::Read);
+ Fault fault = walker->startFunctional(
+ tc, addr, logBytes, BaseTLB::Read);
if (fault != NoFault)
panic("vtophys page walk returned fault\n");
- Addr masked_addr = vaddr & (size - 1);
+ Addr masked_addr = vaddr & mask(logBytes);
Addr paddr = addr | masked_addr;
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
return paddr;
projects / gem5.git / commitdiff