/* Must be long enough to hold any of the names in arm_cpus. */
static char selected_cpu_name[16];
+extern FLONUM_TYPE generic_floating_point_number;
+
/* Return if no cpu was selected on command-line. */
static bfd_boolean
no_cpu_selected (void)
return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
}
+
+/* Detect the presence of a floating point or integer zero constant,
+ i.e. #0.0 or #0. */
+
+static bfd_boolean
+parse_ifimm_zero (char **in)
+{
+ int error_code;
+
+ if (!is_immediate_prefix (**in))
+ return FALSE;
+
+ ++*in;
+ error_code = atof_generic (in, ".", EXP_CHARS,
+ &generic_floating_point_number);
+
+ if (!error_code
+ && generic_floating_point_number.sign == '+'
+ && (generic_floating_point_number.low
+ > generic_floating_point_number.leader))
+ return TRUE;
+
+ return FALSE;
+}
+
/* Parse an 8-bit "quarter-precision" floating point number of the form:
0baBbbbbbc defgh000 00000000 00000000.
The zero and minus-zero cases need special handling, since they can't be
OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
+ OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
OP_RR_RNSC, /* ARM reg or Neon scalar. */
OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
break;
+ case OP_RSVD_FI0:
+ {
+ po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
+ break;
+ try_ifimm0:
+ if (parse_ifimm_zero (&str))
+ inst.operands[i].imm = 0;
+ else
+ {
+ inst.error
+ = _("only floating point zero is allowed as immediate value");
+ goto failure;
+ }
+ }
+ break;
+
case OP_RR_RNSC:
{
po_scalar_or_goto (8, try_rr);
nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
- nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
- nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
+ nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
+ nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: UAL vcmp with 0
+#as: -mfpu=vfpv3
+
+.*: +file format .*arm.*
+
+
+Disassembly of section .text:
+0+000 <[^>]*> eeb50a40 vcmp.f32 s0, #0.0
+0+004 <[^>]*> eef50a40 vcmp.f32 s1, #0.0
+0+008 <[^>]*> eef51ac0 vcmpe.f32 s3, #0.0
+0+00c <[^>]*> eeb52ac0 vcmpe.f32 s4, #0.0
+0+010 <[^>]*> eef52a40 vcmp.f32 s5, #0.0
+0+014 <[^>]*> eeb53a40 vcmp.f32 s6, #0.0
+0+018 <[^>]*> eef53ac0 vcmpe.f32 s7, #0.0
+0+01c <[^>]*> eeb54ac0 vcmpe.f32 s8, #0.0
+0+020 <[^>]*> eeb50b40 vcmp.f64 d0, #0.0
+0+024 <[^>]*> eeb51b40 vcmp.f64 d1, #0.0
+0+028 <[^>]*> eeb52bc0 vcmpe.f64 d2, #0.0
+0+02c <[^>]*> eeb53bc0 vcmpe.f64 d3, #0.0
+0+030 <[^>]*> eeb54b40 vcmp.f64 d4, #0.0
+0+034 <[^>]*> eeb55b40 vcmp.f64 d5, #0.0
+0+038 <[^>]*> eeb56bc0 vcmpe.f64 d6, #0.0
+0+03c <[^>]*> eeb57bc0 vcmpe.f64 d7, #0.0
\ No newline at end of file