Major cleanup of python config code.
authorSteve Reinhardt <stever@eecs.umich.edu>
Sun, 29 May 2005 05:14:50 +0000 (01:14 -0400)
committerSteve Reinhardt <stever@eecs.umich.edu>
Sun, 29 May 2005 05:14:50 +0000 (01:14 -0400)
Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions.  This commit is for my
own convenience and won't be pushed until more testing
is done.

python/m5/__init__.py:
    Get rid of mpy_importer and param_types.
python/m5/config.py:
    Major cleanup.  We now have separate classes and
    instances for SimObjects.  Proxy handling and param
    conversion significantly reorganized.  No explicit
    instantiation step anymore; we can dump an ini file
    straight from the original tree.
    Still needs more/better/truer comments.
test/genini.py:
    Replace LoadMpyFile() with built-in execfile().
    Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    Fixes for eliminating mpy_importer, and modified
    handling of frequency/latency params.
    Also renamed parent to Parent.

--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76

53 files changed:
python/m5/__init__.py
python/m5/config.py
python/m5/objects/AlphaConsole.mpy [deleted file]
python/m5/objects/AlphaConsole.py [new file with mode: 0644]
python/m5/objects/AlphaFullCPU.mpy [deleted file]
python/m5/objects/AlphaFullCPU.py [new file with mode: 0644]
python/m5/objects/AlphaTLB.mpy [deleted file]
python/m5/objects/AlphaTLB.py [new file with mode: 0644]
python/m5/objects/BadDevice.mpy [deleted file]
python/m5/objects/BadDevice.py [new file with mode: 0644]
python/m5/objects/BaseCPU.mpy [deleted file]
python/m5/objects/BaseCPU.py [new file with mode: 0644]
python/m5/objects/BaseCache.mpy [deleted file]
python/m5/objects/BaseCache.py [new file with mode: 0644]
python/m5/objects/BaseSystem.mpy [deleted file]
python/m5/objects/BaseSystem.py [new file with mode: 0644]
python/m5/objects/Bus.mpy [deleted file]
python/m5/objects/Bus.py [new file with mode: 0644]
python/m5/objects/CoherenceProtocol.mpy [deleted file]
python/m5/objects/CoherenceProtocol.py [new file with mode: 0644]
python/m5/objects/Device.mpy [deleted file]
python/m5/objects/Device.py [new file with mode: 0644]
python/m5/objects/DiskImage.mpy [deleted file]
python/m5/objects/DiskImage.py [new file with mode: 0644]
python/m5/objects/Ethernet.mpy [deleted file]
python/m5/objects/Ethernet.py [new file with mode: 0644]
python/m5/objects/Ide.mpy [deleted file]
python/m5/objects/Ide.py [new file with mode: 0644]
python/m5/objects/IntrControl.mpy [deleted file]
python/m5/objects/IntrControl.py [new file with mode: 0644]
python/m5/objects/MemTest.mpy [deleted file]
python/m5/objects/MemTest.py [new file with mode: 0644]
python/m5/objects/Pci.mpy [deleted file]
python/m5/objects/Pci.py [new file with mode: 0644]
python/m5/objects/PhysicalMemory.mpy [deleted file]
python/m5/objects/PhysicalMemory.py [new file with mode: 0644]
python/m5/objects/Platform.mpy [deleted file]
python/m5/objects/Platform.py [new file with mode: 0644]
python/m5/objects/Process.mpy [deleted file]
python/m5/objects/Process.py [new file with mode: 0644]
python/m5/objects/Repl.mpy [deleted file]
python/m5/objects/Repl.py [new file with mode: 0644]
python/m5/objects/Root.mpy [deleted file]
python/m5/objects/Root.py [new file with mode: 0644]
python/m5/objects/SimConsole.mpy [deleted file]
python/m5/objects/SimConsole.py [new file with mode: 0644]
python/m5/objects/SimpleDisk.mpy [deleted file]
python/m5/objects/SimpleDisk.py [new file with mode: 0644]
python/m5/objects/Tsunami.mpy [deleted file]
python/m5/objects/Tsunami.py [new file with mode: 0644]
python/m5/objects/Uart.mpy [deleted file]
python/m5/objects/Uart.py [new file with mode: 0644]
test/genini.py

index 27bd917499f1a9774e43b8eb36829d62261a376b..5a3c69caa9e100c9f40b9c1cc84440496735856e 100644 (file)
@@ -5,9 +5,12 @@ def panic(string):
     print >>sys.stderr, 'panic:', string
     sys.exit(1)
 
-# the mpy import code is added to the global import meta_path as a
-# side effect of this import
-from mpy_importer import AddToPath, LoadMpyFile
+# Add given directory to system module search path, if it is not
+# already there.
+def AddToPath(path):
+    path = os.path.realpath(path)
+    if os.path.isdir(path) and path not in sys.path:
+        sys.path.append(path)
 
 # find the m5 compile options: must be specified as a dict in
 # __main__.m5_build_env.
@@ -26,12 +29,7 @@ env.update(os.environ)
 
 # import the main m5 config code
 from config import *
-config.add_param_types(config)
 
 # import the built-in object definitions
 from objects import *
-config.add_param_types(objects)
-
-cpp_classes = config.MetaSimObject.cpp_classes
-cpp_classes.sort()
 
index 2db2164fc4564b3a9a6537cdcebcc6a1003a42e5..5da1ba934f7442abc116242179aac383a9400f39 100644 (file)
@@ -1,4 +1,4 @@
-# Copyright (c) 2004 The Regents of The University of Michigan
+# Copyright (c) 2004-2005 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -27,7 +27,8 @@
 from __future__ import generators
 import os, re, sys, types, inspect
 
-from m5 import panic, env
+import m5
+panic = m5.panic
 from convert import *
 from multidict import multidict
 
@@ -50,7 +51,7 @@ class Singleton(type):
 # M5 Python Configuration Utility
 #
 # The basic idea is to write simple Python programs that build Python
-# objects corresponding to M5 SimObjects for the deisred simulation
+# objects corresponding to M5 SimObjects for the desired simulation
 # configuration.  For now, the Python emits a .ini file that can be
 # parsed by M5.  In the future, some tighter integration between M5
 # and the Python interpreter may allow bypassing the .ini file.
@@ -65,13 +66,10 @@ class Singleton(type):
 # object, either using keyword assignment in the constructor or in
 # separate assignment statements.  For example:
 #
-# cache = BaseCache('my_cache', root, size='64KB')
+# cache = BaseCache(size='64KB')
 # cache.hit_latency = 3
 # cache.assoc = 8
 #
-# (The first two constructor arguments specify the name of the created
-# cache and its parent node in the hierarchy.)
-#
 # The magic lies in the mapping of the Python attributes for SimObject
 # classes to the actual SimObject parameter specifications.  This
 # allows parameter validity checking in the Python code.  Continuing
@@ -82,13 +80,6 @@ class Singleton(type):
 # primarily by overriding the special __setattr__ method that controls
 # assignment to object attributes.
 #
-# The Python module provides another class, ConfigNode, which is a
-# superclass of SimObject.  ConfigNode implements the parent/child
-# relationship for building the configuration hierarchy tree.
-# Concrete instances of ConfigNode can be used to group objects in the
-# hierarchy, but do not correspond to SimObjects themselves (like a
-# .ini section with "children=" but no "type=".
-#
 # Once a set of Python objects have been instantiated in a hierarchy,
 # calling 'instantiate(obj)' (where obj is the root of the hierarchy)
 # will generate a .ini file.  See simple-4cpu.py for an example
@@ -140,162 +131,21 @@ class Singleton(type):
 #
 #####################################################################
 
-class Proxy(object):
-    def __init__(self, path):
-        self._object = None
-        if path == 'any':
-            self._path = None
-        else:
-            # path is a list of (attr,index) tuples
-            self._path = [(path,None)]
-        self._index = None
-        self._multiplier = None
-
-    def __getattr__(self, attr):
-        # python uses __bases__ internally for inheritance
-        if attr == '__bases__':
-            return super(Proxy, self).__getattr__(self, attr)
-        if (self._path == None):
-            panic("Can't add attributes to 'any' proxy")
-        self._path.append((attr,None))
-        return self
-
-    def __setattr__(self, attr, value):
-        if not attr.startswith('_'):
-            raise AttributeError, 'cannot set attribute %s' % attr
-        super(Proxy, self).__setattr__(attr, value)
-
-    # support indexing on proxies (e.g., parent.cpu[0])
-    def __getitem__(self, key):
-        if not isinstance(key, int):
-            raise TypeError, "Proxy object requires integer index"
-        if self._path == None:
-            raise IndexError, "Index applied to 'any' proxy"
-        # replace index portion of last path element with new index
-        self._path[-1] = (self._path[-1][0], key)
-        return self
-
-    # support multiplying proxies by constants
-    def __mul__(self, other):
-        if not isinstance(other, (int, float)):
-            raise TypeError, "Proxy multiplier must be integer"
-        if self._multiplier == None:
-            self._multiplier = other
-        else:
-            # support chained multipliers
-            self._multiplier *= other
-        return self
-
-    __rmul__ = __mul__
-
-    def _mulcheck(self, result):
-        if self._multiplier == None:
-            return result
-        if not isinstance(result, int):
-            # this was an error, but for now we'll assume if it's not
-            # an int it must be a Frequency (yuk)
-            result = Frequency._convert(result)
-        # assuming we're dealing with a frequency here, turn it into
-        # a string and give it a 't' suffix so the Frequency._convert
-        # doesn't choke on it later.
-        return ("%d" % int(round((result * self._multiplier)))) + 't'
-
-    def unproxy(self, base, ptype):
-        obj = base
-        done = False
-        while not done:
-            if obj is None:
-                raise AttributeError, \
-                      'Parent of %s type %s not found at path %s' \
-                      % (base.name, ptype, self._path)
-
-            result, done = obj.find(ptype, self._path)
-            obj = obj.parent
-
-        if isinstance(result, Proxy):
-            result = result.unproxy(obj, ptype)
-
-        return self._mulcheck(result)
-
-    def getindex(obj, index):
-        if index == None:
-            return obj
-        try:
-            obj = obj[index]
-        except TypeError:
-            if index != 0:
-                raise
-            # if index is 0 and item is not subscriptable, just
-            # use item itself (so cpu[0] works on uniprocessors)
-        return obj
-    getindex = staticmethod(getindex)
-
-class ProxyFactory(object):
-    def __getattr__(self, attr):
-        return Proxy(attr)
-
-# global object for handling parent.foo proxies
-parent = ProxyFactory()
-
-def isSubClass(value, cls):
-    try:
-        return issubclass(value, cls)
-    except:
-        return False
-
-def isConfigNode(value):
-    try:
-        return issubclass(value, ConfigNode)
-    except:
-        return False
-
 def isSimObject(value):
-    try:
-        return issubclass(value, SimObject)
-    except:
-        return False
+    return isinstance(value, SimObject)
 
 def isSimObjSequence(value):
     if not isinstance(value, (list, tuple)):
         return False
 
     for val in value:
-        if not isNullPointer(val) and not isConfigNode(val):
+        if not isNullPointer(val) and not isSimObject(val):
             return False
 
     return True
 
-def isParamContext(value):
-    try:
-        return issubclass(value, ParamContext)
-    except:
-        return False
-
-class_decorator = 'M5M5_SIMOBJECT_'
-expr_decorator = 'M5M5_EXPRESSION_'
-dot_decorator = '_M5M5_DOT_'
-
-# 'Global' map of legitimate types for SimObject parameters.
-param_types = {}
-
-# Dummy base class to identify types that are legitimate for SimObject
-# parameters.
-class ParamType(object):
-    pass
-
-# Add types defined in given context (dict or module) that are derived
-# from ParamType to param_types map.
-def add_param_types(ctx):
-    if isinstance(ctx, types.DictType):
-        source_dict = ctx
-    elif isinstance(ctx, types.ModuleType):
-        source_dict = ctx.__dict__
-    else:
-        raise TypeError, \
-              "m5.config.add_param_types requires dict or module as arg"
-    for key,val in source_dict.iteritems():
-        if isinstance(val, type) and issubclass(val, ParamType):
-            param_types[key] = val
+def isNullPointer(value):
+    return isinstance(value, NullSimObject)
 
 # The metaclass for ConfigNode (and thus for everything that derives
 # from ConfigNode, including SimObject).  This class controls how new
@@ -303,9 +153,10 @@ def add_param_types(ctx):
 # inherited class behavior (just like a class controls how instances
 # of that class are instantiated, and provides inherited instance
 # behavior).
-class MetaConfigNode(type):
+class MetaSimObject(type):
     # Attributes that can be set only at initialization time
-    init_keywords = {}
+    init_keywords = { 'abstract' : types.BooleanType,
+                      'type' : types.StringType }
     # Attributes that can be set any time
     keywords = { 'check' : types.FunctionType,
                  'children' : types.ListType }
@@ -325,27 +176,32 @@ class MetaConfigNode(type):
                 cls_dict[key] = val
                 del dict[key]
         cls_dict['_init_dict'] = dict
-        return super(MetaConfigNode, mcls).__new__(mcls, name, bases, cls_dict)
+        return super(MetaSimObject, mcls).__new__(mcls, name, bases, cls_dict)
 
     # initialization
     def __init__(cls, name, bases, dict):
-        super(MetaConfigNode, cls).__init__(name, bases, dict)
+        super(MetaSimObject, cls).__init__(name, bases, dict)
 
         # initialize required attributes
         cls._params = multidict()
         cls._values = multidict()
-        cls._param_types = {}
-        cls._bases = [c for c in cls.__mro__ if isConfigNode(c)]
         cls._anon_subclass_counter = 0
 
-        # We don't support multiple inheritence.  If you want to, you
+        # We don't support multiple inheritance.  If you want to, you
         # must fix multidict to deal with it properly.
-        cnbase = [ base for base in bases if isConfigNode(base) ]
-        if len(cnbase) == 1:
+        if len(bases) > 1:
+            raise TypeError, "SimObjects do not support multiple inheritance"
+
+        base = bases[0]
+
+        if isinstance(base, MetaSimObject):
+            cls._params.parent = base._params
+            cls._values.parent = base._values
+
             # If your parent has a value in it that's a config node, clone
             # it.  Do this now so if we update any of the values'
             # attributes we are updating the clone and not the original.
-            for key,val in cnbase[0]._values.iteritems():
+            for key,val in base._values.iteritems():
 
                 # don't clone if (1) we're about to overwrite it with
                 # a local setting or (2) we've already cloned a copy
@@ -353,51 +209,24 @@ class MetaConfigNode(type):
                 if cls._init_dict.has_key(key) or cls._values.has_key(key):
                     continue
 
-                if isConfigNode(val):
+                if isSimObject(val):
                     cls._values[key] = val()
                 elif isSimObjSequence(val) and len(val):
                     cls._values[key] = [ v() for v in val ]
 
-            cls._params.parent = cnbase[0]._params
-            cls._values.parent = cnbase[0]._values
-
-        elif len(cnbase) > 1:
-            panic("""\
-The config hierarchy only supports single inheritence of SimObject
-classes. You're trying to derive from:
-%s""" % str(cnbase))
-
-        # process param types from _init_dict, as these may be needed
-        # by param descriptions also in _init_dict
-        for key,val in cls._init_dict.items():
-            if isinstance(val, type) and issubclass(val, ParamType):
-                cls._param_types[key] = val
-                if not issubclass(val, ConfigNode):
-                    del cls._init_dict[key]
-
         # now process remaining _init_dict items
         for key,val in cls._init_dict.items():
+            if isinstance(val, (types.FunctionType, types.TypeType)):
+                type.__setattr__(cls, key, val)
+
             # param descriptions
-            if isinstance(val, ParamBase):
+            elif isinstance(val, ParamDesc):
                 cls._new_param(key, val)
 
             # init-time-only keywords
             elif cls.init_keywords.has_key(key):
                 cls._set_keyword(key, val, cls.init_keywords[key])
 
-            # See description of decorators in the importer.py file.
-            # We just strip off the expr_decorator now since we don't
-            # need from this point on.
-            elif key.startswith(expr_decorator):
-                key = key[len(expr_decorator):]
-                # because it had dots into a list so that we can find the
-                # proper variable to modify.
-                key = key.split(dot_decorator)
-                c = cls
-                for item in key[:-1]:
-                    c = getattr(c, item)
-                setattr(c, key[-1], val)
-
             # default: use normal path (ends up in __setattr__)
             else:
                 setattr(cls, key, val)
@@ -413,9 +242,7 @@ classes. You're trying to derive from:
     def _new_param(cls, name, value):
         cls._params[name] = value
         if hasattr(value, 'default'):
-            cls._values[name] = value.default
-        # try to resolve local param types in local param_types scope
-        value.maybe_resolve_type(cls._param_types)
+            setattr(cls, name, value.default)
 
     # Set attribute (called on foo.attr = value when foo is an
     # instance of class cls).
@@ -433,341 +260,182 @@ classes. You're trying to derive from:
         param = cls._params.get(attr, None)
         if param:
             # It's ok: set attribute by delegating to 'object' class.
-            # Note the use of param.make_value() to verify/canonicalize
-            # the assigned value
             try:
-                param.valid(value)
+                cls._values[attr] = param.convert(value)
             except Exception, e:
                 msg = "%s\nError setting param %s.%s to %s\n" % \
                       (e, cls.__name__, attr, value)
                 e.args = (msg, )
                 raise
-            cls._values[attr] = value
-        elif isConfigNode(value) or isSimObjSequence(value):
-            cls._values[attr] = value
+        # I would love to get rid of this
+        elif isSimObject(value) or isSimObjSequence(value) or isParamContext(value):
+           cls._values[attr] = value
         else:
             raise AttributeError, \
                   "Class %s has no parameter %s" % (cls.__name__, attr)
 
     def __getattr__(cls, attr):
-        if cls._params.has_key(attr) or cls._values.has_key(attr):
-            return Value(cls, attr)
-
-        if attr == '_cpp_param_decl' and hasattr(cls, 'type'):
-            return cls.type + '*'
+        if cls._values.has_key(attr):
+            return cls._values[attr]
 
         raise AttributeError, \
               "object '%s' has no attribute '%s'" % (cls.__name__, attr)
 
-    def add_child(cls, instance, name, child):
-        if isNullPointer(child) or instance.top_child_names.has_key(name):
-            return
-
-        if isinstance(child, (list, tuple)):
-            kid = []
-            for i,c in enumerate(child):
-                n = '%s%d' % (name, i)
-                k = c.instantiate(n, instance)
-
-                instance.children.append(k)
-                instance.child_names[n] = k
-                instance.child_objects[c] = k
-                kid.append(k)
-        else:
-            kid = child.instantiate(name, instance)
-            instance.children.append(kid)
-            instance.child_names[name] = kid
-            instance.child_objects[child] = kid
-
-        instance.top_child_names[name] = kid
-
-    # Print instance info to .ini file.
-    def instantiate(cls, name, parent = None):
-        instance = Node(name, cls, parent, isParamContext(cls))
-
-        if hasattr(cls, 'check'):
-            cls.check()
-
-        for key,value in cls._values.iteritems():
-            if isConfigNode(value):
-                cls.add_child(instance, key, value)
-            if isinstance(value, (list, tuple)):
-                vals = [ v for v in value if isConfigNode(v) ]
-                if len(vals):
-                    cls.add_child(instance, key, vals)
-
-        for pname,param in cls._params.iteritems():
-            value = cls._values.get(pname, None)
-            if value is None:
-                panic('Error getting %s from %s' % (pname, name))
-
-            try:
-                if isConfigNode(value):
-                    value = instance.child_objects[value]
-                elif isinstance(value, (list, tuple)):
-                    v = []
-                    for val in value:
-                        if isConfigNode(val):
-                            v.append(instance.child_objects[val])
-                        else:
-                            v.append(val)
-                    value = v
-
-                p = NodeParam(pname, param, value)
-                instance.params.append(p)
-                instance.param_names[pname] = p
-            except Exception, e:
-                msg = 'Exception while evaluating %s.%s\n%s' % \
-                      (instance.path, pname, e)
-                e.args = (msg, )
-                raise
-
-        return instance
-
-    def _convert(cls, value):
-        realvalue = value
-        if isinstance(value, Node):
-            realvalue = value.realtype
-
-        if isinstance(realvalue, Proxy):
-            return value
-
-        if realvalue == None or isNullPointer(realvalue):
-            return value
-
-        if isSubClass(realvalue, cls):
-            return value
-
-        raise TypeError, 'object %s type %s wrong type, should be %s' % \
-              (repr(realvalue), realvalue, cls)
-
-    def _string(cls, value):
-        if isNullPointer(value):
-            return 'Null'
-        return Node._string(value)
-
 # The ConfigNode class is the root of the special hierarchy.  Most of
 # the code in this class deals with the configuration hierarchy itself
 # (parent/child node relationships).
-class ConfigNode(object):
-    # Specify metaclass.  Any class inheriting from ConfigNode will
+class SimObject(object):
+    # Specify metaclass.  Any class inheriting from SimObject will
     # get this metaclass.
-    __metaclass__ = MetaConfigNode
-
-    def __new__(cls, **kwargs):
-        name = cls.__name__ + ("_%d" % cls._anon_subclass_counter)
-        cls._anon_subclass_counter += 1
-        return cls.__metaclass__(name, (cls, ), kwargs)
-
-class ParamContext(ConfigNode,ParamType):
-    pass
-
-class MetaSimObject(MetaConfigNode):
-    # init_keywords and keywords are inherited from MetaConfigNode,
-    # with overrides/additions
-    init_keywords = MetaConfigNode.init_keywords
-    init_keywords.update({ 'abstract' : types.BooleanType,
-                           'type' : types.StringType })
-
-    keywords = MetaConfigNode.keywords
-    # no additional keywords
-
-    cpp_classes = []
-
-    # initialization
-    def __init__(cls, name, bases, dict):
-        super(MetaSimObject, cls).__init__(name, bases, dict)
-
-        if hasattr(cls, 'type'):
-            if name == 'SimObject':
-                cls._cpp_base = None
-            elif hasattr(cls._bases[1], 'type'):
-                cls._cpp_base = cls._bases[1].type
-            else:
-                panic("SimObject %s derives from a non-C++ SimObject %s "\
-                      "(no 'type')" % (cls, cls_bases[1].__name__))
-
-            # This class corresponds to a C++ class: put it on the global
-            # list of C++ objects to generate param structs, etc.
-            MetaSimObject.cpp_classes.append(cls)
-
-    def _cpp_decl(cls):
-        name = cls.__name__
-        code = ""
-        code += "\n".join([e.cpp_declare() for e in cls._param_types.values()])
-        code += "\n"
-        param_names = cls._params.keys()
-        param_names.sort()
-        code += "struct Params"
-        if cls._cpp_base:
-            code += " : public %s::Params" % cls._cpp_base
-        code += " {\n    "
-        code += "\n    ".join([cls._params[pname].cpp_decl(pname) \
-                               for pname in param_names])
-        code += "\n};\n"
-        return code
-
-class NodeParam(object):
-    def __init__(self, name, param, value):
-        self.name = name
-        self.param = param
-        self.ptype = param.ptype
-        self.convert = param.convert
-        self.string = param.string
-        self.value = value
-
-class Node(object):
-    all = {}
-    def __init__(self, name, realtype, parent, paramcontext):
-        self.name = name
-        self.realtype = realtype
-        if isSimObject(realtype):
-            self.type = realtype.type
-        else:
-            self.type = None
-        self.parent = parent
-        self.children = []
-        self.child_names = {}
-        self.child_objects = {}
-        self.top_child_names = {}
-        self.params = []
-        self.param_names = {}
-        self.paramcontext = paramcontext
-
-        path = [ self.name ]
-        node = self.parent
-        while node is not None:
-            if node.name != 'root':
-                path.insert(0, node.name)
-            else:
-                assert(node.parent is None)
-            node = node.parent
-        self.path = '.'.join(path)
-
-    def find(self, realtype, path):
-        if not path:
-            if issubclass(self.realtype, realtype):
-                return self, True
-
-            obj = None
-            for child in self.children:
-                if issubclass(child.realtype, realtype):
-                    if obj is not None:
-                        raise AttributeError, \
-                              'parent.any matched more than one: %s %s' % \
-                              (obj.path, child.path)
-                    obj = child
-            for param in self.params:
-                if isConfigNode(param.ptype):
-                    continue
-                if issubclass(param.ptype, realtype):
-                    if obj is not None:
-                        raise AttributeError, \
-                              'parent.any matched more than one: %s' % obj.path
-                    obj = param.value
-            return obj, obj is not None
-
-        try:
-            obj = self
-            for (node,index) in path[:-1]:
-                if obj.child_names.has_key(node):
-                    obj = obj.child_names[node]
-                else:
-                    obj = obj.top_child_names[node]
-                obj = Proxy.getindex(obj, index)
-
-            (last,index) = path[-1]
-            if obj.child_names.has_key(last):
-                value = obj.child_names[last]
-                return Proxy.getindex(value, index), True
-            elif obj.top_child_names.has_key(last):
-                value = obj.top_child_names[last]
-                return Proxy.getindex(value, index), True
-            elif obj.param_names.has_key(last):
-                value = obj.param_names[last]
-                #realtype._convert(value.value)
-                return Proxy.getindex(value.value, index), True
-        except KeyError:
-            pass
-
-        return None, False
-
-    def unproxy(self, param, ptype):
-        if not isinstance(param, Proxy):
-            return param
-        return param.unproxy(self, ptype)
-
-    def fixup(self):
-        self.all[self.path] = self
-
-        for param in self.params:
-            ptype = param.ptype
-            pval = param.value
+    __metaclass__ = MetaSimObject
 
-            try:
-                if isinstance(pval, (list, tuple)):
-                    param.value = [ self.unproxy(pv, ptype) for pv in pval ]
-                else:
-                    param.value = self.unproxy(pval, ptype)
-            except Exception, e:
-                msg = 'Error while fixing up %s:%s\n%s' % \
-                      (self.path, param.name, e)
-                e.args = (msg, )
-                raise
+    def __init__(self, _value_parent = None, **kwargs):
+        self._children = {}
+        if not _value_parent:
+            _value_parent = self.__class__
+        # clone values
+        self._values = multidict(_value_parent._values)
+        for key,val in _value_parent._values.iteritems():
+            if isSimObject(val):
+                setattr(self, key, val())
+            elif isSimObjSequence(val) and len(val):
+                setattr(self, key, [ v() for v in val ])
+        # apply attribute assignments from keyword args, if any
+        for key,val in kwargs.iteritems():
+            setattr(self, key, val)
+
+    def __call__(self, **kwargs):
+        return self.__class__(_value_parent = self, **kwargs)
 
-        for child in self.children:
-            assert(child != self)
-            child.fixup()
+    def __getattr__(self, attr):
+        if self._values.has_key(attr):
+            return self._values[attr]
 
-    # print type and parameter values to .ini file
-    def display(self):
-        print '[' + self.path + ']'    # .ini section header
+        raise AttributeError, "object '%s' has no attribute '%s'" \
+              % (self.__class__.__name__, attr)
 
-        if isSimObject(self.realtype):
-            print 'type = %s' % self.type
+    # Set attribute (called on foo.attr = value when foo is an
+    # instance of class cls).
+    def __setattr__(self, attr, value):
+        # normal processing for private attributes
+        if attr.startswith('_'):
+            object.__setattr__(self, attr, value)
+            return
 
-        if self.children:
-            # instantiate children in same order they were added for
-            # backward compatibility (else we can end up with cpu1
-            # before cpu0).  Changing ordering can also influence timing
-            # in the current memory system, as caches get added to a bus
-            # in different orders which affects their priority in the
-            # case of simulataneous requests.
-            self.children.sort(lambda x,y: cmp(x.name, y.name))
-            children = [ c.name for c in self.children if not c.paramcontext]
-            print 'children =', ' '.join(children)
-
-        self.params.sort(lambda x,y: cmp(x.name, y.name))
-        for param in self.params:
+        # must be SimObject param
+        param = self._params.get(attr, None)
+        if param:
+            # It's ok: set attribute by delegating to 'object' class.
             try:
-                if param.value is None:
-                    raise AttributeError, 'Parameter with no value'
-
-                value = param.convert(param.value)
-                if hasattr(value, 'relative') and value.relative and value:
-                    if param.name == 'cycle_time':
-                        start = self.parent
-                    else:
-                        start = self
-                    val = start.unproxy(parent.cycle_time,
-                                        (Frequency, Latency, ClockPeriod))
-                    value.clock = Frequency._convert(val)
-                string = param.string(value)
+                value = param.convert(value)
             except Exception, e:
-                msg = 'exception in %s:%s=%s\n%s' % (self.path, param.name,
-                                                     value, e)
+                msg = "%s\nError setting param %s.%s to %s\n" % \
+                      (e, self.__class__.__name__, attr, value)
                 e.args = (msg, )
                 raise
+        # I would love to get rid of this
+        elif isSimObject(value) or isSimObjSequence(value) or isParamContext(value):
+            pass
+        else:
+            raise AttributeError, "Class %s has no parameter %s" \
+                  % (self.__class__.__name__, attr)
 
-            print '%s = %s' % (param.name, string)
+        if isSimObject(value):
+            value.set_path(self, attr)
+        elif isSimObjSequence(value):
+            value = SimObjVector(value)
+            [v.set_path(self, "%s%d" % (attr, i)) for i,v in enumerate(value)]
 
-        print
+        self._values[attr] = value
 
-        # recursively dump out children
-        for c in self.children:
-            c.display()
+    # this hack allows tacking a '[0]' onto parameters that may or may
+    # not be vectors, and always getting the first element (e.g. cpus)
+    def __getitem__(self, key):
+        if key == 0:
+            return self
+        raise TypeError, "Non-zero index '%s' to SimObject" % key
+
+    def add_child(self, name, value):
+        self._children[name] = value
+
+    def set_path(self, parent, name):
+        if not hasattr(self, '_parent'):
+            self._parent = parent
+            self._name = name
+            parent.add_child(name, self)
+
+    def path(self):
+        if not hasattr(self, '_parent'):
+            return 'root'
+        ppath = self._parent.path()
+        if ppath == 'root':
+            return self._name
+        return ppath + "." + self._name
 
-    # print type and parameter values to .ini file
+    def __str__(self):
+        return self.path()
+
+    def ini_str(self):
+        return self.path()
+
+    def find_any(self, ptype):
+        if isinstance(self, ptype):
+            return self, True
+
+        found_obj = None
+        for child in self._children.itervalues():
+            if isinstance(child, ptype):
+                if found_obj != None and child != found_obj:
+                    raise AttributeError, \
+                          'parent.any matched more than one: %s %s' % \
+                          (obj.path, child.path)
+                found_obj = child
+        # search param space
+        for pname,pdesc in self._params.iteritems():
+            if issubclass(pdesc.ptype, ptype):
+                match_obj = self._values[pname]
+                if found_obj != None and found_obj != match_obj:
+                    raise AttributeError, \
+                          'parent.any matched more than one: %s' % obj.path
+                found_obj = match_obj
+        return found_obj, found_obj != None
+
+    def print_ini(self):
+        print '[' + self.path() + ']'  # .ini section header
+
+        if hasattr(self, 'type') and not isinstance(self, ParamContext):
+            print 'type =', self.type
+
+        child_names = self._children.keys()
+        child_names.sort()
+        np_child_names = [c for c in child_names \
+                          if not isinstance(self._children[c], ParamContext)]
+        if len(np_child_names):
+            print 'children =', ' '.join(np_child_names)
+
+        param_names = self._params.keys()
+        param_names.sort()
+        for param in param_names:
+            value = self._values.get(param, None)
+            if value != None:
+                if isproxy(value):
+                    try:
+                        value = value.unproxy(self)
+                    except:
+                        print >> sys.stderr, \
+                              "Error in unproxying param '%s' of %s" % \
+                              (param, self.path())
+                        raise
+                    setattr(self, param, value)
+                print param, '=', self._values[param].ini_str()
+
+        print  # blank line between objects
+
+        for child in child_names:
+            self._children[child].print_ini()
+
+    # generate output file for 'dot' to display as a pretty graph.
+    # this code is currently broken.
     def outputDot(self, dot):
         label = "{%s|" % self.path
         if isSimObject(self.realtype):
@@ -786,17 +454,14 @@ class Node(object):
                 if param.value is None:
                     raise AttributeError, 'Parameter with no value'
 
-                value = param.convert(param.value)
-                if param.ptype in (Frequency, Latency, ClockPeriod):
-                    val = self.parent.unproxy(parent.frequency, Frequency)
-                    param.clock = Frequency._convert(val)
+                value = param.value
                 string = param.string(value)
             except Exception, e:
                 msg = 'exception in %s:%s\n%s' % (self.name, param.name, e)
                 e.args = (msg, )
                 raise
 
-            if isConfigNode(param.ptype) and string != "Null":
+            if isSimObject(param.ptype) and string != "Null":
                 simobjs.append(string)
             else:
                 label += '%s = %s\\n' % (param.name, string)
@@ -812,11 +477,166 @@ class Node(object):
         for c in self.children:
             c.outputDot(dot)
 
-    def _string(cls, value):
-        if not isinstance(value, Node):
-            raise AttributeError, 'expecting %s got %s' % (Node, value)
-        return value.path
-    _string = classmethod(_string)
+class ParamContext(SimObject):
+    pass
+
+#####################################################################
+#
+# Proxy object support.
+#
+#####################################################################
+
+class BaseProxy(object):
+    def __init__(self, search_self, search_up):
+        self._search_self = search_self
+        self._search_up = search_up
+        self._multiplier = None
+
+    def __setattr__(self, attr, value):
+        if not attr.startswith('_'):
+            raise AttributeError, 'cannot set attribute on proxy object'
+        super(BaseProxy, self).__setattr__(attr, value)
+
+    # support multiplying proxies by constants
+    def __mul__(self, other):
+        if not isinstance(other, (int, float)):
+            raise TypeError, "Proxy multiplier must be integer"
+        if self._multiplier == None:
+            self._multiplier = other
+        else:
+            # support chained multipliers
+            self._multiplier *= other
+        return self
+
+    __rmul__ = __mul__
+
+    def _mulcheck(self, result):
+        if self._multiplier == None:
+            return result
+        return result * self._multiplier
+
+    def unproxy(self, base):
+        obj = base
+        done = False
+
+        if self._search_self:
+            result, done = self.find(obj)
+
+        if self._search_up:
+            while not done:
+                try: obj = obj._parent
+                except: break
+
+                result, done = self.find(obj)
+
+        if not done:
+            raise AttributeError, "Can't resolve proxy '%s' from '%s'" % \
+                  (self.path(), base.path())
+
+        if isinstance(result, BaseProxy):
+            if result == self:
+                raise RuntimeError, "Cycle in unproxy"
+            result = result.unproxy(obj)
+
+        return self._mulcheck(result)
+
+    def getindex(obj, index):
+        if index == None:
+            return obj
+        try:
+            obj = obj[index]
+        except TypeError:
+            if index != 0:
+                raise
+            # if index is 0 and item is not subscriptable, just
+            # use item itself (so cpu[0] works on uniprocessors)
+        return obj
+    getindex = staticmethod(getindex)
+
+    def set_param_desc(self, pdesc):
+        self._pdesc = pdesc
+
+class AttrProxy(BaseProxy):
+    def __init__(self, search_self, search_up, attr):
+        super(AttrProxy, self).__init__(search_self, search_up)
+        self._attr = attr
+        self._modifiers = []
+
+    def __getattr__(self, attr):
+        # python uses __bases__ internally for inheritance
+        if attr.startswith('_'):
+            return super(AttrProxy, self).__getattr__(self, attr)
+        if hasattr(self, '_pdesc'):
+            raise AttributeError, "Attribute reference on bound proxy"
+        self._modifiers.append(attr)
+        return self
+
+    # support indexing on proxies (e.g., Self.cpu[0])
+    def __getitem__(self, key):
+        if not isinstance(key, int):
+            raise TypeError, "Proxy object requires integer index"
+        self._modifiers.append(key)
+        return self
+
+    def find(self, obj):
+        try:
+            val = getattr(obj, self._attr)
+        except:
+            return None, False
+        while isproxy(val):
+            val = val.unproxy(obj)
+        for m in self._modifiers:
+            if isinstance(m, str):
+                val = getattr(val, m)
+            elif isinstance(m, int):
+                val = val[m]
+            else:
+                assert("Item must be string or integer")
+            while isproxy(val):
+                val = val.unproxy(obj)
+        return val, True
+
+    def path(self):
+        p = self._attr
+        for m in self._modifiers:
+            if isinstance(m, str):
+                p += '.%s' % m
+            elif isinstance(m, int):
+                p += '[%d]' % m
+            else:
+                assert("Item must be string or integer")
+        return p
+
+class AnyProxy(BaseProxy):
+    def find(self, obj):
+        return obj.find_any(self._pdesc.ptype)
+
+    def path(self):
+        return 'any'
+
+def isproxy(obj):
+    if isinstance(obj, BaseProxy):
+        return True
+    elif isinstance(obj, (list, tuple)):
+        for v in obj:
+            if isproxy(v):
+                return True
+    return False
+
+class ProxyFactory(object):
+    def __init__(self, search_self, search_up):
+        self.search_self = search_self
+        self.search_up = search_up
+
+    def __getattr__(self, attr):
+        if attr == 'any':
+            return AnyProxy(self.search_self, self.search_up)
+        else:
+            return AttrProxy(self.search_self, self.search_up, attr)
+
+# global objects for handling proxies
+Parent = ProxyFactory(search_self = False, search_up = True)
+Self = ProxyFactory(search_self = True, search_up = False)
 
 #####################################################################
 #
@@ -835,47 +655,27 @@ class Node(object):
 #
 #####################################################################
 
-def isNullPointer(value):
-    return isinstance(value, NullSimObject)
-
-class Value(object):
-    def __init__(self, obj, attr):
-        super(Value, self).__setattr__('attr', attr)
-        super(Value, self).__setattr__('obj', obj)
-
-    def _getattr(self):
-        return self.obj._values.get(self.attr)
-
-    def __setattr__(self, attr, value):
-        setattr(self._getattr(), attr, value)
-
-    def __getattr__(self, attr):
-        return getattr(self._getattr(), attr)
-
-    def __getitem__(self, index):
-        return self._getattr().__getitem__(index)
-
-    def __call__(self, *args, **kwargs):
-        return self._getattr().__call__(*args, **kwargs)
-
-    def __nonzero__(self):
-        return bool(self._getattr())
+# Dummy base class to identify types that are legitimate for SimObject
+# parameters.
+class ParamValue(object):
 
-    def __str__(self):
-        return str(self._getattr())
+    # default for printing to .ini file is regular string conversion.
+    # will be overridden in some cases
+    def ini_str(self):
+        return str(self)
 
-    def __len__(self):
-        return len(self._getattr())
+    # allows us to blithely call unproxy() on things without checking
+    # if they're really proxies or not
+    def unproxy(self, base):
+        return self
 
-# Regular parameter.
-class ParamBase(object):
-    def __init__(self, ptype, *args, **kwargs):
-        if isinstance(ptype, types.StringType):
-            self.ptype_string = ptype
-        elif isinstance(ptype, type):
+# Regular parameter description.
+class ParamDesc(object):
+    def __init__(self, ptype_str, ptype, *args, **kwargs):
+        self.ptype_str = ptype_str
+        # remember ptype only if it is provided
+        if ptype != None:
             self.ptype = ptype
-        else:
-            raise TypeError, "Param type is not a type (%s)" % ptype
 
         if args:
             if len(args) == 1:
@@ -902,114 +702,94 @@ class ParamBase(object):
         if not hasattr(self, 'desc'):
             raise TypeError, 'desc attribute missing'
 
-    def maybe_resolve_type(self, context):
-        # check if already resolved... don't use hasattr(),
-        # as that calls __getattr__()
-        if self.__dict__.has_key('ptype'):
-            return
-        try:
-            self.ptype = context[self.ptype_string]
-        except KeyError:
-            # no harm in trying... we'll try again later using global scope
-            pass
-
     def __getattr__(self, attr):
         if attr == 'ptype':
             try:
-                self.ptype = param_types[self.ptype_string]
-                return self.ptype
-            except:
-                panic("undefined Param type %s" % self.ptype_string)
-        else:
-            raise AttributeError, "'%s' object has no attribute '%s'" % \
-                  (type(self).__name__, attr)
-
-    def valid(self, value):
-        if not isinstance(value, Proxy):
-            self.ptype._convert(value)
+                ptype = eval(self.ptype_str, m5.__dict__)
+                if not isinstance(ptype, type):
+                    panic("Param qualifier is not a type: %s" % self.ptype)
+                self.ptype = ptype
+                return ptype
+            except NameError:
+                pass
+        raise AttributeError, "'%s' object has no attribute '%s'" % \
+              (type(self).__name__, attr)
 
     def convert(self, value):
-        return self.ptype._convert(value)
-
-    def string(self, value):
-        return self.ptype._string(value)
-
-    def set(self, name, instance, value):
-        instance.__dict__[name] = value
-
-    def cpp_decl(self, name):
-        return '%s %s;' % (self.ptype._cpp_param_decl, name)
-
-class ParamFactory(object):
-    def __init__(self, type):
-        self.ptype = type
-
-    # E.g., Param.Int(5, "number of widgets")
-    def __call__(self, *args, **kwargs):
-        return ParamBase(self.ptype, *args, **kwargs)
-
-    # Strange magic to theoretically allow dotted names as Param classes,
-    # e.g., Param.Foo.Bar(...) to have a param of type Foo.Bar
-    def __getattr__(self, attr):
-        if attr == '__bases__':
-            raise AttributeError, ''
-        cls = type(self)
-        return cls(attr)
-
-    def __setattr__(self, attr, value):
-        if attr != 'ptype':
-            raise AttributeError, \
-                  'Attribute %s not available in %s' % (attr, self.__class__)
-        super(ParamFactory, self).__setattr__(attr, value)
-
-Param = ParamFactory(None)
+        if isinstance(value, BaseProxy):
+            value.set_param_desc(self)
+            return value
+        if not hasattr(self, 'ptype') and isNullPointer(value):
+            # deferred evaluation of SimObject; continue to defer if
+            # we're just assigning a null pointer
+            return value
+        if isinstance(value, self.ptype):
+            return value
+        if isNullPointer(value) and issubclass(self.ptype, SimObject):
+            return value
+        return self.ptype(value)
 
-# Vector-valued parameter description.  Just like Param, except that
-# the value is a vector (list) of the specified type instead of a
+# Vector-valued parameter description.  Just like ParamDesc, except
+# that the value is a vector (list) of the specified type instead of a
 # single value.
-class VectorParamBase(ParamBase):
-    def __init__(self, type, *args, **kwargs):
-        ParamBase.__init__(self, type, *args, **kwargs)
 
-    def valid(self, value):
-        if value == None:
-            return True
+class VectorParamValue(list):
+    def ini_str(self):
+        return ' '.join([str(v) for v in self])
 
-        if isinstance(value, (list, tuple)):
-            for val in value:
-                if not isinstance(val, Proxy):
-                    self.ptype._convert(val)
-        elif not isinstance(value, Proxy):
-            self.ptype._convert(value)
+    def unproxy(self, base):
+        return [v.unproxy(base) for v in self]
+
+class SimObjVector(VectorParamValue):
+    def print_ini(self):
+        for v in self:
+            v.print_ini()
 
+class VectorParamDesc(ParamDesc):
     # Convert assigned value to appropriate type.  If the RHS is not a
     # list or tuple, it generates a single-element list.
     def convert(self, value):
-        if value == None:
-            return []
-
         if isinstance(value, (list, tuple)):
             # list: coerce each element into new list
-            return [ self.ptype._convert(v) for v in value ]
+            tmp_list = [ ParamDesc.convert(self, v) for v in value ]
+            if isSimObjSequence(tmp_list):
+                return SimObjVector(tmp_list)
+            else:
+                return VectorParamValue(tmp_list)
         else:
-            # singleton: coerce & wrap in a list
-            return self.ptype._convert(value)
+            # singleton: leave it be (could coerce to a single-element
+            # list here, but for some historical reason we don't...
+            return ParamDesc.convert(self, value)
 
-    def string(self, value):
-        if isinstance(value, (list, tuple)):
-            return ' '.join([ self.ptype._string(v) for v in value])
-        else:
-            return self.ptype._string(value)
 
-    def cpp_decl(self, name):
-        return 'std::vector<%s> %s;' % (self.ptype._cpp_param_decl, name)
+class ParamFactory(object):
+    def __init__(self, param_desc_class, ptype_str = None):
+        self.param_desc_class = param_desc_class
+        self.ptype_str = ptype_str
+
+    def __getattr__(self, attr):
+        if self.ptype_str:
+            attr = self.ptype_str + '.' + attr
+        return ParamFactory(self.param_desc_class, attr)
 
-class VectorParamFactory(ParamFactory):
-    # E.g., VectorParam.Int(5, "number of widgets")
+    # E.g., Param.Int(5, "number of widgets")
     def __call__(self, *args, **kwargs):
-        return VectorParamBase(self.ptype, *args, **kwargs)
+        caller_frame = inspect.stack()[1][0]
+        ptype = None
+        try:
+            ptype = eval(self.ptype_str,
+                         caller_frame.f_globals, caller_frame.f_locals)
+            if not isinstance(ptype, type):
+                raise TypeError, \
+                      "Param qualifier is not a type: %s" % ptype
+        except NameError:
+            # if name isn't defined yet, assume it's a SimObject, and
+            # try to resolve it later
+            pass
+        return self.param_desc_class(self.ptype_str, ptype, *args, **kwargs)
 
-VectorParam = VectorParamFactory(None)
+Param = ParamFactory(ParamDesc)
+VectorParam = ParamFactory(VectorParamDesc)
 
 #####################################################################
 #
@@ -1025,81 +805,45 @@ VectorParam = VectorParamFactory(None)
 #
 #####################################################################
 
-class MetaRange(type):
-    def __init__(cls, name, bases, dict):
-        super(MetaRange, cls).__init__(name, bases, dict)
-        if name == 'Range':
-            return
-        cls._cpp_param_decl = 'Range<%s>' % cls.type._cpp_param_decl
-
-    def _convert(cls, value):
-        if not isinstance(value, Range):
-            raise TypeError, 'value %s is not a Pair' % value
-        value = cls(value)
-        value.first = cls.type._convert(value.first)
-        value.second = cls.type._convert(value.second)
-        return value
-
-    def _string(cls, value):
-        first = int(value.first)
-        second = int(value.second)
-        if value.extend:
-            second += first
-        if not value.inclusive:
-            second -= 1
-        return '%s:%s' % (cls.type._string(first), cls.type._string(second))
-
-class Range(ParamType):
-    __metaclass__ = MetaRange
+class Range(ParamValue):
+    type = int # default; can be overridden in subclasses
     def __init__(self, *args, **kwargs):
-        if len(args) == 0:
-            self.first = kwargs.pop('start')
 
+        def handle_kwargs(self, kwargs):
             if 'end' in kwargs:
-                self.second = kwargs.pop('end')
-                self.inclusive = True
-                self.extend = False
+                self.second = self.type(kwargs.pop('end'))
             elif 'size' in kwargs:
-                self.second = kwargs.pop('size')
-                self.inclusive = False
-                self.extend = True
+                self.second = self.first + self.type(kwargs.pop('size')) - 1
             else:
                 raise TypeError, "Either end or size must be specified"
 
+        if len(args) == 0:
+            self.first = self.type(kwargs.pop('start'))
+            handle_kwargs(self, kwargs)
+
         elif len(args) == 1:
             if kwargs:
-                self.first = args[0]
-                if 'end' in kwargs:
-                    self.second = kwargs.pop('end')
-                    self.inclusive = True
-                    self.extend = False
-                elif 'size' in kwargs:
-                    self.second = kwargs.pop('size')
-                    self.inclusive = False
-                    self.extend = True
-                else:
-                    raise TypeError, "Either end or size must be specified"
+                self.first = self.type(args[0])
+                handle_kwargs(self, kwargs)
             elif isinstance(args[0], Range):
-                self.first = args[0].first
-                self.second = args[0].second
-                self.inclusive = args[0].inclusive
-                self.extend = args[0].extend
+                self.first = self.type(args[0].first)
+                self.second = self.type(args[0].second)
             else:
-                self.first = 0
-                self.second = args[0]
-                self.inclusive = False
-                self.extend = True
+                self.first = self.type(0)
+                self.second = self.type(args[0]) - 1
 
         elif len(args) == 2:
-            self.first, self.second = args
-            self.inclusive = True
-            self.extend = False
+            self.first = self.type(args[0])
+            self.second = self.type(args[1])
         else:
             raise TypeError, "Too many arguments specified"
 
         if kwargs:
             raise TypeError, "too many keywords: %s" % kwargs.keys()
 
+    def __str__(self):
+        return '%s:%s' % (self.first, self.second)
+
 # Metaclass for bounds-checked integer parameters.  See CheckedInt.
 class CheckedIntType(type):
     def __init__(cls, name, bases, dict):
@@ -1123,72 +867,51 @@ class CheckedIntType(type):
                 cls.min = -(2 ** (cls.size - 1))
                 cls.max = (2 ** (cls.size - 1)) - 1
 
-        cls._cpp_param_decl = cls.cppname
-
-    def _convert(cls, value):
-        if isinstance(value, bool):
-            return int(value)
-
-        if not isinstance(value, (int, long, float, str)):
-            raise TypeError, 'Integer param of invalid type %s' % type(value)
-
-        if isinstance(value, float):
-            value = long(value)
-        elif isinstance(value, str):
-            value = toInteger(value)
-
-        if not cls.min <= value <= cls.max:
-            raise TypeError, 'Integer param out of bounds %d < %d < %d' % \
-                  (cls.min, value, cls.max)
-
-        return value
-
-    def _string(cls, value):
-        return str(value)
-
 # Abstract superclass for bounds-checked integer parameters.  This
 # class is subclassed to generate parameter classes with specific
 # bounds.  Initialization of the min and max bounds is done in the
 # metaclass CheckedIntType.__init__.
-class CheckedInt(long,ParamType):
+class CheckedInt(long,ParamValue):
     __metaclass__ = CheckedIntType
 
-class Int(CheckedInt):      cppname = 'int';      size = 32; unsigned = False
-class Unsigned(CheckedInt): cppname = 'unsigned'; size = 32; unsigned = True
+    def __new__(cls, value):
+        if isinstance(value, str):
+            value = toInteger(value)
+
+        self = long.__new__(cls, value)
+
+        if not cls.min <= self <= cls.max:
+            raise TypeError, 'Integer param out of bounds %d < %d < %d' % \
+                  (cls.min, self, cls.max)
+        return self
 
-class Int8(CheckedInt):     cppname =  'int8_t';  size =  8; unsigned = False
-class UInt8(CheckedInt):    cppname = 'uint8_t';  size =  8; unsigned = True
-class Int16(CheckedInt):    cppname =  'int16_t'; size = 16; unsigned = False
-class UInt16(CheckedInt):   cppname = 'uint16_t'; size = 16; unsigned = True
-class Int32(CheckedInt):    cppname =  'int32_t'; size = 32; unsigned = False
-class UInt32(CheckedInt):   cppname = 'uint32_t'; size = 32; unsigned = True
-class Int64(CheckedInt):    cppname =  'int64_t'; size = 64; unsigned = False
-class UInt64(CheckedInt):   cppname = 'uint64_t'; size = 64; unsigned = True
+class Int(CheckedInt):      size = 32; unsigned = False
+class Unsigned(CheckedInt): size = 32; unsigned = True
 
-class Counter(CheckedInt):  cppname = 'Counter';  size = 64; unsigned = True
-class Tick(CheckedInt):     cppname = 'Tick';     size = 64; unsigned = True
-class TcpPort(CheckedInt):  cppname = 'uint16_t'; size = 16; unsigned = True
-class UdpPort(CheckedInt):  cppname = 'uint16_t'; size = 16; unsigned = True
+class Int8(CheckedInt):     size =  8; unsigned = False
+class UInt8(CheckedInt):    size =  8; unsigned = True
+class Int16(CheckedInt):    size = 16; unsigned = False
+class UInt16(CheckedInt):   size = 16; unsigned = True
+class Int32(CheckedInt):    size = 32; unsigned = False
+class UInt32(CheckedInt):   size = 32; unsigned = True
+class Int64(CheckedInt):    size = 64; unsigned = False
+class UInt64(CheckedInt):   size = 64; unsigned = True
 
-class Percent(CheckedInt):  cppname = 'int'; min = 0; max = 100
+class Counter(CheckedInt):  size = 64; unsigned = True
+class Tick(CheckedInt):     size = 64; unsigned = True
+class TcpPort(CheckedInt):  size = 16; unsigned = True
+class UdpPort(CheckedInt):  size = 16; unsigned = True
+
+class Percent(CheckedInt):  min = 0; max = 100
 
 class MemorySize(CheckedInt):
-    cppname = 'uint64_t'
     size = 64
     unsigned = True
     def __new__(cls, value):
         return super(MemorySize, cls).__new__(cls, toMemorySize(value))
 
-    def _convert(cls, value):
-        return cls(value)
-    _convert = classmethod(_convert)
-
-    def _string(cls, value):
-        return '%d' % value
-    _string = classmethod(_string)
 
 class Addr(CheckedInt):
-    cppname = 'Addr'
     size = 64
     unsigned = True
     def __new__(cls, value):
@@ -1198,56 +921,31 @@ class Addr(CheckedInt):
             value = long(value)
         return super(Addr, cls).__new__(cls, value)
 
-    def _convert(cls, value):
-        return cls(value)
-    _convert = classmethod(_convert)
-
-    def _string(cls, value):
-        return '%d' % value
-    _string = classmethod(_string)
-
 class AddrRange(Range):
     type = Addr
 
-# Boolean parameter type.
-class Bool(ParamType):
-    _cpp_param_decl = 'bool'
+# String-valued parameter.  Just mixin the ParamValue class
+# with the built-in str class.
+class String(ParamValue,str):
+    pass
+
+# Boolean parameter type.  Python doesn't let you subclass bool, since
+# it doesn't want to let you create multiple instances of True and
+# False.  Thus this is a little more complicated than String.
+class Bool(ParamValue):
     def __init__(self, value):
         try:
             self.value = toBool(value)
         except TypeError:
             self.value = bool(value)
 
-    def _convert(cls, value):
-        return cls(value)
-    _convert = classmethod(_convert)
-
-    def _string(cls, value):
-        if value.value:
-            return "true"
-        else:
-            return "false"
-    _string = classmethod(_string)
-
-# String-valued parameter.
-class String(ParamType):
-    _cpp_param_decl = 'string'
-
-    # Constructor.  Value must be Python string.
-    def _convert(cls,value):
-        if value is None:
-            return ''
-        if isinstance(value, str):
-            return value
-
-        raise TypeError, \
-              "String param got value %s %s" % (repr(value), type(value))
-    _convert = classmethod(_convert)
+    def __str__(self):
+        return str(self.value)
 
-    # Generate printable string version.  Not too tricky.
-    def _string(cls, value):
-        return value
-    _string = classmethod(_string)
+    def ini_str(self):
+        if self.value:
+            return 'true'
+        return 'false'
 
 def IncEthernetAddr(addr, val = 1):
     bytes = map(lambda x: int(x, 16), addr.split(':'))
@@ -1269,12 +967,11 @@ class NextEthernetAddr(object):
         self.value = self.addr
         self.addr = IncEthernetAddr(self.addr, inc)
 
-class EthernetAddr(ParamType):
-    _cpp_param_decl = 'EthAddr'
-
-    def _convert(cls, value):
+class EthernetAddr(ParamValue):
+    def __init__(self, value):
         if value == NextEthernetAddr:
-            return value
+            self.value = value
+            return
 
         if not isinstance(value, str):
             raise TypeError, "expected an ethernet address and didn't get one"
@@ -1287,14 +984,12 @@ class EthernetAddr(ParamType):
             if not 0 <= int(byte) <= 256:
                 raise TypeError, 'invalid ethernet address %s' % value
 
-        return value
-    _convert = classmethod(_convert)
+        self.value = value
 
-    def _string(cls, value):
-        if value == NextEthernetAddr:
-            value = value().value
-        return value
-    _string = classmethod(_string)
+    def __str__(self):
+        if self.value == NextEthernetAddr:
+            self.value = self.value().value
+        return self.value
 
 # Special class for NULL pointers.  Note the special check in
 # make_param_value() above that lets these be assigned where a
@@ -1309,20 +1004,8 @@ class NullSimObject(object):
     def _instantiate(self, parent = None, path = ''):
         pass
 
-    def _convert(cls, value):
-        if value == None:
-            return
-
-        if isinstance(value, cls):
-            return value
-
-        raise TypeError, 'object %s %s of the wrong type, should be %s' % \
-              (repr(value), type(value), cls)
-    _convert = classmethod(_convert)
-
-    def _string():
-        return 'NULL'
-    _string = staticmethod(_string)
+    def ini_str(self):
+        return 'Null'
 
 # The only instance you'll ever need...
 Null = NULL = NullSimObject()
@@ -1364,8 +1047,6 @@ class MetaEnum(type):
             raise TypeError, "Enum-derived class must define "\
                   "attribute 'map' or 'vals'"
 
-        cls._cpp_param_decl = name
-
         super(MetaEnum, cls).__init__(name, bases, init_dict)
 
     def cpp_declare(cls):
@@ -1375,180 +1056,148 @@ class MetaEnum(type):
         return s
 
 # Base class for enum types.
-class Enum(ParamType):
+class Enum(ParamValue):
     __metaclass__ = MetaEnum
     vals = []
 
-    def _convert(self, value):
+    def __init__(self, value):
         if value not in self.map:
             raise TypeError, "Enum param got bad value '%s' (not in %s)" \
                   % (value, self.vals)
-        return value
-    _convert = classmethod(_convert)
-
-    # Generate printable string version of value.
-    def _string(self, value):
-        return str(value)
-    _string = classmethod(_string)
-
-root_frequency = None
-
-#
-# "Constants"... handy aliases for various values.
-#
-class RootFrequency(float,ParamType):
-    _cpp_param_decl = 'Tick'
-
-    def __new__(cls, value):
-        return super(cls, RootFrequency).__new__(cls, toFrequency(value))
-
-    def _convert(cls, value):
-        return cls(value)
-    _convert = classmethod(_convert)
-
-    def _string(cls, value):
-        return '%d' % int(round(value))
-    _string = classmethod(_string)
-
-class ClockPeriod(float,ParamType):
-    _cpp_param_decl = 'Tick'
-    def __new__(cls, value):
-        absolute = False
-        relative = False
-        try:
-            val = toClockPeriod(value)
-        except ValueError, e:
-            if value.endswith('f'):
-                val = float(value[:-1])
-                if val:
-                    val = 1 / val
-                relative = True
-            elif value.endswith('c'):
-                val = float(value[:-1])
-                relative = True
-            elif value.endswith('t'):
-                val = float(value[:-1])
-                absolute = True
-            else:
-                raise e
-
-        self = super(cls, ClockPeriod).__new__(cls, val)
-        self.absolute = absolute
-        self.relative = relative
-        return self
+        self.value = value
 
-    def _convert(cls, value):
-        return cls(value)
-    _convert = classmethod(_convert)
+    def __str__(self):
+        return self.value
+
+ticks_per_sec = None
+
+# how big does a rounding error need to be before we warn about it?
+frequency_tolerance = 0.001  # 0.1%
+
+# convert a floting-point # of ticks to integer, and warn if rounding
+# discards too much precision
+def tick_check(float_ticks):
+    if float_ticks == 0:
+        return 0
+    int_ticks = int(round(float_ticks))
+    err = (float_ticks - int_ticks) / float_ticks
+    if err > frequency_tolerance:
+        print >> sys.stderr, "Warning: rounding error > tolerance"
+    return int_ticks
+
+# superclass for "numeric" parameter values, to emulate math
+# operations in a type-safe way.  e.g., a Latency times an int returns
+# a new Latency object.
+class NumericParamValue(ParamValue):
+    def __mul__(self, other):
+        newobj = self.__class__(self)
+        newobj.value *= other
+        return newobj
 
-    def _string(cls, value):
-        if value and not value.absolute:
-            if value.relative:
-                base = root_frequency / value.clock
-            else:
-                base = root_frequency
-            value *= base
+    __rmul__ = __mul__
 
-        return '%d' % int(round(value))
-    _string = classmethod(_string)
+class Latency(NumericParamValue):
+    def __init__(self, value):
+        if isinstance(value, Latency):
+            self.value = value.value
+        elif isinstance(value, Frequency):
+            self.value = 1 / value.value
+        elif isinstance(value, str):
+            try:
+                self.value = toLatency(value)
+            except ValueError:
+                try:
+                    freq = toFrequency(value)
+                except ValueError:
+                    raise ValueError, "Latency value '%s' is neither " \
+                          "frequency nor period" % value
+                self.value = 1 / freq
+        elif value == 0:
+            # the one unitless value that's OK...
+            self.value = value
+        else:
+            raise ValueError, "Invalid Latency value '%s'" % value
 
-class Frequency(float,ParamType):
-    _cpp_param_decl = 'Tick'
+    def __getattr__(self, attr):
+        if attr in ('latency', 'period'):
+            return self
+        if attr == 'frequency':
+            return Frequency(self)
+        raise AttributeError, "Latency object has no attribute '%s'" % attr
 
-    def __new__(cls, value):
-        relative = False
-        try:
-            val = toFrequency(value)
-        except ValueError, e:
-            if value.endswith('f'):
-                val = float(value[:-1])
-                relative = True
-            else:
-                raise e
-        self = super(cls, Frequency).__new__(cls, val)
-        self.relative = relative
-        return self
+    def __str__(self):
+        return str(self.value)
 
-    def _convert(cls, value):
-        return cls(value)
-    _convert = classmethod(_convert)
+    # convert latency to ticks
+    def ini_str(self):
+        return str(tick_check(self.value * ticks_per_sec))
 
-    def _string(cls, value):
-        if value:
-            if value.relative:
-                base = root_frequency / value.clock
-            else:
-                base = root_frequency
+class Frequency(NumericParamValue):
+    def __init__(self, value):
+        if isinstance(value, Frequency):
+            self.value = value.value
+        elif isinstance(value, Latency):
+            self.value = 1 / value.value
+        elif isinstance(value, str):
+            try:
+                self.value = toFrequency(value)
+            except ValueError:
+                try:
+                    freq = toLatency(value)
+                except ValueError:
+                    raise ValueError, "Frequency value '%s' is neither " \
+                          "frequency nor period" % value
+                self.value = 1 / freq
+        else:
+            raise ValueError, "Invalid Frequency value '%s'" % value
 
-            value = base / value
+    def __getattr__(self, attr):
+        if attr == 'frequency':
+            return self
+        if attr in ('latency', 'period'):
+            return Latency(self)
+        raise AttributeError, "Frequency object has no attribute '%s'" % attr
 
-        return '%d' % int(round(value))
-    _string = classmethod(_string)
+    def __str__(self):
+        return str(self.value)
 
-class Latency(float,ParamType):
-    _cpp_param_decl = 'Tick'
-    def __new__(cls, value):
-        absolute = False
-        relative = False
-        try:
-            val = toLatency(value)
-        except ValueError, e:
-            if value.endswith('c'):
-                val = float(value[:-1])
-                relative = True
-            elif value.endswith('t'):
-                val = float(value[:-1])
-                absolute = True
-            else:
-                raise e
-        self = super(cls, Latency).__new__(cls, val)
-        self.absolute = absolute
-        self.relative = relative
-        return self
+    def __float__(self):
+        return float(self.value)
 
-    def _convert(cls, value):
-        return cls(value)
-    _convert = classmethod(_convert)
+    # convert frequency to ticks per period
+    def ini_str(self):
+        return self.period.ini_str()
 
-    def _string(cls, value):
-        if value and not value.absolute:
-            if value.relative:
-                base = root_frequency / value.clock
-            else:
-                base = root_frequency
-            value *= base
-        return '%d' % int(round(value))
-    _string = classmethod(_string)
+# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz)
+class RootFrequency(Frequency):
+    def ini_str(self):
+        return str(tick_check(self.value))
 
-class NetworkBandwidth(float,ParamType):
-    _cpp_param_decl = 'float'
+class NetworkBandwidth(float,ParamValue):
     def __new__(cls, value):
         val = toNetworkBandwidth(value) / 8.0
         return super(cls, NetworkBandwidth).__new__(cls, val)
 
-    def _convert(cls, value):
-        return cls(value)
-    _convert = classmethod(_convert)
+    def __str__(self):
+        return str(self.val)
 
-    def _string(cls, value):
-        value = root_frequency / value
-        return '%f' % value
-    _string = classmethod(_string)
+    def ini_str(self):
+        return '%f' % (ticks_per_sec / self.val)
 
-class MemoryBandwidth(float,ParamType):
-    _cpp_param_decl = 'float'
+class MemoryBandwidth(float,ParamValue):
     def __new__(self, value):
         val = toMemoryBandwidth(value)
         return super(cls, MemoryBandwidth).__new__(cls, val)
 
-    def _convert(cls, value):
-        return cls(value)
-    _convert = classmethod(_convert)
+    def __str__(self):
+        return str(self.val)
+
+    def ini_str(self):
+        return '%f' % (ticks_per_sec / self.val)
 
-    def _string(cls, value):
-        value = root_frequency / value
-        return '%f' % value
-    _string = classmethod(_string)
+#
+# "Constants"... handy aliases for various values.
+#
 
 # Some memory range specifications use this as a default upper bound.
 MaxAddr = Addr.max
@@ -1560,11 +1209,10 @@ AllMemory = AddrRange(0, MaxAddr)
 # The final hook to generate .ini files.  Called from configuration
 # script once config is built.
 def instantiate(root):
-    global root_frequency
-    instance = root.instantiate('root')
-    root_frequency = RootFrequency._convert(root.frequency._getattr())
-    instance.fixup()
-    instance.display()
+    global ticks_per_sec
+    ticks_per_sec = float(root.frequency)
+    root.print_ini()
+    noDot = True # temporary until we fix dot
     if not noDot:
        dot = pydot.Dot()
        instance.outputDot(dot)
@@ -1575,27 +1223,19 @@ def instantiate(root):
        dot.write("config.dot")
        dot.write_ps("config.ps")
 
-# SimObject is a minimal extension of ConfigNode, implementing a
-# hierarchy node that corresponds to an M5 SimObject.  It prints out a
-# "type=" line to indicate its SimObject class, prints out the
-# assigned parameters corresponding to its class, and allows
-# parameters to be set by keyword in the constructor.  Note that most
-# of the heavy lifting for the SimObject param handling is done in the
-# MetaConfigNode metaclass.
-class SimObject(ConfigNode, ParamType):
-    __metaclass__ = MetaSimObject
-    type = 'SimObject'
-
-
 # __all__ defines the list of symbols that get exported when
 # 'from config import *' is invoked.  Try to keep this reasonably
 # short to avoid polluting other namespaces.
-__all__ = ['ConfigNode', 'SimObject', 'ParamContext', 'Param', 'VectorParam',
-           'parent', 'Enum',
+__all__ = ['SimObject', 'ParamContext', 'Param', 'VectorParam',
+           'Parent', 'Self',
+           'Enum', 'Bool', 'String',
            'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
            'Int32', 'UInt32', 'Int64', 'UInt64',
            'Counter', 'Addr', 'Tick', 'Percent',
-           'MemorySize', 'RootFrequency', 'Frequency', 'Latency',
-           'ClockPeriod', 'NetworkBandwidth', 'MemoryBandwidth',
-           'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory', 'NULL',
+           'TcpPort', 'UdpPort', 'EthernetAddr',
+           'MemorySize', 'Latency', 'Frequency', 'RootFrequency',
+           'NetworkBandwidth', 'MemoryBandwidth',
+           'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory',
+           'Null', 'NULL',
            'NextEthernetAddr', 'instantiate']
+
diff --git a/python/m5/objects/AlphaConsole.mpy b/python/m5/objects/AlphaConsole.mpy
deleted file mode 100644 (file)
index 63aea5b..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-from Device import PioDevice
-
-simobj AlphaConsole(PioDevice):
-    type = 'AlphaConsole'
-    cpu = Param.BaseCPU(parent.any, "Processor")
-    disk = Param.SimpleDisk("Simple Disk")
-    num_cpus = Param.Int(1, "Number of CPUs")
-    sim_console = Param.SimConsole(parent.any, "The Simulator Console")
-    system = Param.BaseSystem(parent.any, "system object")
diff --git a/python/m5/objects/AlphaConsole.py b/python/m5/objects/AlphaConsole.py
new file mode 100644 (file)
index 0000000..9fe31b0
--- /dev/null
@@ -0,0 +1,10 @@
+from m5 import *
+from Device import PioDevice
+
+class AlphaConsole(PioDevice):
+    type = 'AlphaConsole'
+    cpu = Param.BaseCPU(Parent.any, "Processor")
+    disk = Param.SimpleDisk("Simple Disk")
+    num_cpus = Param.Int(1, "Number of CPUs")
+    sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
+    system = Param.BaseSystem(Parent.any, "system object")
diff --git a/python/m5/objects/AlphaFullCPU.mpy b/python/m5/objects/AlphaFullCPU.mpy
deleted file mode 100644 (file)
index bf3f2d7..0000000
+++ /dev/null
@@ -1,79 +0,0 @@
-from BaseCPU import BaseCPU
-
-simobj DerivAlphaFullCPU(BaseCPU):
-    type = 'DerivAlphaFullCPU'
-
-    numThreads = Param.Unsigned("number of HW thread contexts")
-
-    if not build_env['FULL_SYSTEM']:
-        mem = Param.FunctionalMemory(NULL, "memory")
-
-    decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
-    renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
-    iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
-               "delay")
-    commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
-    fetchWidth = Param.Unsigned("Fetch width")
-
-    renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
-    iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
-               "delay")
-    commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
-    fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
-    decodeWidth = Param.Unsigned("Decode width")
-
-    iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
-               "delay")
-    commitToRenameDelay = Param.Unsigned("Commit to rename delay")
-    decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
-    renameWidth = Param.Unsigned("Rename width")
-
-    commitToIEWDelay = Param.Unsigned("Commit to "
-               "Issue/Execute/Writeback delay")
-    renameToIEWDelay = Param.Unsigned("Rename to "
-               "Issue/Execute/Writeback delay")
-    issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
-              "to the IEW stage)")
-    issueWidth = Param.Unsigned("Issue width")
-    executeWidth = Param.Unsigned("Execute width")
-    executeIntWidth = Param.Unsigned("Integer execute width")
-    executeFloatWidth = Param.Unsigned("Floating point execute width")
-    executeBranchWidth = Param.Unsigned("Branch execute width")
-    executeMemoryWidth = Param.Unsigned("Memory execute width")
-
-    iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
-               "delay")
-    renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
-    commitWidth = Param.Unsigned("Commit width")
-    squashWidth = Param.Unsigned("Squash width")
-
-    local_predictor_size = Param.Unsigned("Size of local predictor")
-    local_ctr_bits = Param.Unsigned("Bits per counter")
-    local_history_table_size = Param.Unsigned("Size of local history table")
-    local_history_bits = Param.Unsigned("Bits for the local history")
-    global_predictor_size = Param.Unsigned("Size of global predictor")
-    global_ctr_bits = Param.Unsigned("Bits per counter")
-    global_history_bits = Param.Unsigned("Bits of history")
-    choice_predictor_size = Param.Unsigned("Size of choice predictor")
-    choice_ctr_bits = Param.Unsigned("Bits of choice counters")
-
-    BTBEntries = Param.Unsigned("Number of BTB entries")
-    BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
-
-    RASSize = Param.Unsigned("RAS size")
-
-    LQEntries = Param.Unsigned("Number of load queue entries")
-    SQEntries = Param.Unsigned("Number of store queue entries")
-    LFSTSize = Param.Unsigned("Last fetched store table size")
-    SSITSize = Param.Unsigned("Store set ID table size")
-
-    numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
-    numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
-               "registers")
-    numIQEntries = Param.Unsigned("Number of instruction queue entries")
-    numROBEntries = Param.Unsigned("Number of reorder buffer entries")
-
-    instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
-
-    function_trace = Param.Bool(False, "Enable function trace")
-    function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/python/m5/objects/AlphaFullCPU.py b/python/m5/objects/AlphaFullCPU.py
new file mode 100644 (file)
index 0000000..48989d0
--- /dev/null
@@ -0,0 +1,80 @@
+from m5 import *
+from BaseCPU import BaseCPU
+
+class DerivAlphaFullCPU(BaseCPU):
+    type = 'DerivAlphaFullCPU'
+
+    numThreads = Param.Unsigned("number of HW thread contexts")
+
+    if not build_env['FULL_SYSTEM']:
+        mem = Param.FunctionalMemory(NULL, "memory")
+
+    decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
+    renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
+    iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
+               "delay")
+    commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
+    fetchWidth = Param.Unsigned("Fetch width")
+
+    renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
+    iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
+               "delay")
+    commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
+    fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
+    decodeWidth = Param.Unsigned("Decode width")
+
+    iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
+               "delay")
+    commitToRenameDelay = Param.Unsigned("Commit to rename delay")
+    decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
+    renameWidth = Param.Unsigned("Rename width")
+
+    commitToIEWDelay = Param.Unsigned("Commit to "
+               "Issue/Execute/Writeback delay")
+    renameToIEWDelay = Param.Unsigned("Rename to "
+               "Issue/Execute/Writeback delay")
+    issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
+              "to the IEW stage)")
+    issueWidth = Param.Unsigned("Issue width")
+    executeWidth = Param.Unsigned("Execute width")
+    executeIntWidth = Param.Unsigned("Integer execute width")
+    executeFloatWidth = Param.Unsigned("Floating point execute width")
+    executeBranchWidth = Param.Unsigned("Branch execute width")
+    executeMemoryWidth = Param.Unsigned("Memory execute width")
+
+    iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
+               "delay")
+    renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
+    commitWidth = Param.Unsigned("Commit width")
+    squashWidth = Param.Unsigned("Squash width")
+
+    local_predictor_size = Param.Unsigned("Size of local predictor")
+    local_ctr_bits = Param.Unsigned("Bits per counter")
+    local_history_table_size = Param.Unsigned("Size of local history table")
+    local_history_bits = Param.Unsigned("Bits for the local history")
+    global_predictor_size = Param.Unsigned("Size of global predictor")
+    global_ctr_bits = Param.Unsigned("Bits per counter")
+    global_history_bits = Param.Unsigned("Bits of history")
+    choice_predictor_size = Param.Unsigned("Size of choice predictor")
+    choice_ctr_bits = Param.Unsigned("Bits of choice counters")
+
+    BTBEntries = Param.Unsigned("Number of BTB entries")
+    BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
+
+    RASSize = Param.Unsigned("RAS size")
+
+    LQEntries = Param.Unsigned("Number of load queue entries")
+    SQEntries = Param.Unsigned("Number of store queue entries")
+    LFSTSize = Param.Unsigned("Last fetched store table size")
+    SSITSize = Param.Unsigned("Store set ID table size")
+
+    numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
+    numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
+               "registers")
+    numIQEntries = Param.Unsigned("Number of instruction queue entries")
+    numROBEntries = Param.Unsigned("Number of reorder buffer entries")
+
+    instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
+
+    function_trace = Param.Bool(False, "Enable function trace")
+    function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/python/m5/objects/AlphaTLB.mpy b/python/m5/objects/AlphaTLB.mpy
deleted file mode 100644 (file)
index 8e7cd62..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-simobj AlphaTLB(SimObject):
-    type = 'AlphaTLB'
-    abstract = True
-    size = Param.Int("TLB size")
-
-simobj AlphaDTB(AlphaTLB):
-    type = 'AlphaDTB'
-    size = 64
-
-simobj AlphaITB(AlphaTLB):
-    type = 'AlphaITB'
-    size = 48
diff --git a/python/m5/objects/AlphaTLB.py b/python/m5/objects/AlphaTLB.py
new file mode 100644 (file)
index 0000000..5edf8e1
--- /dev/null
@@ -0,0 +1,13 @@
+from m5 import *
+class AlphaTLB(SimObject):
+    type = 'AlphaTLB'
+    abstract = True
+    size = Param.Int("TLB size")
+
+class AlphaDTB(AlphaTLB):
+    type = 'AlphaDTB'
+    size = 64
+
+class AlphaITB(AlphaTLB):
+    type = 'AlphaITB'
+    size = 48
diff --git a/python/m5/objects/BadDevice.mpy b/python/m5/objects/BadDevice.mpy
deleted file mode 100644 (file)
index 35a12e0..0000000
+++ /dev/null
@@ -1,5 +0,0 @@
-from Device import PioDevice
-
-simobj BadDevice(PioDevice):
-    type = 'BadDevice'
-    devicename = Param.String("Name of device to error on")
diff --git a/python/m5/objects/BadDevice.py b/python/m5/objects/BadDevice.py
new file mode 100644 (file)
index 0000000..3fba463
--- /dev/null
@@ -0,0 +1,6 @@
+from m5 import *
+from Device import PioDevice
+
+class BadDevice(PioDevice):
+    type = 'BadDevice'
+    devicename = Param.String("Name of device to error on")
diff --git a/python/m5/objects/BaseCPU.mpy b/python/m5/objects/BaseCPU.mpy
deleted file mode 100644 (file)
index 707d1b9..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-simobj BaseCPU(SimObject):
-    type = 'BaseCPU'
-    abstract = True
-    icache = Param.BaseMem(NULL, "L1 instruction cache object")
-    dcache = Param.BaseMem(NULL, "L1 data cache object")
-
-    if build_env['FULL_SYSTEM']:
-        dtb = Param.AlphaDTB("Data TLB")
-        itb = Param.AlphaITB("Instruction TLB")
-        mem = Param.FunctionalMemory("memory")
-        system = Param.BaseSystem(parent.any, "system object")
-    else:
-        workload = VectorParam.Process("processes to run")
-
-    max_insts_all_threads = Param.Counter(0,
-        "terminate when all threads have reached this inst count")
-    max_insts_any_thread = Param.Counter(0,
-        "terminate when any thread reaches this inst count")
-    max_loads_all_threads = Param.Counter(0,
-        "terminate when all threads have reached this load count")
-    max_loads_any_thread = Param.Counter(0,
-        "terminate when any thread reaches this load count")
-
-    defer_registration = Param.Bool(False,
-        "defer registration with system (for sampling)")
-
-    cycle_time = Param.ClockPeriod(parent.frequency, "clock speed")
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
new file mode 100644 (file)
index 0000000..d4fa13d
--- /dev/null
@@ -0,0 +1,28 @@
+from m5 import *
+class BaseCPU(SimObject):
+    type = 'BaseCPU'
+    abstract = True
+    icache = Param.BaseMem(NULL, "L1 instruction cache object")
+    dcache = Param.BaseMem(NULL, "L1 data cache object")
+
+    if build_env['FULL_SYSTEM']:
+        dtb = Param.AlphaDTB("Data TLB")
+        itb = Param.AlphaITB("Instruction TLB")
+        mem = Param.FunctionalMemory("memory")
+        system = Param.BaseSystem(Parent.any, "system object")
+    else:
+        workload = VectorParam.Process("processes to run")
+
+    max_insts_all_threads = Param.Counter(0,
+        "terminate when all threads have reached this inst count")
+    max_insts_any_thread = Param.Counter(0,
+        "terminate when any thread reaches this inst count")
+    max_loads_all_threads = Param.Counter(0,
+        "terminate when all threads have reached this load count")
+    max_loads_any_thread = Param.Counter(0,
+        "terminate when any thread reaches this load count")
+
+    defer_registration = Param.Bool(False,
+        "defer registration with system (for sampling)")
+
+    cycle_time = Param.Latency(Parent.frequency.latency, "clock speed")
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy
deleted file mode 100644 (file)
index a9a665f..0000000
+++ /dev/null
@@ -1,64 +0,0 @@
-from BaseMem import BaseMem
-
-class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
-
-simobj BaseCache(BaseMem):
-    type = 'BaseCache'
-    adaptive_compression = Param.Bool(False,
-        "Use an adaptive compression scheme")
-    assoc = Param.Int("associativity")
-    block_size = Param.Int("block size in bytes")
-    compressed_bus = Param.Bool(False,
-        "This cache connects to a compressed memory")
-    compression_latency = Param.Latency('0c',
-        "Latency in cycles of compression algorithm")
-    do_copy = Param.Bool(False, "perform fast copies in the cache")
-    hash_delay = Param.Int(1, "time in cycles of hash access")
-    in_bus = Param.Bus(NULL, "incoming bus object")
-    lifo = Param.Bool(False,
-        "whether this NIC partition should use LIFO repl. policy")
-    max_miss_count = Param.Counter(0,
-        "number of misses to handle before calling exit")
-    mem_trace = Param.MemTraceWriter(NULL,
-                                     "memory trace writer to record accesses")
-    mshrs = Param.Int("number of MSHRs (max outstanding requests)")
-    out_bus = Param.Bus("outgoing bus object")
-    prioritizeRequests = Param.Bool(False,
-        "always service demand misses first")
-    protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
-    repl = Param.Repl(NULL, "replacement policy")
-    size = Param.MemorySize("capacity in bytes")
-    split = Param.Bool(False, "whether or not this cache is split")
-    split_size = Param.Int(0,
-        "How many ways of the cache belong to CPU/LRU partition")
-    store_compressed = Param.Bool(False,
-        "Store compressed data in the cache")
-    subblock_size = Param.Int(0,
-        "Size of subblock in IIC used for compression")
-    tgts_per_mshr = Param.Int("max number of accesses per MSHR")
-    trace_addr = Param.Addr(0, "address to trace")
-    two_queue = Param.Bool(False,
-        "whether the lifo should have two queue replacement")
-    write_buffers = Param.Int(8, "number of write buffers")
-    prefetch_miss = Param.Bool(False,
-         "wheter you are using the hardware prefetcher from Miss stream")
-    prefetch_access = Param.Bool(False,
-         "wheter you are using the hardware prefetcher from Access stream")
-    prefetcher_size = Param.Int(100,
-         "Number of entries in the harware prefetch queue")
-    prefetch_past_page = Param.Bool(False,
-         "Allow prefetches to cross virtual page boundaries")
-    prefetch_serial_squash = Param.Bool(False,
-         "Squash prefetches with a later time on a subsequent miss")
-    prefetch_degree = Param.Int(1,
-         "Degree of the prefetch depth")
-    prefetch_latency = Param.Tick(10,
-         "Latency of the prefetcher")
-    prefetch_policy = Param.Prefetch('none',
-         "Type of prefetcher to use")
-    prefetch_cache_check_push = Param.Bool(True,
-         "Check if in cash on push or pop of prefetch queue")
-    prefetch_use_cpu_id = Param.Bool(True,
-         "Use the CPU ID to seperate calculations of prefetches")
-    prefetch_data_accesses_only = Param.Bool(False,
-         "Only prefetch on data not on instruction accesses")
diff --git a/python/m5/objects/BaseCache.py b/python/m5/objects/BaseCache.py
new file mode 100644 (file)
index 0000000..d311969
--- /dev/null
@@ -0,0 +1,65 @@
+from m5 import *
+from BaseMem import BaseMem
+
+class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
+
+class BaseCache(BaseMem):
+    type = 'BaseCache'
+    adaptive_compression = Param.Bool(False,
+        "Use an adaptive compression scheme")
+    assoc = Param.Int("associativity")
+    block_size = Param.Int("block size in bytes")
+    compressed_bus = Param.Bool(False,
+        "This cache connects to a compressed memory")
+    compression_latency = Param.Latency(0,
+        "Latency in cycles of compression algorithm")
+    do_copy = Param.Bool(False, "perform fast copies in the cache")
+    hash_delay = Param.Int(1, "time in cycles of hash access")
+    in_bus = Param.Bus(NULL, "incoming bus object")
+    lifo = Param.Bool(False,
+        "whether this NIC partition should use LIFO repl. policy")
+    max_miss_count = Param.Counter(0,
+        "number of misses to handle before calling exit")
+    mem_trace = Param.MemTraceWriter(NULL,
+                                     "memory trace writer to record accesses")
+    mshrs = Param.Int("number of MSHRs (max outstanding requests)")
+    out_bus = Param.Bus("outgoing bus object")
+    prioritizeRequests = Param.Bool(False,
+        "always service demand misses first")
+    protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
+    repl = Param.Repl(NULL, "replacement policy")
+    size = Param.MemorySize("capacity in bytes")
+    split = Param.Bool(False, "whether or not this cache is split")
+    split_size = Param.Int(0,
+        "How many ways of the cache belong to CPU/LRU partition")
+    store_compressed = Param.Bool(False,
+        "Store compressed data in the cache")
+    subblock_size = Param.Int(0,
+        "Size of subblock in IIC used for compression")
+    tgts_per_mshr = Param.Int("max number of accesses per MSHR")
+    trace_addr = Param.Addr(0, "address to trace")
+    two_queue = Param.Bool(False,
+        "whether the lifo should have two queue replacement")
+    write_buffers = Param.Int(8, "number of write buffers")
+    prefetch_miss = Param.Bool(False,
+         "wheter you are using the hardware prefetcher from Miss stream")
+    prefetch_access = Param.Bool(False,
+         "wheter you are using the hardware prefetcher from Access stream")
+    prefetcher_size = Param.Int(100,
+         "Number of entries in the harware prefetch queue")
+    prefetch_past_page = Param.Bool(False,
+         "Allow prefetches to cross virtual page boundaries")
+    prefetch_serial_squash = Param.Bool(False,
+         "Squash prefetches with a later time on a subsequent miss")
+    prefetch_degree = Param.Int(1,
+         "Degree of the prefetch depth")
+    prefetch_latency = Param.Tick(10,
+         "Latency of the prefetcher")
+    prefetch_policy = Param.Prefetch('none',
+         "Type of prefetcher to use")
+    prefetch_cache_check_push = Param.Bool(True,
+         "Check if in cash on push or pop of prefetch queue")
+    prefetch_use_cpu_id = Param.Bool(True,
+         "Use the CPU ID to seperate calculations of prefetches")
+    prefetch_data_accesses_only = Param.Bool(False,
+         "Only prefetch on data not on instruction accesses")
diff --git a/python/m5/objects/BaseSystem.mpy b/python/m5/objects/BaseSystem.mpy
deleted file mode 100644 (file)
index 29fe3e1..0000000
+++ /dev/null
@@ -1,17 +0,0 @@
-simobj BaseSystem(SimObject):
-    type = 'BaseSystem'
-    abstract = True
-    boot_cpu_frequency = Param.ClockPeriod(parent.cpu[0].cycle_time,
-        "Boot Processor Frequency")
-    memctrl = Param.MemoryController(parent.any, "memory controller")
-    physmem = Param.PhysicalMemory(parent.any, "phsyical memory")
-    kernel = Param.String("file that contains the kernel code")
-    console = Param.String("file that contains the console code")
-    pal = Param.String("file that contains palcode")
-    readfile = Param.String("", "file to read startup script from")
-    init_param = Param.UInt64(0, "numerical value to pass into simulator")
-    boot_osflags = Param.String("a", "boot flags to pass to the kernel")
-    system_type = Param.UInt64("Type of system we are emulating")
-    system_rev = Param.UInt64("Revision of system we are emulating")
-    bin = Param.Bool(False, "is this system binned")
-    binned_fns = VectorParam.String([], "functions broken down and binned")
diff --git a/python/m5/objects/BaseSystem.py b/python/m5/objects/BaseSystem.py
new file mode 100644 (file)
index 0000000..48c70e4
--- /dev/null
@@ -0,0 +1,18 @@
+from m5 import *
+class BaseSystem(SimObject):
+    type = 'BaseSystem'
+    abstract = True
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].cycle_time.frequency,
+                                         "boot processor frequency")
+    memctrl = Param.MemoryController(Parent.any, "memory controller")
+    physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+    kernel = Param.String("file that contains the kernel code")
+    console = Param.String("file that contains the console code")
+    pal = Param.String("file that contains palcode")
+    readfile = Param.String("", "file to read startup script from")
+    init_param = Param.UInt64(0, "numerical value to pass into simulator")
+    boot_osflags = Param.String("a", "boot flags to pass to the kernel")
+    system_type = Param.UInt64("Type of system we are emulating")
+    system_rev = Param.UInt64("Revision of system we are emulating")
+    bin = Param.Bool(False, "is this system binned")
+    binned_fns = VectorParam.String([], "functions broken down and binned")
diff --git a/python/m5/objects/Bus.mpy b/python/m5/objects/Bus.mpy
deleted file mode 100644 (file)
index aa12f75..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-from BaseHier import BaseHier
-
-simobj Bus(BaseHier):
-    type = 'Bus'
-    clock_ratio = Param.ClockPeriod("ratio of CPU to bus frequency")
-    width = Param.Int("bus width in bytes")
diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py
new file mode 100644 (file)
index 0000000..1ed87d2
--- /dev/null
@@ -0,0 +1,7 @@
+from m5 import *
+from BaseHier import BaseHier
+
+class Bus(BaseHier):
+    type = 'Bus'
+    clock_ratio = Param.Frequency("ratio of CPU to bus frequency")
+    width = Param.Int("bus width in bytes")
diff --git a/python/m5/objects/CoherenceProtocol.mpy b/python/m5/objects/CoherenceProtocol.mpy
deleted file mode 100644 (file)
index f3b0026..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
-
-simobj CoherenceProtocol(SimObject):
-    type = 'CoherenceProtocol'
-    do_upgrades = Param.Bool(True, "use upgrade transactions?")
-    protocol = Param.Coherence("name of coherence protocol")
diff --git a/python/m5/objects/CoherenceProtocol.py b/python/m5/objects/CoherenceProtocol.py
new file mode 100644 (file)
index 0000000..7013000
--- /dev/null
@@ -0,0 +1,7 @@
+from m5 import *
+class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
+
+class CoherenceProtocol(SimObject):
+    type = 'CoherenceProtocol'
+    do_upgrades = Param.Bool(True, "use upgrade transactions?")
+    protocol = Param.Coherence("name of coherence protocol")
diff --git a/python/m5/objects/Device.mpy b/python/m5/objects/Device.mpy
deleted file mode 100644 (file)
index a0d02a6..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-from FunctionalMemory import FunctionalMemory
-
-# This device exists only because there are some devices that I don't
-# want to have a Platform parameter because it would cause a cycle in
-# the C++ that cannot be easily solved.
-#
-# The real solution to this problem is to pass the ParamXXX structure
-# to the constructor, but with the express condition that SimObject
-# parameter values are not to be available at construction time.  If
-# some further configuration must be done, it must be done during the
-# initialization phase at which point all SimObject pointers will be
-# valid.
-simobj FooPioDevice(FunctionalMemory):
-    type = 'PioDevice'
-    abstract = True
-    addr = Param.Addr("Device Address")
-    mmu = Param.MemoryController(parent.any, "Memory Controller")
-    io_bus = Param.Bus(NULL, "The IO Bus to attach to")
-    pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
-
-simobj FooDmaDevice(FooPioDevice):
-    type = 'DmaDevice'
-    abstract = True
-
-simobj PioDevice(FooPioDevice):
-    type = 'PioDevice'
-    abstract = True
-    platform = Param.Platform(parent.any, "Platform")
-
-simobj DmaDevice(PioDevice):
-    type = 'DmaDevice'
-    abstract = True
-
diff --git a/python/m5/objects/Device.py b/python/m5/objects/Device.py
new file mode 100644 (file)
index 0000000..7f6ccd3
--- /dev/null
@@ -0,0 +1,34 @@
+from m5 import *
+from FunctionalMemory import FunctionalMemory
+
+# This device exists only because there are some devices that I don't
+# want to have a Platform parameter because it would cause a cycle in
+# the C++ that cannot be easily solved.
+#
+# The real solution to this problem is to pass the ParamXXX structure
+# to the constructor, but with the express condition that SimObject
+# parameter values are not to be available at construction time.  If
+# some further configuration must be done, it must be done during the
+# initialization phase at which point all SimObject pointers will be
+# valid.
+class FooPioDevice(FunctionalMemory):
+    type = 'PioDevice'
+    abstract = True
+    addr = Param.Addr("Device Address")
+    mmu = Param.MemoryController(Parent.any, "Memory Controller")
+    io_bus = Param.Bus(NULL, "The IO Bus to attach to")
+    pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
+
+class FooDmaDevice(FooPioDevice):
+    type = 'DmaDevice'
+    abstract = True
+
+class PioDevice(FooPioDevice):
+    type = 'PioDevice'
+    abstract = True
+    platform = Param.Platform(Parent.any, "Platform")
+
+class DmaDevice(PioDevice):
+    type = 'DmaDevice'
+    abstract = True
+
diff --git a/python/m5/objects/DiskImage.mpy b/python/m5/objects/DiskImage.mpy
deleted file mode 100644 (file)
index 80ef7b0..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-simobj DiskImage(SimObject):
-    type = 'DiskImage'
-    abstract = True
-    image_file = Param.String("disk image file")
-    read_only = Param.Bool(False, "read only image")
-
-simobj RawDiskImage(DiskImage):
-    type = 'RawDiskImage'
-
-simobj CowDiskImage(DiskImage):
-    type = 'CowDiskImage'
-    child = Param.DiskImage("child image")
-    table_size = Param.Int(65536, "initial table size")
-    image_file = ''
diff --git a/python/m5/objects/DiskImage.py b/python/m5/objects/DiskImage.py
new file mode 100644 (file)
index 0000000..0d55e93
--- /dev/null
@@ -0,0 +1,15 @@
+from m5 import *
+class DiskImage(SimObject):
+    type = 'DiskImage'
+    abstract = True
+    image_file = Param.String("disk image file")
+    read_only = Param.Bool(False, "read only image")
+
+class RawDiskImage(DiskImage):
+    type = 'RawDiskImage'
+
+class CowDiskImage(DiskImage):
+    type = 'CowDiskImage'
+    child = Param.DiskImage("child image")
+    table_size = Param.Int(65536, "initial table size")
+    image_file = ''
diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy
deleted file mode 100644 (file)
index 0065a23..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-from Device import DmaDevice
-from Pci import PciDevice
-
-simobj EtherInt(SimObject):
-    type = 'EtherInt'
-    abstract = True
-    peer = Param.EtherInt(NULL, "peer interface")
-
-simobj EtherLink(SimObject):
-    type = 'EtherLink'
-    int1 = Param.EtherInt("interface 1")
-    int2 = Param.EtherInt("interface 2")
-    delay = Param.Latency('0us', "packet transmit delay")
-    speed = Param.NetworkBandwidth('100Mbps', "link speed")
-    dump = Param.EtherDump(NULL, "dump object")
-
-simobj EtherBus(SimObject):
-    type = 'EtherBus'
-    loopback = Param.Bool(True, "send packet back to the sending interface")
-    dump = Param.EtherDump(NULL, "dump object")
-    speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
-
-simobj EtherTap(EtherInt):
-    type = 'EtherTap'
-    bufsz = Param.Int(10000, "tap buffer size")
-    dump = Param.EtherDump(NULL, "dump object")
-    port = Param.UInt16(3500, "tap port")
-
-simobj EtherDump(SimObject):
-    type = 'EtherDump'
-    file = Param.String("dump file")
-
-simobj EtherDev(DmaDevice):
-    type = 'EtherDev'
-    hardware_address = Param.EthernetAddr(NextEthernetAddr,
-        "Ethernet Hardware Address")
-
-    dma_data_free = Param.Bool(False, "DMA of Data is free")
-    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
-    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
-    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
-    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
-    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
-    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
-
-    rx_filter = Param.Bool(True, "Enable Receive Filter")
-    rx_delay = Param.Latency('1us', "Receive Delay")
-    tx_delay = Param.Latency('1us', "Transmit Delay")
-
-    intr_delay = Param.Latency('0us', "Interrupt Delay")
-    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
-    physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
-    tlaser = Param.Turbolaser(parent.any, "Turbolaser")
-
-simobj NSGigE(PciDevice):
-    type = 'NSGigE'
-    hardware_address = Param.EthernetAddr(NextEthernetAddr,
-        "Ethernet Hardware Address")
-
-    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
-
-    dma_data_free = Param.Bool(False, "DMA of Data is free")
-    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
-    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
-    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
-    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
-    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
-    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
-
-
-    rx_filter = Param.Bool(True, "Enable Receive Filter")
-    rx_delay = Param.Latency('1us', "Receive Delay")
-    tx_delay = Param.Latency('1us', "Transmit Delay")
-
-    rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
-    tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
-
-    m5reg = Param.UInt32(0, "Register for m5 usage")
-
-    intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
-    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
-    physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
-
-simobj EtherDevInt(EtherInt):
-    type = 'EtherDevInt'
-    device = Param.EtherDev("Ethernet device of this interface")
-
-simobj NSGigEInt(EtherInt):
-    type = 'NSGigEInt'
-    device = Param.NSGigE("Ethernet device of this interface")
-
-simobj Sinic(PciDevice):
-    type = 'Sinic'
-    hardware_address = Param.EthernetAddr(NextEthernetAddr,
-        "Ethernet Hardware Address")
-
-    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
-
-    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
-    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
-    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
-    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
-
-    rx_filter = Param.Bool(True, "Enable Receive Filter")
-    rx_delay = Param.Latency('1us', "Receive Delay")
-    tx_delay = Param.Latency('1us', "Transmit Delay")
-
-    rx_max_copy = Param.MemorySize('16kB', "rx max copy")
-    tx_max_copy = Param.MemorySize('16kB', "tx max copy")
-    rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo")
-    tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo")
-    rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
-    tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")
-
-    intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
-    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
-    physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
-
-simobj SinicInt(EtherInt):
-    type = 'SinicInt'
-    device = Param.Sinic("Ethernet device of this interface")
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
new file mode 100644 (file)
index 0000000..69dec15
--- /dev/null
@@ -0,0 +1,122 @@
+from m5 import *
+from Device import DmaDevice
+from Pci import PciDevice
+
+class EtherInt(SimObject):
+    type = 'EtherInt'
+    abstract = True
+    peer = Param.EtherInt(NULL, "peer interface")
+
+class EtherLink(SimObject):
+    type = 'EtherLink'
+    int1 = Param.EtherInt("interface 1")
+    int2 = Param.EtherInt("interface 2")
+    delay = Param.Latency('0us', "packet transmit delay")
+    speed = Param.NetworkBandwidth('100Mbps', "link speed")
+    dump = Param.EtherDump(NULL, "dump object")
+
+class EtherBus(SimObject):
+    type = 'EtherBus'
+    loopback = Param.Bool(True, "send packet back to the sending interface")
+    dump = Param.EtherDump(NULL, "dump object")
+    speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
+
+class EtherTap(EtherInt):
+    type = 'EtherTap'
+    bufsz = Param.Int(10000, "tap buffer size")
+    dump = Param.EtherDump(NULL, "dump object")
+    port = Param.UInt16(3500, "tap port")
+
+class EtherDump(SimObject):
+    type = 'EtherDump'
+    file = Param.String("dump file")
+
+class EtherDev(DmaDevice):
+    type = 'EtherDev'
+    hardware_address = Param.EthernetAddr(NextEthernetAddr,
+        "Ethernet Hardware Address")
+
+    dma_data_free = Param.Bool(False, "DMA of Data is free")
+    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
+    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
+    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
+
+    rx_filter = Param.Bool(True, "Enable Receive Filter")
+    rx_delay = Param.Latency('1us', "Receive Delay")
+    tx_delay = Param.Latency('1us', "Transmit Delay")
+
+    intr_delay = Param.Latency('0us', "Interrupt Delay")
+    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+    tlaser = Param.Turbolaser(Parent.any, "Turbolaser")
+
+class NSGigE(PciDevice):
+    type = 'NSGigE'
+    hardware_address = Param.EthernetAddr(NextEthernetAddr,
+        "Ethernet Hardware Address")
+
+    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+
+    dma_data_free = Param.Bool(False, "DMA of Data is free")
+    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
+    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
+    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
+
+
+    rx_filter = Param.Bool(True, "Enable Receive Filter")
+    rx_delay = Param.Latency('1us', "Receive Delay")
+    tx_delay = Param.Latency('1us', "Transmit Delay")
+
+    rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
+    tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
+
+    m5reg = Param.UInt32(0, "Register for m5 usage")
+
+    intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
+    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+
+class EtherDevInt(EtherInt):
+    type = 'EtherDevInt'
+    device = Param.EtherDev("Ethernet device of this interface")
+
+class NSGigEInt(EtherInt):
+    type = 'NSGigEInt'
+    device = Param.NSGigE("Ethernet device of this interface")
+
+class Sinic(PciDevice):
+    type = 'Sinic'
+    hardware_address = Param.EthernetAddr(NextEthernetAddr,
+        "Ethernet Hardware Address")
+
+    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+
+    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
+
+    rx_filter = Param.Bool(True, "Enable Receive Filter")
+    rx_delay = Param.Latency('1us', "Receive Delay")
+    tx_delay = Param.Latency('1us', "Transmit Delay")
+
+    rx_max_copy = Param.MemorySize('16kB', "rx max copy")
+    tx_max_copy = Param.MemorySize('16kB', "tx max copy")
+    rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo")
+    tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo")
+    rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
+    tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")
+
+    intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
+    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+
+class SinicInt(EtherInt):
+    type = 'SinicInt'
+    device = Param.Sinic("Ethernet device of this interface")
diff --git a/python/m5/objects/Ide.mpy b/python/m5/objects/Ide.mpy
deleted file mode 100644 (file)
index 02b1d95..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-from Pci import PciDevice
-
-class IdeID(Enum): vals = ['master', 'slave']
-
-simobj IdeDisk(SimObject):
-    type = 'IdeDisk'
-    delay = Param.Latency('1us', "Fixed disk delay in microseconds")
-    driveID = Param.IdeID('master', "Drive ID")
-    image = Param.DiskImage("Disk image")
-    physmem = Param.PhysicalMemory(parent.any, "Physical memory")
-
-simobj IdeController(PciDevice):
-    type = 'IdeController'
-    disks = VectorParam.IdeDisk("IDE disks attached to this controller")
diff --git a/python/m5/objects/Ide.py b/python/m5/objects/Ide.py
new file mode 100644 (file)
index 0000000..6855ec6
--- /dev/null
@@ -0,0 +1,15 @@
+from m5 import *
+from Pci import PciDevice
+
+class IdeID(Enum): vals = ['master', 'slave']
+
+class IdeDisk(SimObject):
+    type = 'IdeDisk'
+    delay = Param.Latency('1us', "Fixed disk delay in microseconds")
+    driveID = Param.IdeID('master', "Drive ID")
+    image = Param.DiskImage("Disk image")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical memory")
+
+class IdeController(PciDevice):
+    type = 'IdeController'
+    disks = VectorParam.IdeDisk("IDE disks attached to this controller")
diff --git a/python/m5/objects/IntrControl.mpy b/python/m5/objects/IntrControl.mpy
deleted file mode 100644 (file)
index 144be0f..0000000
+++ /dev/null
@@ -1,3 +0,0 @@
-simobj IntrControl(SimObject):
-    type = 'IntrControl'
-    cpu = Param.BaseCPU(parent.any, "the cpu")
diff --git a/python/m5/objects/IntrControl.py b/python/m5/objects/IntrControl.py
new file mode 100644 (file)
index 0000000..66c82c1
--- /dev/null
@@ -0,0 +1,4 @@
+from m5 import *
+class IntrControl(SimObject):
+    type = 'IntrControl'
+    cpu = Param.BaseCPU(Parent.any, "the cpu")
diff --git a/python/m5/objects/MemTest.mpy b/python/m5/objects/MemTest.mpy
deleted file mode 100644 (file)
index af14ed9..0000000
+++ /dev/null
@@ -1,18 +0,0 @@
-simobj MemTest(SimObject):
-    type = 'MemTest'
-    cache = Param.BaseCache("L1 cache")
-    check_mem = Param.FunctionalMemory("check memory")
-    main_mem = Param.FunctionalMemory("hierarchical memory")
-    max_loads = Param.Counter("number of loads to execute")
-    memory_size = Param.Int(65536, "memory size")
-    percent_copies = Param.Percent(0, "target copy percentage")
-    percent_dest_unaligned = Param.Percent(50,
-        "percent of copy dest address that are unaligned")
-    percent_reads = Param.Percent(65, "target read percentage")
-    percent_source_unaligned = Param.Percent(50,
-        "percent of copy source address that are unaligned")
-    percent_uncacheable = Param.Percent(10,
-        "target uncacheable percentage")
-    progress_interval = Param.Counter(1000000,
-        "progress report interval (in accesses)")
-    trace_addr = Param.Addr(0, "address to trace")
diff --git a/python/m5/objects/MemTest.py b/python/m5/objects/MemTest.py
new file mode 100644 (file)
index 0000000..34299fa
--- /dev/null
@@ -0,0 +1,19 @@
+from m5 import *
+class MemTest(SimObject):
+    type = 'MemTest'
+    cache = Param.BaseCache("L1 cache")
+    check_mem = Param.FunctionalMemory("check memory")
+    main_mem = Param.FunctionalMemory("hierarchical memory")
+    max_loads = Param.Counter("number of loads to execute")
+    memory_size = Param.Int(65536, "memory size")
+    percent_copies = Param.Percent(0, "target copy percentage")
+    percent_dest_unaligned = Param.Percent(50,
+        "percent of copy dest address that are unaligned")
+    percent_reads = Param.Percent(65, "target read percentage")
+    percent_source_unaligned = Param.Percent(50,
+        "percent of copy source address that are unaligned")
+    percent_uncacheable = Param.Percent(10,
+        "target uncacheable percentage")
+    progress_interval = Param.Counter(1000000,
+        "progress report interval (in accesses)")
+    trace_addr = Param.Addr(0, "address to trace")
diff --git a/python/m5/objects/Pci.mpy b/python/m5/objects/Pci.mpy
deleted file mode 100644 (file)
index b9b3e5a..0000000
+++ /dev/null
@@ -1,51 +0,0 @@
-from Device import FooPioDevice, DmaDevice
-
-simobj PciConfigData(SimObject):
-    type = 'PciConfigData'
-    VendorID = Param.UInt16("Vendor ID")
-    DeviceID = Param.UInt16("Device ID")
-    Command = Param.UInt16(0, "Command")
-    Status = Param.UInt16(0, "Status")
-    Revision = Param.UInt8(0, "Device")
-    ProgIF = Param.UInt8(0, "Programming Interface")
-    SubClassCode = Param.UInt8(0, "Sub-Class Code")
-    ClassCode = Param.UInt8(0, "Class Code")
-    CacheLineSize = Param.UInt8(0, "System Cacheline Size")
-    LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
-    HeaderType = Param.UInt8(0, "PCI Header Type")
-    BIST = Param.UInt8(0, "Built In Self Test")
-
-    BAR0 = Param.UInt32(0x00, "Base Address Register 0")
-    BAR1 = Param.UInt32(0x00, "Base Address Register 1")
-    BAR2 = Param.UInt32(0x00, "Base Address Register 2")
-    BAR3 = Param.UInt32(0x00, "Base Address Register 3")
-    BAR4 = Param.UInt32(0x00, "Base Address Register 4")
-    BAR5 = Param.UInt32(0x00, "Base Address Register 5")
-    BAR0Size = Param.UInt32(0, "Base Address Register 0 Size")
-    BAR1Size = Param.UInt32(0, "Base Address Register 1 Size")
-    BAR2Size = Param.UInt32(0, "Base Address Register 2 Size")
-    BAR3Size = Param.UInt32(0, "Base Address Register 3 Size")
-    BAR4Size = Param.UInt32(0, "Base Address Register 4 Size")
-    BAR5Size = Param.UInt32(0, "Base Address Register 5 Size")
-
-    CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
-    SubsystemID = Param.UInt16(0x00, "Subsystem ID")
-    SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
-    ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
-    InterruptLine = Param.UInt8(0x00, "Interrupt Line")
-    InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
-    MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
-    MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
-
-simobj PciConfigAll(FooPioDevice):
-    type = 'PciConfigAll'
-
-simobj PciDevice(DmaDevice):
-    type = 'PciDevice'
-    abstract = True
-    addr = 0xffffffffL
-    pci_bus = Param.Int("PCI bus")
-    pci_dev = Param.Int("PCI device number")
-    pci_func = Param.Int("PCI function code")
-    configdata = Param.PciConfigData(parent.any, "PCI Config data")
-    configspace = Param.PciConfigAll(parent.any, "PCI Configspace")
diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py
new file mode 100644 (file)
index 0000000..0957e28
--- /dev/null
@@ -0,0 +1,52 @@
+from m5 import *
+from Device import FooPioDevice, DmaDevice
+
+class PciConfigData(SimObject):
+    type = 'PciConfigData'
+    VendorID = Param.UInt16("Vendor ID")
+    DeviceID = Param.UInt16("Device ID")
+    Command = Param.UInt16(0, "Command")
+    Status = Param.UInt16(0, "Status")
+    Revision = Param.UInt8(0, "Device")
+    ProgIF = Param.UInt8(0, "Programming Interface")
+    SubClassCode = Param.UInt8(0, "Sub-Class Code")
+    ClassCode = Param.UInt8(0, "Class Code")
+    CacheLineSize = Param.UInt8(0, "System Cacheline Size")
+    LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
+    HeaderType = Param.UInt8(0, "PCI Header Type")
+    BIST = Param.UInt8(0, "Built In Self Test")
+
+    BAR0 = Param.UInt32(0x00, "Base Address Register 0")
+    BAR1 = Param.UInt32(0x00, "Base Address Register 1")
+    BAR2 = Param.UInt32(0x00, "Base Address Register 2")
+    BAR3 = Param.UInt32(0x00, "Base Address Register 3")
+    BAR4 = Param.UInt32(0x00, "Base Address Register 4")
+    BAR5 = Param.UInt32(0x00, "Base Address Register 5")
+    BAR0Size = Param.UInt32(0, "Base Address Register 0 Size")
+    BAR1Size = Param.UInt32(0, "Base Address Register 1 Size")
+    BAR2Size = Param.UInt32(0, "Base Address Register 2 Size")
+    BAR3Size = Param.UInt32(0, "Base Address Register 3 Size")
+    BAR4Size = Param.UInt32(0, "Base Address Register 4 Size")
+    BAR5Size = Param.UInt32(0, "Base Address Register 5 Size")
+
+    CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
+    SubsystemID = Param.UInt16(0x00, "Subsystem ID")
+    SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
+    ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
+    InterruptLine = Param.UInt8(0x00, "Interrupt Line")
+    InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
+    MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
+    MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
+
+class PciConfigAll(FooPioDevice):
+    type = 'PciConfigAll'
+
+class PciDevice(DmaDevice):
+    type = 'PciDevice'
+    abstract = True
+    addr = 0xffffffffL
+    pci_bus = Param.Int("PCI bus")
+    pci_dev = Param.Int("PCI device number")
+    pci_func = Param.Int("PCI function code")
+    configdata = Param.PciConfigData(Parent.any, "PCI Config data")
+    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
diff --git a/python/m5/objects/PhysicalMemory.mpy b/python/m5/objects/PhysicalMemory.mpy
deleted file mode 100644 (file)
index e6df2a1..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-from FunctionalMemory import FunctionalMemory
-
-simobj PhysicalMemory(FunctionalMemory):
-    type = 'PhysicalMemory'
-    range = Param.AddrRange("Device Address")
-    file = Param.String('', "memory mapped file")
-    mmu = Param.MemoryController(parent.any, "Memory Controller")
diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py
new file mode 100644 (file)
index 0000000..f50937e
--- /dev/null
@@ -0,0 +1,8 @@
+from m5 import *
+from FunctionalMemory import FunctionalMemory
+
+class PhysicalMemory(FunctionalMemory):
+    type = 'PhysicalMemory'
+    range = Param.AddrRange("Device Address")
+    file = Param.String('', "memory mapped file")
+    mmu = Param.MemoryController(Parent.any, "Memory Controller")
diff --git a/python/m5/objects/Platform.mpy b/python/m5/objects/Platform.mpy
deleted file mode 100644 (file)
index 166f3f4..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-simobj Platform(SimObject):
-    type = 'Platform'
-    abstract = True
-    intrctrl = Param.IntrControl(parent.any, "interrupt controller")
diff --git a/python/m5/objects/Platform.py b/python/m5/objects/Platform.py
new file mode 100644 (file)
index 0000000..4da0ffa
--- /dev/null
@@ -0,0 +1,5 @@
+from m5 import *
+class Platform(SimObject):
+    type = 'Platform'
+    abstract = True
+    intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
diff --git a/python/m5/objects/Process.mpy b/python/m5/objects/Process.mpy
deleted file mode 100644 (file)
index 6a91c09..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-simobj Process(SimObject):
-    type = 'Process'
-    abstract = True
-    output = Param.String('cout', 'filename for stdout/stderr')
-
-simobj LiveProcess(Process):
-    type = 'LiveProcess'
-    cmd = VectorParam.String("command line (executable plus arguments)")
-    env = VectorParam.String('', "environment settings")
-    input = Param.String('cin', "filename for stdin")
-
-simobj EioProcess(Process):
-    type = 'EioProcess'
-    chkpt = Param.String('', "EIO checkpoint file name (optional)")
-    file = Param.String("EIO trace file name")
diff --git a/python/m5/objects/Process.py b/python/m5/objects/Process.py
new file mode 100644 (file)
index 0000000..17a66c6
--- /dev/null
@@ -0,0 +1,16 @@
+from m5 import *
+class Process(SimObject):
+    type = 'Process'
+    abstract = True
+    output = Param.String('cout', 'filename for stdout/stderr')
+
+class LiveProcess(Process):
+    type = 'LiveProcess'
+    cmd = VectorParam.String("command line (executable plus arguments)")
+    env = VectorParam.String('', "environment settings")
+    input = Param.String('cin', "filename for stdin")
+
+class EioProcess(Process):
+    type = 'EioProcess'
+    chkpt = Param.String('', "EIO checkpoint file name (optional)")
+    file = Param.String("EIO trace file name")
diff --git a/python/m5/objects/Repl.mpy b/python/m5/objects/Repl.mpy
deleted file mode 100644 (file)
index fff5a2a..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-simobj Repl(SimObject):
-    type = 'Repl'
-    abstract = True
-
-simobj GenRepl(Repl):
-    type = 'GenRepl'
-    fresh_res = Param.Int("associativity")
-    num_pools = Param.Int("capacity in bytes")
-    pool_res = Param.Int("block size in bytes")
diff --git a/python/m5/objects/Repl.py b/python/m5/objects/Repl.py
new file mode 100644 (file)
index 0000000..afd2560
--- /dev/null
@@ -0,0 +1,10 @@
+from m5 import *
+class Repl(SimObject):
+    type = 'Repl'
+    abstract = True
+
+class GenRepl(Repl):
+    type = 'GenRepl'
+    fresh_res = Param.Int("associativity")
+    num_pools = Param.Int("capacity in bytes")
+    pool_res = Param.Int("block size in bytes")
diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy
deleted file mode 100644 (file)
index 2493dc4..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-from HierParams import HierParams
-from Serialize import Serialize
-from Statistics import Statistics
-from Trace import Trace
-
-simobj Root(SimObject):
-    type = 'Root'
-    frequency = Param.RootFrequency('200MHz', "tick frequency")
-    output_file = Param.String('cout', "file to dump simulator output to")
-    hier = HierParams(do_data = False, do_events = True)
-    checkpoint = Param.String('', "Checkpoint file")
-    stats = Statistics()
-    trace = Trace()
-    serialize = Serialize()
diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py
new file mode 100644 (file)
index 0000000..78d5388
--- /dev/null
@@ -0,0 +1,20 @@
+from m5 import *
+from HierParams import HierParams
+from Serialize import Serialize
+from Statistics import Statistics
+from Trace import Trace
+
+class Root(SimObject):
+    type = 'Root'
+    frequency = Param.RootFrequency('200MHz', "tick frequency")
+    output_file = Param.String('cout', "file to dump simulator output to")
+    checkpoint = Param.String('', "checkpoint file to load")
+#    hier = Param.HierParams(HierParams(do_data = False, do_events = True),
+#                            "shared memory hierarchy parameters")
+#    stats = Param.Statistics(Statistics(), "statistics object")
+#    trace = Param.Trace(Trace(), "trace object")
+#    serialize = Param.Serialize(Serialize(), "checkpoint generation options")
+    hier = HierParams(do_data = False, do_events = True)
+    stats = Statistics()
+    trace = Trace()
+    serialize = Serialize()
diff --git a/python/m5/objects/SimConsole.mpy b/python/m5/objects/SimConsole.mpy
deleted file mode 100644 (file)
index 53ddaa2..0000000
+++ /dev/null
@@ -1,11 +0,0 @@
-simobj ConsoleListener(SimObject):
-    type = 'ConsoleListener'
-    port = Param.TcpPort(3456, "listen port")
-
-simobj SimConsole(SimObject):
-    type = 'SimConsole'
-    append_name = Param.Bool(True, "append name() to filename")
-    intr_control = Param.IntrControl(parent.any, "interrupt controller")
-    listener = Param.ConsoleListener("console listener")
-    number = Param.Int(0, "console number")
-    output = Param.String('console', "file to dump output to")
diff --git a/python/m5/objects/SimConsole.py b/python/m5/objects/SimConsole.py
new file mode 100644 (file)
index 0000000..df30619
--- /dev/null
@@ -0,0 +1,12 @@
+from m5 import *
+class ConsoleListener(SimObject):
+    type = 'ConsoleListener'
+    port = Param.TcpPort(3456, "listen port")
+
+class SimConsole(SimObject):
+    type = 'SimConsole'
+    append_name = Param.Bool(True, "append name() to filename")
+    intr_control = Param.IntrControl(Parent.any, "interrupt controller")
+    listener = Param.ConsoleListener("console listener")
+    number = Param.Int(0, "console number")
+    output = Param.String('console', "file to dump output to")
diff --git a/python/m5/objects/SimpleDisk.mpy b/python/m5/objects/SimpleDisk.mpy
deleted file mode 100644 (file)
index b616fb3..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-simobj SimpleDisk(SimObject):
-    type = 'SimpleDisk'
-    disk = Param.DiskImage("Disk Image")
-    physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
diff --git a/python/m5/objects/SimpleDisk.py b/python/m5/objects/SimpleDisk.py
new file mode 100644 (file)
index 0000000..48448e6
--- /dev/null
@@ -0,0 +1,5 @@
+from m5 import *
+class SimpleDisk(SimObject):
+    type = 'SimpleDisk'
+    disk = Param.DiskImage("Disk Image")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
diff --git a/python/m5/objects/Tsunami.mpy b/python/m5/objects/Tsunami.mpy
deleted file mode 100644 (file)
index c17eae1..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-from Device import FooPioDevice
-from Platform import Platform
-
-simobj Tsunami(Platform):
-    type = 'Tsunami'
-    pciconfig = Param.PciConfigAll("PCI configuration")
-    system = Param.BaseSystem(parent.any, "system")
-
-simobj TsunamiCChip(FooPioDevice):
-    type = 'TsunamiCChip'
-    tsunami = Param.Tsunami(parent.any, "Tsunami")
-
-simobj TsunamiFake(FooPioDevice):
-    type = 'TsunamiFake'
-
-simobj TsunamiIO(FooPioDevice):
-    type = 'TsunamiIO'
-    time = Param.UInt64(1136073600,
-        "System time to use (0 for actual time, default is 1/1/06)")
-    tsunami = Param.Tsunami(parent.any, "Tsunami")
-    frequency = Param.Frequency('1024Hz', "frequency of interrupts")
-
-simobj TsunamiPChip(FooPioDevice):
-    type = 'TsunamiPChip'
-    tsunami = Param.Tsunami(parent.any, "Tsunami")
diff --git a/python/m5/objects/Tsunami.py b/python/m5/objects/Tsunami.py
new file mode 100644 (file)
index 0000000..fa3c181
--- /dev/null
@@ -0,0 +1,26 @@
+from m5 import *
+from Device import FooPioDevice
+from Platform import Platform
+
+class Tsunami(Platform):
+    type = 'Tsunami'
+    pciconfig = Param.PciConfigAll("PCI configuration")
+    system = Param.BaseSystem(Parent.any, "system")
+
+class TsunamiCChip(FooPioDevice):
+    type = 'TsunamiCChip'
+    tsunami = Param.Tsunami(Parent.any, "Tsunami")
+
+class TsunamiFake(FooPioDevice):
+    type = 'TsunamiFake'
+
+class TsunamiIO(FooPioDevice):
+    type = 'TsunamiIO'
+    time = Param.UInt64(1136073600,
+        "System time to use (0 for actual time, default is 1/1/06)")
+    tsunami = Param.Tsunami(Parent.any, "Tsunami")
+    frequency = Param.Frequency('1024Hz', "frequency of interrupts")
+
+class TsunamiPChip(FooPioDevice):
+    type = 'TsunamiPChip'
+    tsunami = Param.Tsunami(Parent.any, "Tsunami")
diff --git a/python/m5/objects/Uart.mpy b/python/m5/objects/Uart.mpy
deleted file mode 100644 (file)
index 5a6c25f..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-from Device import PioDevice
-
-simobj Uart(PioDevice):
-    type = 'Uart'
-    console = Param.SimConsole(parent.any, "The console")
-    size = Param.Addr(0x8, "Device size")
diff --git a/python/m5/objects/Uart.py b/python/m5/objects/Uart.py
new file mode 100644 (file)
index 0000000..cfb09ac
--- /dev/null
@@ -0,0 +1,7 @@
+from m5 import *
+from Device import PioDevice
+
+class Uart(PioDevice):
+    type = 'Uart'
+    console = Param.SimConsole(Parent.any, "The console")
+    size = Param.Addr(0x8, "Device size")
index d04f049eaf7df7679fe3e95698f9ccac254afadb..ac789e5d6c4dc7923314af389fc4a4206c40b118 100755 (executable)
@@ -55,14 +55,19 @@ try:
 except getopt.GetoptError:
     sys.exit('Improper Usage')
 
+import __main__
+__main__.m5_build_env = m5_build_env
+
 from m5 import *
 
 for path in pathlist:
     AddToPath(path)
 
 for arg in args:
-    LoadMpyFile(arg)
+    AddToPath(os.path.dirname(arg))
+    execfile(arg)
 
-if globals().has_key('root') and isinstance(root, type) \
-       and issubclass(root, Root):
+if globals().has_key('root') and isinstance(root, Root):
     instantiate(root)
+else:
+    print "Instantiation skipped: no root object found."