i965/gen6+: Add support for storing immediate data into a buffer

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index efe7730965d432a2e731d5f8724ef537fa386014..e628564f14a345e96296801c762ea556f8b91946 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1452,6 +1452,10 @@ void brw_store_register_mem32(struct brw_context *brw,
                               drm_intel_bo *bo, uint32_t reg, uint32_t offset);
 void brw_store_register_mem64(struct brw_context *brw,
                               drm_intel_bo *bo, uint32_t reg, uint32_t offset);
+void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
+                          uint32_t offset, uint32_t imm);
+void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
+                          uint32_t offset, uint64_t imm);
 
 /*======================================================================
  * brw_state_dump.c

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 03a31b69184b9294bc7d26e768f4ee3eecc7c05e..334be0c427d6a4b3b921a5a2bddac9c15491616c 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -600,3 +600,48 @@ brw_store_register_mem64(struct brw_context *brw,
       ADVANCE_BATCH();
    }
 }
+
+/*
+ * Write 32-bits of immediate data to a GPU memory buffer.
+ */
+void
+brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
+                     uint32_t offset, uint32_t imm)
+{
+   const int len = brw->gen >= 8 ? 4 : 3;
+   assert(brw->gen >= 6);
+
+   BEGIN_BATCH(len);
+   OUT_BATCH(MI_STORE_DATA_IMM | (len - 2));
+   if (len > 3)
+      OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                  offset);
+   else
+      OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                offset);
+   OUT_BATCH(imm);
+   ADVANCE_BATCH();
+}
+
+/*
+ * Write 64-bits of immediate data to a GPU memory buffer.
+ */
+void
+brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
+                     uint32_t offset, uint64_t imm)
+{
+   const int len = brw->gen >= 8 ? 5 : 4;
+   assert(brw->gen >= 6);
+
+   BEGIN_BATCH(len);
+   OUT_BATCH(MI_STORE_DATA_IMM | (len - 2));
+   if (len > 4)
+      OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                  offset);
+   else
+      OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                offset);
+   OUT_BATCH(imm & 0xffffffffu);
+   OUT_BATCH(imm >> 32);
+   ADVANCE_BATCH();
+}

diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
index 01b435864e33e54c0b6d6a9e5d6831b3c932d60e..c0d28746875e7833f4bdde430d73f8d6097581de 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ b/src/mesa/drivers/dri/i965/intel_reg.h
@@ -35,6 +35,7 @@
 #define FLUSH_MAP_CACHE                                (1 << 0)
 #define INHIBIT_FLUSH_RENDER_CACHE             (1 << 2)
 
+#define MI_STORE_DATA_IMM              (CMD_MI | (0x20 << 23))
 #define MI_LOAD_REGISTER_IMM           (CMD_MI | (0x22 << 23))
 
 #define MI_FLUSH_DW                    (CMD_MI | (0x26 << 23) | 2)