+2018-01-26 Julia Koval <julia.koval@intel.com>
+
+ * config/i386/avx512bitalgintrin.h (_mm512_bitshuffle_epi64_mask,
+ _mm512_mask_bitshuffle_epi64_mask, _mm256_bitshuffle_epi64_mask,
+ _mm256_mask_bitshuffle_epi64_mask, _mm_bitshuffle_epi64_mask,
+ _mm_mask_bitshuffle_epi64_mask): Fix type.
+ * config/i386/i386-builtin-types.def (UHI_FTYPE_V2DI_V2DI_UHI,
+ USI_FTYPE_V4DI_V4DI_USI): Remove.
+ * config/i386/i386-builtin.def (__builtin_ia32_vpshufbitqmb512_mask,
+ __builtin_ia32_vpshufbitqmb256_mask,
+ __builtin_ia32_vpshufbitqmb128_mask): Fix types.
+ * config/i386/i386.c (ix86_expand_args_builtin): Remove old types.
+ * config/i386/sse.md (VI1_AVX512VLBW): Change types.
+
2018-01-26 Alan Modra <amodra@gmail.com>
PR target/84033
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_bitshuffle_epi64_mask (__m512i __A, __m512i __B)
{
- return (__mmask64) __builtin_ia32_vpshufbitqmb512_mask ((__v8di) __A,
- (__v8di) __B,
+ return (__mmask64) __builtin_ia32_vpshufbitqmb512_mask ((__v64qi) __A,
+ (__v64qi) __B,
(__mmask64) -1);
}
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_mask_bitshuffle_epi64_mask (__mmask8 __M, __m512i __A, __m512i __B)
{
- return (__mmask64) __builtin_ia32_vpshufbitqmb512_mask ((__v8di) __A,
- (__v8di) __B,
+ return (__mmask64) __builtin_ia32_vpshufbitqmb512_mask ((__v64qi) __A,
+ (__v64qi) __B,
(__mmask64) __M);
}
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_bitshuffle_epi64_mask (__m256i __A, __m256i __B)
{
- return (__mmask32) __builtin_ia32_vpshufbitqmb256_mask ((__v4di) __A,
- (__v4di) __B,
+ return (__mmask32) __builtin_ia32_vpshufbitqmb256_mask ((__v32qi) __A,
+ (__v32qi) __B,
(__mmask32) -1);
}
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_mask_bitshuffle_epi64_mask (__mmask32 __M, __m256i __A, __m256i __B)
{
- return (__mmask32) __builtin_ia32_vpshufbitqmb256_mask ((__v4di) __A,
- (__v4di) __B,
+ return (__mmask32) __builtin_ia32_vpshufbitqmb256_mask ((__v32qi) __A,
+ (__v32qi) __B,
(__mmask32) __M);
}
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_bitshuffle_epi64_mask (__m128i __A, __m128i __B)
{
- return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v2di) __A,
- (__v2di) __B,
+ return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v16qi) __A,
+ (__v16qi) __B,
(__mmask16) -1);
}
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_mask_bitshuffle_epi64_mask (__mmask16 __M, __m128i __A, __m128i __B)
{
- return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v2di) __A,
- (__v2di) __B,
+ return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v16qi) __A,
+ (__v16qi) __B,
(__mmask16) __M);
}
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, INT)
# BITALG builtins
-DEF_FUNCTION_TYPE (UHI, V2DI, V2DI, UHI)
-DEF_FUNCTION_TYPE (USI, V4DI, V4DI, USI)
DEF_FUNCTION_TYPE (V4DI, V4DI)
DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, UHI)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, UHI)
BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv8hi, "__builtin_ia32_vpopcountw_v8hi", IX86_BUILTIN_VPOPCOUNTWV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI)
BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpopcountv8hi_mask, "__builtin_ia32_vpopcountw_v8hi_mask", IX86_BUILTIN_VPOPCOUNTQV8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI)
-BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512vl_vpshufbitqmbv8di_mask, "__builtin_ia32_vpshufbitqmb512_mask", IX86_BUILTIN_VPSHUFBITQMB512_MASK, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_UQI)
-BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512vl_vpshufbitqmbv4di_mask, "__builtin_ia32_vpshufbitqmb256_mask", IX86_BUILTIN_VPSHUFBITQMB256_MASK, UNKNOWN, (int) USI_FTYPE_V4DI_V4DI_USI)
-BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpshufbitqmbv2di_mask, "__builtin_ia32_vpshufbitqmb128_mask", IX86_BUILTIN_VPSHUFBITQMB128_MASK, UNKNOWN, (int) UHI_FTYPE_V2DI_V2DI_UHI)
+BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512vl_vpshufbitqmbv64qi_mask, "__builtin_ia32_vpshufbitqmb512_mask", IX86_BUILTIN_VPSHUFBITQMB512_MASK, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI)
+BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512vl_vpshufbitqmbv32qi_mask, "__builtin_ia32_vpshufbitqmb256_mask", IX86_BUILTIN_VPSHUFBITQMB256_MASK, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI)
+BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpshufbitqmbv16qi_mask, "__builtin_ia32_vpshufbitqmb128_mask", IX86_BUILTIN_VPSHUFBITQMB128_MASK, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
case HI_FTYPE_V16SF_INT_UHI:
case QI_FTYPE_V8SF_INT_UQI:
case QI_FTYPE_V4SF_INT_UQI:
- case UHI_FTYPE_V2DI_V2DI_UHI:
- case USI_FTYPE_V4DI_V4DI_USI:
case V4SI_FTYPE_V4SI_V4SI_UHI:
case V8SI_FTYPE_V8SI_V8SI_UHI:
nargs = 3;
(V4SI "TARGET_AVX2") (V2DI "TARGET_AVX2")
(V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2")])
-(define_mode_iterator VI48_AVX512VLBW
- [(V8DI "TARGET_AVX512BW") (V4DI "TARGET_AVX512VL")
- (V2DI "TARGET_AVX512VL")])
+(define_mode_iterator VI1_AVX512VLBW
+ [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL")
+ (V16QI "TARGET_AVX512VL")])
(define_mode_attr avx512
[(V16QI "avx512vl") (V32QI "avx512vl") (V64QI "avx512bw")
(define_insn "avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
(unspec:<avx512fmaskmode>
- [(match_operand:VI48_AVX512VLBW 1 "register_operand" "v")
- (match_operand:VI48_AVX512VLBW 2 "nonimmediate_operand" "vm")]
+ [(match_operand:VI1_AVX512VLBW 1 "register_operand" "v")
+ (match_operand:VI1_AVX512VLBW 2 "nonimmediate_operand" "vm")]
UNSPEC_VPSHUFBIT))]
"TARGET_AVX512BITALG"
"vpshufbitqmb\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
+2018-01-26 Julia Koval <julia.koval@intel.com>
+
+ * gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Add -mavx512f -mavx512bw.
+ * gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Add -mavx512bw.
+ * gcc.target/i386/i386.exp: Fix types.
+
2018-01-26 Alan Modra <amodra@gmail.com>
PR target/84033
/* { dg-do run } */
-/* { dg-options "-O2 -mavx512bitalg" } */
+/* { dg-options "-O2 -mavx512bitalg -mavx512f -mavx512bw" } */
/* { dg-require-effective-target avx512bitalg } */
#include "avx512f-helper.h"
/* { dg-do run } */
-/* { dg-options "-O2 -mavx512vl -mavx512bitalg" } */
+/* { dg-options "-O2 -mavx512vl -mavx512bitalg -mavx512bw" } */
/* { dg-require-effective-target avx512vl } */
/* { dg-require-effective-target avx512bitalg } */
# Return 1 if avx512_bitalg instructions can be compiled.
proc check_effective_target_avx512bitalg { } {
return [check_no_compiler_messages avx512bitalg object {
- typedef int __v32hi __attribute__ ((__vector_size__ (64)));
+ typedef short int __v32hi __attribute__ ((__vector_size__ (64)));
__v32hi
_mm512_popcnt_epi16 (__v32hi __A)
{
- return (__v32hi) __builtin_ia32_vpopcountd_v32hi ((__v32hi) __A);
+ return (__v32hi) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A);
}
} "-mavx512bitalg" ]
}