// If we have a signed multiply-add, then perform sign extension
// TODO: Need to check CD[31:16] is sign extension of CD[15:0]?
if (st.addAB->getParam("\\A_SIGNED").as_bool() && st.addAB->getParam("\\B_SIGNED").as_bool())
- pm.module->connect(O[-1], O[-2]);
+ pm.module->connect(O[32], O[31]);
else
- cell->setPort("\\CO", O[-1]);
+ cell->setPort("\\CO", O[32]);
O.remove(O_width-1);
}
else
endmatch
code
- SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
- O.remove_const();
- if (!includes(port(ffO_lo, \D).to_sigbit_set(), O.to_sigbit_set()))
- reject;
+ if (ffO_lo) {
+ SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
+ O.remove_const();
+ if (!includes(port(ffO_lo, \D).to_sigbit_set(), O.to_sigbit_set()))
+ reject;
+ }
endcode
match ffO_hi
endmatch
code
- SigSpec O = sigOused.extract_end(16);
- O.remove_const();
- if (!includes(port(ffO_hi, \D).to_sigbit_set(), O.to_sigbit_set()))
- reject;
+ if (ffO_hi) {
+ SigSpec O = sigOused.extract_end(16);
+ O.remove_const();
+ if (!includes(port(ffO_hi, \D).to_sigbit_set(), O.to_sigbit_set()))
+ reject;
+ }
endcode
code clock clock_pol sigO sigCD