[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Fri, 27 Mar 2020 10:44:30 +0000 (10:44 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 27 Mar 2020 10:44:31 +0000 (10:44 +0000)
5e/97f21cc8b3d1c36a25307beeb1798e34ca825d [new file with mode: 0644]

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+Date: Fri, 27 Mar 2020 10:44:30 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: staf@fibraservi.eu
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+Message-ID: <bug-268-13-RhBrMKruuY@http.bugs.libre-riscv.org/>
+In-Reply-To: <bug-268-13@http.bugs.libre-riscv.org/>
+References: <bug-268-13@http.bugs.libre-riscv.org/>
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+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 268] nmigen does not seem to support
+ write-through SRAM
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