It can't parse "llu".
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
#define __DRI2_FENCE "DRI2_Fence"
#define __DRI2_FENCE_VERSION 2
-#define __DRI2_FENCE_TIMEOUT_INFINITE 0xffffffffffffffffllu
+#define __DRI2_FENCE_TIMEOUT_INFINITE 0xffffffffffffffffull
#define __DRI2_FENCE_FLAG_FLUSH_COMMANDS (1 << 0)
case TGSI_SEMANTIC_TESSOUTER:
case TGSI_SEMANTIC_PATCH:
sel->lds_patch_outputs_written_mask |=
- 1llu << r600_get_lds_unique_index(name, index);
+ 1ull << r600_get_lds_unique_index(name, index);
break;
default:
sel->lds_outputs_written_mask |=
- 1llu << r600_get_lds_unique_index(name, index);
+ 1ull << r600_get_lds_unique_index(name, index);
}
}
break;
#define DBG_TEST_DMA (1 << 20)
/* Bits 21-31 are reserved for the r600g driver. */
/* features */
-#define DBG_NO_ASYNC_DMA (1llu << 32)
-#define DBG_NO_HYPERZ (1llu << 33)
-#define DBG_NO_DISCARD_RANGE (1llu << 34)
-#define DBG_NO_2D_TILING (1llu << 35)
-#define DBG_NO_TILING (1llu << 36)
-#define DBG_SWITCH_ON_EOP (1llu << 37)
-#define DBG_FORCE_DMA (1llu << 38)
-#define DBG_PRECOMPILE (1llu << 39)
-#define DBG_INFO (1llu << 40)
-#define DBG_NO_WC (1llu << 41)
-#define DBG_CHECK_VM (1llu << 42)
-#define DBG_NO_DCC (1llu << 43)
-#define DBG_NO_DCC_CLEAR (1llu << 44)
-#define DBG_NO_RB_PLUS (1llu << 45)
-#define DBG_SI_SCHED (1llu << 46)
-#define DBG_MONOLITHIC_SHADERS (1llu << 47)
-#define DBG_NO_CE (1llu << 48)
-#define DBG_UNSAFE_MATH (1llu << 49)
-#define DBG_NO_DCC_FB (1llu << 50)
-#define DBG_TEST_VMFAULT_CP (1llu << 51)
-#define DBG_TEST_VMFAULT_SDMA (1llu << 52)
-#define DBG_TEST_VMFAULT_SHADER (1llu << 53)
+#define DBG_NO_ASYNC_DMA (1ull << 32)
+#define DBG_NO_HYPERZ (1ull << 33)
+#define DBG_NO_DISCARD_RANGE (1ull << 34)
+#define DBG_NO_2D_TILING (1ull << 35)
+#define DBG_NO_TILING (1ull << 36)
+#define DBG_SWITCH_ON_EOP (1ull << 37)
+#define DBG_FORCE_DMA (1ull << 38)
+#define DBG_PRECOMPILE (1ull << 39)
+#define DBG_INFO (1ull << 40)
+#define DBG_NO_WC (1ull << 41)
+#define DBG_CHECK_VM (1ull << 42)
+#define DBG_NO_DCC (1ull << 43)
+#define DBG_NO_DCC_CLEAR (1ull << 44)
+#define DBG_NO_RB_PLUS (1ull << 45)
+#define DBG_SI_SCHED (1ull << 46)
+#define DBG_MONOLITHIC_SHADERS (1ull << 47)
+#define DBG_NO_CE (1ull << 48)
+#define DBG_UNSAFE_MATH (1ull << 49)
+#define DBG_NO_DCC_FB (1ull << 50)
+#define DBG_TEST_VMFAULT_CP (1ull << 51)
+#define DBG_TEST_VMFAULT_SDMA (1ull << 52)
+#define DBG_TEST_VMFAULT_SHADER (1ull << 53)
#define R600_MAP_BUFFER_ALIGNMENT 64
#define R600_MAX_VIEWPORTS 16
if (!size)
return;
- dma_clear_size = size & ~3llu;
+ dma_clear_size = size & ~3ull;
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
/* Print the usage. */
for (j = 0; j < 64; j++) {
- if (!(saved->bo_list[i].priority_usage & (1llu << j)))
+ if (!(saved->bo_list[i].priority_usage & (1ull << j)))
continue;
fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j));
}
continue;
}
- timestamp = sec * 1000000llu + usec;
+ timestamp = sec * 1000000ull + usec;
/* If just updating the timestamp. */
if (!out_addr)
if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
/* Just set this if any of the colorbuffers are enabled. */
if (spi_format &
- ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
+ ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
last_color_export = 0;
} else {
for (i = 0; i < 8; i++)
case PIPE_SHADER_TESS_CTRL:
/* Always reserve space for these. */
sel->patch_outputs_written |=
- (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
- (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
+ (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
+ (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
/* fall through */
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_TESS_EVAL:
case TGSI_SEMANTIC_TESSOUTER:
case TGSI_SEMANTIC_PATCH:
sel->patch_outputs_written |=
- 1llu << si_shader_io_get_unique_index_patch(name, index);
+ 1ull << si_shader_io_get_unique_index_patch(name, index);
break;
case TGSI_SEMANTIC_GENERIC:
/* fall through */
default:
sel->outputs_written |=
- 1llu << si_shader_io_get_unique_index(name, index);
+ 1ull << si_shader_io_get_unique_index(name, index);
break;
case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
case TGSI_SEMANTIC_EDGEFLAG:
/* fall through */
default:
sel->inputs_read |=
- 1llu << si_shader_io_get_unique_index(name, index);
+ 1ull << si_shader_io_get_unique_index(name, index);
break;
case TGSI_SEMANTIC_PCOORD: /* ignore this */
break;
buffer = &cs->sparse_buffers[index];
}
- buffer->u.real.priority_usage |= 1llu << priority;
+ buffer->u.real.priority_usage |= 1ull << priority;
buffer->usage |= usage;
cs->last_added_bo = bo;
reloc->read_domains |= rd;
reloc->write_domain |= wd;
reloc->flags = MAX2(reloc->flags, priority);
- cs->csc->relocs_bo[index].u.real.priority_usage |= 1llu << priority;
+ cs->csc->relocs_bo[index].u.real.priority_usage |= 1ull << priority;
if (added_domains & RADEON_DOMAIN_VRAM)
cs->base.used_vram += bo->base.size;
/* Define ST_NEW_xxx values as static const uint64_t values.
* We can't use an enum type because MSVC doesn't allow 64-bit enum values.
*/
-#define ST_STATE(FLAG, st_update) static const uint64_t FLAG = 1llu << FLAG##_INDEX;
+#define ST_STATE(FLAG, st_update) static const uint64_t FLAG = 1ull << FLAG##_INDEX;
#include "st_atom_list.h"
#undef ST_STATE
/* All state flags within each group: */
#define ST_PIPELINE_RENDER_STATE_MASK (ST_NEW_CS_STATE - 1)
-#define ST_PIPELINE_COMPUTE_STATE_MASK (0xffllu << ST_NEW_CS_STATE_INDEX)
+#define ST_PIPELINE_COMPUTE_STATE_MASK (0xffull << ST_NEW_CS_STATE_INDEX)
#define ST_PIPELINE_CLEAR_STATE_MASK (ST_NEW_FB_STATE | \
ST_NEW_SCISSOR | \
ST_NEW_WINDOW_RECTANGLES)
static inline void
u_bit_scan_consecutive_range64(uint64_t *mask, int *start, int *count)
{
- if (*mask == ~0llu) {
+ if (*mask == ~0ull) {
*start = 0;
*count = 64;
*mask = 0;