arch-riscv: ignore writes to SXL/UXL fields in status register.

We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.

Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25651
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 754ff85b758a41d4ea2c0fb70aac23cc324d6ff0..a2fbd804373151d2db16d1847baa4967d7c5b3a6 100644 (file)
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -347,6 +347,15 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
                 setMiscRegNoEffect(misc_reg, new_val);
             }
             break;
+          case MISCREG_STATUS:
+            {
+                // SXL and UXL are hard-wired to 64 bit
+                auto cur = readMiscRegNoEffect(misc_reg);
+                val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
+                val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
+                setMiscRegNoEffect(misc_reg, val);
+            }
+            break;
           default:
             setMiscRegNoEffect(misc_reg, val);
         }