aarch64.c (aarch64_simd_gen_const_vector_dup): Change int to HOST_WIDE_INT.

gcc/
2017-01-19  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64.c (aarch64_simd_gen_const_vector_dup):
	Change int to HOST_WIDE_INT.
	* config/aarch64/aarch64-protos.h
	(aarch64_simd_gen_const_vector_dup): Likewise.
	* config/aarch64/aarch64-simd.md: Add copysign<mode>3.

gcc/testsuite/
2017-01-19  Tamar Christina  <tamar.christina@arm.com>

	* gcc/testsuite/lib/target-supports.exp
	(check_effective_target_vect_call_copysignf): Enable for AArch64.

From-SVN: r244649

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a51167089e627825866d9ced5a8237fc01bcffbc..6bfb0c65b6ff5083d09e7eae91b07c7763cc5425 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2017-01-19  Tamar Christina  <tamar.christina@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_simd_gen_const_vector_dup):
+       Change int to HOST_WIDE_INT.
+       * config/aarch64/aarch64-protos.h
+       (aarch64_simd_gen_const_vector_dup): Likewise.
+       * config/aarch64/aarch64-simd.md: Add copysign<mode>3.
+
 2017-01-19  David Malcolm  <dmalcolm@redhat.com>
 
        * langhooks-def.h (lhd_type_for_size): New decl.

diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 8c4380b5953f3ec10b0fdbe654cbb69ecb044679..7a9a21ea51c77ad18b92d31924c420622fed3d60 100644 (file)
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -362,7 +362,7 @@ rtx aarch64_eh_return_handler_rtx (void);
 rtx aarch64_mask_from_zextract_ops (rtx, rtx);
 const char *aarch64_output_move_struct (rtx *operands);
 rtx aarch64_return_addr (int, rtx);
-rtx aarch64_simd_gen_const_vector_dup (machine_mode, int);
+rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT);
 bool aarch64_simd_mem_operand_p (rtx);
 rtx aarch64_simd_vect_par_cnst_half (machine_mode, bool);
 rtx aarch64_tls_get_addr (void);

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index a12e2268ef9b023112f8d05db0a86957fee83273..b61f79a09462b8cecca7dd2cc4ac0eb4be2dbc79 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -338,6 +338,24 @@
   }
 )
 
+(define_expand "copysign<mode>3"
+  [(match_operand:VHSDF 0 "register_operand")
+   (match_operand:VHSDF 1 "register_operand")
+   (match_operand:VHSDF 2 "register_operand")]
+  "TARGET_FLOAT && TARGET_SIMD"
+{
+  rtx v_bitmask = gen_reg_rtx (<V_cmp_result>mode);
+  int bits = GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1;
+
+  emit_move_insn (v_bitmask,
+                 aarch64_simd_gen_const_vector_dup (<V_cmp_result>mode,
+                                                    HOST_WIDE_INT_M1U << bits));
+  emit_insn (gen_aarch64_simd_bsl<mode> (operands[0], v_bitmask,
+                                        operands[2], operands[1]));
+  DONE;
+}
+)
+
 (define_insn "*aarch64_mul3_elt<mode>"
  [(set (match_operand:VMUL 0 "register_operand" "=w")
     (mult:VMUL

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 39a58804ab691f63c9fa7a92aac24c2a25a4b84b..4432cae6b8ddc84b00219eae884720af69dc376f 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -11237,14 +11237,16 @@ aarch64_mov_operand_p (rtx x, machine_mode mode)
 
 /* Return a const_int vector of VAL.  */
 rtx
-aarch64_simd_gen_const_vector_dup (machine_mode mode, int val)
+aarch64_simd_gen_const_vector_dup (machine_mode mode, HOST_WIDE_INT val)
 {
   int nunits = GET_MODE_NUNITS (mode);
   rtvec v = rtvec_alloc (nunits);
   int i;
 
+  rtx cache = GEN_INT (val);
+
   for (i=0; i < nunits; i++)
-    RTVEC_ELT (v, i) = GEN_INT (val);
+    RTVEC_ELT (v, i) = cache;
 
   return gen_rtx_CONST_VECTOR (mode, v);
 }

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 662fbc548dcafe1ef9724e1162e7f2d830e85442..1a3a521187ec48579097db7a1669a767e3e2a410 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-01-19  Tamar Christina  <tamar.christina@arm.com>
+
+       * gcc/testsuite/lib/target-supports.exp
+       (check_effective_target_vect_call_copysignf): Enable for AArch64.
+
 2017-01-19  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
        PR testsuite/79051

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index b88d13c13f277e8cdb88b5dc8545ffa01408a0fa..12dbf475e31933cff781c2f9e9c1cfbe2ce108bb 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6158,7 +6158,8 @@ proc check_effective_target_vect_call_copysignf { } {
     } else {
        set et_vect_call_copysignf_saved($et_index) 0
        if { [istarget i?86-*-*] || [istarget x86_64-*-*]
-            || [istarget powerpc*-*-*] } {
+            || [istarget powerpc*-*-*]
+            || [istarget aarch64*-*-*] } {
           set et_vect_call_copysignf_saved($et_index) 1
        }
     }