add example code

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 0d4f43c3db7b770fdead00997d8d76bebbfb98d2..e3a951273cba93ff6f5eba60dc740af2e706c226 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -667,8 +667,8 @@ loop:
 
  \begin{itemize}
    \item Actually about parallelism, not Vectors (or SIMD) per se
-   \item Only actually needs 3 actual instructions plus CSRs\\
-         (RVV - and "standard" SIMD - require ISA duplication)
+   \item Only needs 3 actual instructions (plus CSRs)\\
+         RVV - and "standard" SIMD - require ISA duplication
    \item Designed for flexibility (graded levels of complexity)
    \item Huge range of implementor freedom
    \item Fits RISC-V ethos: achieve more with less