radv: mask out high VM address bits in registers where needed

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index f0a0b08678173876d227de709ed2f7e4c7381aef..b3d6fc484ef5f201e0423d5178b9edf07dfe0977 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -820,20 +820,20 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
                radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
                radeon_emit(cmd_buffer->cs, cb->cb_color_base);
-               radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
+               radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
                radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
                radeon_emit(cmd_buffer->cs, cb->cb_color_view);
                radeon_emit(cmd_buffer->cs, cb_color_info);
                radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
                radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
                radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
-               radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
+               radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
                radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
-               radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
+               radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
 
                radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
                radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
-               radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
+               radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
                
                radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
                                       S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
@@ -881,20 +881,20 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
                radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
                radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
-               radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
+               radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
                radeon_emit(cmd_buffer->cs, ds->db_depth_size);
 
                radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
                radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
                radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
                radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
-               radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);  /* DB_Z_READ_BASE_HI */
+               radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
                radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
-               radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
+               radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
                radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
-               radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
+               radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
                radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
-               radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
+               radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
 
                radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
                radeon_emit(cmd_buffer->cs, ds->db_z_info2);

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 4acdf3d41630f7a4d049906318200937edf42593..65727571a3ad6961f2e6e3980832e5b526d671c4 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1921,7 +1921,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
                                                       tf_va >> 8);
                                if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
                                        radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
-                                                              tf_va >> 40);
+                                                              S_030944_BASE_HI(tf_va >> 40));
                                }
                                radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
                        } else {

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index af1ea395d361b150da6e1a27c0c45b5cbd98cba8..5a44efb78b3bd261bbfb29a367ed529e346db5ba 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2418,7 +2418,7 @@ radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
 
        radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
        radeon_emit(cs, va >> 8);
-       radeon_emit(cs, va >> 40);
+       radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
        radeon_emit(cs, shader->rsrc1);
        radeon_emit(cs, shader->rsrc2);
 
@@ -2477,7 +2477,7 @@ radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
 
        radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
        radeon_emit(cs, va >> 8);
-       radeon_emit(cs, va >> 40);
+       radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
        radeon_emit(cs, shader->rsrc1);
        radeon_emit(cs, shader->rsrc2);
 }
@@ -2493,7 +2493,7 @@ radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
 
        radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
        radeon_emit(cs, va >> 8);
-       radeon_emit(cs, va >> 40);
+       radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
 
        rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
        if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
@@ -2516,7 +2516,7 @@ radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
        if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
                radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
                radeon_emit(cs, va >> 8);
-               radeon_emit(cs, va >> 40);
+               radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
 
                radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
                radeon_emit(cs, shader->rsrc1);
@@ -2525,7 +2525,7 @@ radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
        } else {
                radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
                radeon_emit(cs, va >> 8);
-               radeon_emit(cs, va >> 40);
+               radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
                radeon_emit(cs, shader->rsrc1);
                radeon_emit(cs, shader->rsrc2);
        }
@@ -2627,7 +2627,7 @@ radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
        if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
                radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
                radeon_emit(cs, va >> 8);
-               radeon_emit(cs, va >> 40);
+               radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
 
                radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
                radeon_emit(cs, gs->rsrc1);
@@ -2638,7 +2638,7 @@ radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
        } else {
                radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
                radeon_emit(cs, va >> 8);
-               radeon_emit(cs, va >> 40);
+               radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
                radeon_emit(cs, gs->rsrc1);
                radeon_emit(cs, gs->rsrc2);
        }
@@ -2761,7 +2761,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
 
        radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
        radeon_emit(cs, va >> 8);
-       radeon_emit(cs, va >> 40);
+       radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
        radeon_emit(cs, ps->rsrc1);
        radeon_emit(cs, ps->rsrc2);
 
@@ -3236,7 +3236,7 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline)
 
        radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
        radeon_emit(&pipeline->cs, va >> 8);
-       radeon_emit(&pipeline->cs, va >> 40);
+       radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
 
        radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
        radeon_emit(&pipeline->cs, compute_shader->rsrc1);