unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
switch (reg) {
case AMDGPU::M0: return 124;
+ case AMDGPU::EXEC: return 126;
+ case AMDGPU::EXEC_LO: return 126;
+ case AMDGPU::EXEC_HI: return 127;
case AMDGPU::SREG_LIT_0: return 128;
case AMDGPU::SI_LITERAL_CONSTANT: return 255;
default: return getHWRegNum(reg);
SI_256 <name, subregs>;
def VCC : SIReg<"VCC">;
-def EXEC : SIReg<"EXEC">;
+def EXEC_LO : SIReg<"EXEC LO">;
+def EXEC_HI : SIReg<"EXEC HI">;
+def EXEC : SI_64<"EXEC", [EXEC_LO,EXEC_HI]>;
def SCC : SIReg<"SCC">;
def SREG_LIT_0 : SIReg <"S LIT 0">;
def SI_LITERAL_CONSTANT : SIReg<"LITERAL CONSTANT">;
print <<STRING;
def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
- (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0)
+ (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0, EXEC_LO, EXEC_HI)
>;
def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,