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diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn
index c04f6f7162c8f1ece9af12d04725f0dceb77c488..0a7a211bd892f550d5137129868caa84e350a6be 100644 (file)
--- a/openpower/sv/propagation.mdwn
+++ b/openpower/sv/propagation.mdwn
@@ -15,6 +15,6 @@ Any time the LSB of any one of the 7 Context SPRs is zero, the 24 bit `RM` Conte
 
 When the 40 bits of any one of the SPRs reaches zero the entire SPR is set to zero, and the entire SPR bank shuffles down so that at no time will there be an DPR containing zeros splitting up the SPRs.  This allows a data-dependent fail-first copy of all SPRs to be used as a single instruction because the last SPR will always be zero.
 
-As these changes occur on a fixed schedule conpilers should not have difficulties statically allocating the Context Propagation, as long as certain conventions are followed, such as avoidance of allowing the context to propagate through branches used by more than one incoming path, and loops.
+As these changes occur on a fixed schedule compilers should not have difficulties statically allocating the Context Propagation, as long as certain conventions are followed, such as avoidance of allowing the context to propagate through branches used by more than one incoming path, and loops.