re PR rtl-optimization/66706 (Redundant bitmask instruction on x >> (n & 32))

	PR rtl-optimization/66706
	* gcc.target/powerpc/shift-int.c: New testcase.

From-SVN: r225382

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 05344971c993d9cf7a7b1188c53dfc303debaf9a..493b730a559b2bd84697dc776cc89f8ee9ad46ae 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-07-03  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       PR rtl-optimization/66706
+       * gcc.target/powerpc/shift-int.c: New testcase.
+
 2015-07-03  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/66746.

diff --git a/gcc/testsuite/gcc.target/powerpc/shift-int.c b/gcc/testsuite/gcc.target/powerpc/shift-int.c
new file mode 100644 (file)
index 0000000..fe696ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/shift-int.c
@@ -0,0 +1,23 @@
+/* Check that shifts do not get unnecessary extends.
+   See PR66706 for a case where this failed.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Each function should compile to exactly two instructions.  */
+/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 16 } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+blr} 8 } } */
+
+
+typedef unsigned u;
+typedef signed s;
+
+u rot(u x, u n) { return (x << n) | (x >> (32 - n)); }
+u shl(u x, u n) { return x << n; }
+u shr(u x, u n) { return x >> n; }
+s asr(s x, u n) { return x >> n; }
+
+u roti(u x) { return (x << 23) | (x >> 9); }
+u shli(u x) { return x << 23; }
+u shri(u x) { return x >> 23; }
+s asri(s x) { return x >> 23; }