radeonsi/gfx10: set more registers and fields

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/registers/gfx10.json b/src/amd/registers/gfx10.json
index 522af60a72a7fadaf251a27fc254e7d6ec7fb052..ea00d0c7fdc06337a12ecf3a8f70b18f7cc41f79 100644 (file)
--- a/src/amd/registers/gfx10.json
+++ b/src/amd/registers/gfx10.json
@@ -10192,6 +10192,12 @@
    "name": "GE_USER_VGPR3",
    "type_ref": "COMPUTE_PGM_LO"
   },
+  {
+   "chips": ["gfx10"],
+   "map": {"at": 199048, "to": "mm"},
+   "name": "GE_USER_VGPR_EN",
+   "type_ref": "GE_USER_VGPR_EN"
+  },
   {
    "chips": ["gfx10"],
    "map": {"at": 165840, "to": "mm"},
@@ -18944,10 +18950,14 @@
     {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
     {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
     {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
-    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"},
-    {"bits": [21, 21], "name": "EN_USER_VGPR1"},
-    {"bits": [22, 22], "name": "EN_USER_VGPR2"},
-    {"bits": [23, 23], "name": "EN_USER_VGPR3"}
+    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
+   ]
+  },
+  "GE_USER_VGPR_EN": {
+   "fields": [
+    {"bits": [0, 0], "name": "EN_USER_VGPR1"},
+    {"bits": [1, 1], "name": "EN_USER_VGPR2"},
+    {"bits": [2, 2], "name": "EN_USER_VGPR3"}
    ]
   },
   "GE_DMA_FIRST_INDEX": {

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 4241d7670dca5b210d71b488dac3e5cb3dbcc716..cc419632d6557256eac3b82b4507a6025d8947d4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1435,6 +1435,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
        if (sctx->num_occlusion_queries > 0 &&
            !sctx->occlusion_queries_disabled) {
                bool perfect = sctx->num_perfect_occlusion_queries > 0;
+               bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
 
                if (sctx->chip_class >= GFX7) {
                        unsigned log_sample_rate = sctx->framebuffer.log_samples;
@@ -1447,6 +1448,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
 
                        db_count_control =
                                S_028004_PERFECT_ZPASS_COUNTS(perfect) |
+                               S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
                                S_028004_SAMPLE_RATE(log_sample_rate) |
                                S_028004_ZPASS_ENABLE(1) |
                                S_028004_SLICE_EVEN_ENABLE(1) |
@@ -5471,9 +5473,12 @@ static void si_init_config(struct si_context *sctx)
        }
 
        if (sctx->chip_class >= GFX10) {
+               si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
                si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
                si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
                si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
+               si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0);
+               si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0);
        } else if (sctx->chip_class == GFX9) {
                si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
                si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
@@ -5608,6 +5613,13 @@ static void si_init_config(struct si_context *sctx)
                               S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
                               S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
                               S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
+               si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
+
+               si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
+                              S_00B0C0_SOFT_GROUPING_EN(1) |
+                              S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
+               si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
+
        }
 
        if (sctx->chip_class >= GFX8) {