log("a series of trivial optimizations and cleanups. This pass executes the other\n");
log("passes in the following order:\n");
log("\n");
- log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-keepdc]\n");
+ log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]\n");
log(" opt_share -nomux\n");
log("\n");
log(" do\n");
log(" opt_muxtree\n");
- log(" opt_reduce [-fine]\n");
+ log(" opt_reduce [-fine] [-full]\n");
log(" opt_share\n");
log(" opt_rmdff\n");
log(" opt_clean [-purge]\n");
- log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-keepdc]\n");
+ log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]\n");
log(" while <changed design>\n");
log("\n");
log("When called with -fast the following script is used instead:\n");
log("\n");
log(" do\n");
- log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-keepdc]\n");
+ log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]\n");
log(" opt_share\n");
log(" opt_rmdff\n");
log(" opt_clean [-purge]\n");
opt_reduce_args += " -fine";
continue;
}
+ if (args[argidx] == "-full") {
+ opt_const_args += " -full";
+ opt_reduce_args += " -full";
+ continue;
+ }
if (args[argidx] == "-keepdc") {
opt_const_args += " -keepdc";
continue;
log(" -undriven\n");
log(" replace undriven nets with undef (x) constants\n");
log("\n");
+ log(" -fine\n");
+ log(" perform fine-grain optimizations\n");
+ log("\n");
+ log(" -full\n");
+ log(" alias for -mux_undef -mux_bool -undriven -fine\n");
+ log("\n");
log(" -keepdc\n");
log(" some optimizations change the behavior of the circuit with respect to\n");
log(" don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause\n");
log(" all result bits to be set to x. this behavior changes when 'a+0' is\n");
log(" replaced by 'a'. the -keepdc option disables all such optimizations.\n");
log("\n");
- log(" -fine\n");
- log(" perform fine-grain optimizations\n");
- log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
do_fine = true;
continue;
}
+ if (args[argidx] == "-full") {
+ mux_undef = true;
+ mux_bool = true;
+ undriven = true;
+ do_fine = true;
+ continue;
+ }
if (args[argidx] == "-keepdc") {
keepdc = true;
continue;
log(" -fine\n");
log(" perform fine-grain optimizations\n");
log("\n");
+ log(" -full\n");
+ log(" alias for -fine\n");
+ log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
do_fine = true;
continue;
}
+ if (args[argidx] == "-full") {
+ do_fine = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
log(" opt_clean\n");
log("\n");
log(" fine:\n");
+ log(" opt -fast -full\n");
log(" memory_map\n");
+ log(" opt -full\n");
log(" techmap\n");
- log(" opt -fast\n");
+ log(" opt -fast -full\n");
#ifdef YOSYS_ENABLE_ABC
log(" abc -fast\n");
log(" opt_clean\n");
if (check_label(active, run_from, run_to, "fine"))
{
+ Pass::call(design, "opt -fast -full");
Pass::call(design, "memory_map");
+ Pass::call(design, "opt -full");
Pass::call(design, "techmap");
- Pass::call(design, "opt -fast");
+ Pass::call(design, "opt -fast -full");
#ifdef YOSYS_ENABLE_ABC
Pass::call(design, "abc -fast");
Pass::call(design, "opt_clean");