i386-opts.h (enum prefer_vector_width): Added new enum for the new option -mprefer...

	* config/i386/i386-opts.h (enum prefer_vector_width): Added new enum
	for the new option -mprefer-vector-width=[none|128|256|512].
	* config/i386/i386.c (ix86_target_string): remove old style options
	-mprefer-avx256 and make -mprefer-avx128 as alias.
	(ix86_option_override_internal):  Apply defaults for the
	-mprefer-vector-width=[128|256] option.
	* config/i386/i386.h (TARGET_PREFER_AVX128, TARGET_PREFER_AVX256):
	Implement macros to work with -mprefer-vector-width=.
	* config/i386/i386.opt: Implemented option
	-mprefer-vector-width=[none|128|256|512].
	* doc/invoke.texi: Documentation for
	-mprefer-vector-width=[none|128|256|512].

gcc/testsuite/

	* g++.dg/ext/pr57362.C (__attribute__): Test
	prefer-vector-width=[128|256] target attribute.
	* gcc.target/i386/avx512f-constant-float-return.c (dg-optioins):
	Use -mprefer-vector-width=256 instead of -mprefer-avx256.
	* gcc.target/i386/avx512f-prefer.c: Ditto.
	* gcc.target/i386/pr82460-2.c: Ditto.

From-SVN: r255030

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a099c79a02c61f2941ab932b28bc93e434ec403d..86b538479ecc82971d1f3e33307b147ceb14a346 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2017-11-21  Sergey Shalnov  <Sergey.Shalnov@intel.com>
+
+       * config/i386/i386-opts.h (enum prefer_vector_width): Added new enum
+       for the new option -mprefer-vector-width=[none|128|256|512].
+       * config/i386/i386.c (ix86_target_string): remove old style options
+       -mprefer-avx256 and make -mprefer-avx128 as alias.
+       (ix86_option_override_internal):  Apply defaults for the
+       -mprefer-vector-width=[128|256] option.
+       * config/i386/i386.h (TARGET_PREFER_AVX128, TARGET_PREFER_AVX256):
+       Implement macros to work with -mprefer-vector-width=.
+       * config/i386/i386.opt: Implemented option
+       -mprefer-vector-width=[none|128|256|512].
+       * doc/invoke.texi: Documentation for
+       -mprefer-vector-width=[none|128|256|512].
+
 2017-11-21  Pat Haugen  <pthaugen@us.ibm.com>
 
        * config/rs6000/ppc-asm.h (f50, vs50): Fix values.

diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h
index 542cd0f3d677f132fed23848a9aa809a909d3959..8c37a7489e00418133175cebf5860d840f4e61a0 100644 (file)
--- a/gcc/config/i386/i386-opts.h
+++ b/gcc/config/i386/i386-opts.h
@@ -99,4 +99,11 @@ enum stack_protector_guard {
   SSP_GLOBAL    /* global canary */
 };
 
+enum prefer_vector_width {
+    PVW_NONE,
+    PVW_AVX128,
+    PVW_AVX256,
+    PVW_AVX512
+};
+
 #endif

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index b32288608d98867a712510d222fa57f278ee7a15..b1ce630753fc08248d5c61ef71bc6db57555dc0d 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2847,15 +2847,13 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
     { "-mstv",                         MASK_STV },
     { "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD },
     { "-mavx256-split-unaligned-store",        MASK_AVX256_SPLIT_UNALIGNED_STORE },
-    { "-mprefer-avx128",               MASK_PREFER_AVX128 },
     { "-mcall-ms2sysv-xlogues",                MASK_CALL_MS2SYSV_XLOGUES }
   };
 
   /* Additional flag options.  */
   static struct ix86_target_opts flag2_opts[] =
   {
-    { "-mgeneral-regs-only",           OPTION_MASK_GENERAL_REGS_ONLY },
-    { "-mprefer-avx256",               OPTION_MASK_PREFER_AVX256 },
+    { "-mgeneral-regs-only",           OPTION_MASK_GENERAL_REGS_ONLY }
   };
 
   const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (isa2_opts)
@@ -4686,16 +4684,18 @@ ix86_option_override_internal (bool main_args_p,
   if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL]
       && !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE))
     opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
+
   /* Enable 128-bit AVX instruction generation
      for the auto-vectorizer.  */
   if (TARGET_AVX128_OPTIMAL
-      && !(opts_set->x_target_flags & MASK_PREFER_AVX128))
-    opts->x_target_flags |= MASK_PREFER_AVX128;
-  /* Use 256-bit AVX instructions instead of 512-bit AVX instructions
+      && (opts_set->x_prefer_vector_width_type == PVW_NONE))
+    opts->x_prefer_vector_width_type = PVW_AVX128;
+
+  /* Use 256-bit AVX instruction generation
      in the auto-vectorizer.  */
   if (ix86_tune_features[X86_TUNE_AVX256_OPTIMAL]
-      && !(opts_set->x_ix86_target_flags & OPTION_MASK_PREFER_AVX256))
-    opts->x_ix86_target_flags |= OPTION_MASK_PREFER_AVX256;
+      && (opts_set->x_prefer_vector_width_type == PVW_NONE))
+    opts->x_prefer_vector_width_type = PVW_AVX256;
 
   if (opts->x_ix86_recip_name)
     {

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index bc601c8e6f8739d026292fee1a16c0718f55d852..6eadc0300001c7bbe4c4cdac96ee432aa6e2f691 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2678,6 +2678,11 @@ extern void debug_dispatch_window (int);
 #define TARGET_RECIP_VEC_DIV   ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
 #define TARGET_RECIP_VEC_SQRT  ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
 
+/* Use 128-bit AVX instructions in the auto-vectorizer.  */
+#define TARGET_PREFER_AVX128   (prefer_vector_width_type == PVW_AVX128)
+/* Use 256-bit AVX instructions in the auto-vectorizer.  */
+#define TARGET_PREFER_AVX256   (prefer_vector_width_type == PVW_AVX256)
+
 #define IX86_HLE_ACQUIRE (1 << 16)
 #define IX86_HLE_RELEASE (1 << 17)
 

diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 0fb46989ef5cd56a54d36de407a6fbd5b5ce1f3e..ce4ec7e8ecf261edc65239d856b8c119cfee1313 100644 (file)
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -182,6 +182,10 @@ int x_ix86_tune_no_default
 TargetSave
 enum ix86_veclibabi x_ix86_veclibabi_type
 
+;; -mprefer-vector-width=
+TargetSave
+enum prefer_vector_width x_prefer_vector_width_type
+
 ;; x86 options
 m128bit-long-double
 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
@@ -588,12 +592,28 @@ Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
 or znver1 and Haifa scheduling is selected.
 
 mprefer-avx128
-Target Report Mask(PREFER_AVX128) Save
+Target Alias(mprefer-vector-width=, 128, 256)
 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
 
-mprefer-avx256
-Target Report Mask(PREFER_AVX256) Var(ix86_target_flags) Save
-Use 256-bit AVX instructions instead of 512-bit AVX instructions in the auto-vectorizer.
+mprefer-vector-width=
+Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE)
+Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
+
+Enum
+Name(prefer_vector_width) Type(enum prefer_vector_width)
+Known preferred register vector length (to use with the -mprefer-vector-width= option)
+
+EnumValue
+Enum(prefer_vector_width) String(none) Value(PVW_NONE)
+
+EnumValue
+Enum(prefer_vector_width) String(128) Value(PVW_AVX128)
+
+EnumValue
+Enum(prefer_vector_width) String(256) Value(PVW_AVX256)
+
+EnumValue
+Enum(prefer_vector_width) String(512) Value(PVW_AVX512)
 
 ;; ISA support
 

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 47323e5b0da27e9badbd76fe43dd8dee3c79e8df..eeb87563dc8d7b32ad8dd225eca3045995a48007 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1196,7 +1196,7 @@ See RS/6000 and PowerPC Options.
 -mincoming-stack-boundary=@var{num} @gol
 -mcld  -mcx16  -msahf  -mmovbe  -mcrc32 @gol
 -mrecip  -mrecip=@var{opt} @gol
--mvzeroupper  -mprefer-avx128 -mprefer-avx256 @gol
+-mvzeroupper  -mprefer-avx128 -mprefer-vector-width=@var{opt} @gol
 -mmmx  -msse  -msse2  -msse3  -mssse3  -msse4.1  -msse4.2  -msse4  -mavx @gol
 -mavx2  -mavx512f  -mavx512pf  -mavx512er  -mavx512cd  -mavx512vl @gol
 -mavx512bw  -mavx512dq  -mavx512ifma  -mavx512vbmi  -msha  -maes @gol
@@ -26095,10 +26095,24 @@ intrinsics.
 This option instructs GCC to use 128-bit AVX instructions instead of
 256-bit AVX instructions in the auto-vectorizer.
 
-@item -mprefer-avx256
-@opindex mprefer-avx256
-This option instructs GCC to use 256-bit AVX instructions instead of
-512-bit AVX instructions in the auto-vectorizer.
+@item -mprefer-vector-width=@var{opt}
+@opindex mprefer-vector-width
+This option instructs GCC to use @var{opt}-bit vector width in instructions
+instead of default on the selected platform.
+
+@table @samp
+@item none
+No extra limitations applied to GCC other than defined by the selected platform.
+
+@item 128
+Prefer 128-bit vector width for instructions.
+
+@item 256
+Prefer 256-bit vector width for instructions.
+
+@item 512
+Prefer 512-bit vector width for instructions.
+@end table
 
 @item -mcx16
 @opindex mcx16

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 42282509f300ce1275b058be3d0ee5d250345902..a793d57ff71a53e85d940cf3eeeecd6666b177f6 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2017-11-21  Sergey Shalnov  <Sergey.Shalnov@intel.com>
+
+       * g++.dg/ext/pr57362.C (__attribute__): Test
+       prefer-vector-width=[128|256] target attribute.
+       * gcc.target/i386/avx512f-constant-float-return.c (dg-optioins):
+       Use -mprefer-vector-width=256 instead of -mprefer-avx256.
+       * gcc.target/i386/avx512f-prefer.c: Ditto.
+       * gcc.target/i386/pr82460-2.c: Ditto.
+
 2017-11-21  Martin Liska  <mliska@suse.cz>
 
        * g++.dg/cpp0x/constexpr-48089.C: Add quotes for constexpr

diff --git a/gcc/testsuite/g++.dg/ext/pr57362.C b/gcc/testsuite/g++.dg/ext/pr57362.C
index 3613b63a13728ba64b2e0cd3fa47760dc9a5ed1e..07270946d558ad4e43f1ce4749c12eeedebfb9a4 100644 (file)
--- a/gcc/testsuite/g++.dg/ext/pr57362.C
+++ b/gcc/testsuite/g++.dg/ext/pr57362.C
@@ -81,7 +81,9 @@ __attribute__((target("dispatch-scheduler")))
 int foo(void) { return 1; }
 __attribute__((target("prefer-avx128")))
 int foo(void) { return 1; }
-__attribute__((target("prefer-avx256")))
+__attribute__((target("prefer-vector-width=128")))
+int foo(void) { return 1; }
+__attribute__((target("prefer-vector-width=256")))
 int foo(void) { return 1; }
 __attribute__((target("32")))
 int foo(void) { return 1; }

diff --git a/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
index 153cf698127172856ea34bc87d2786b371eb999b..ed0becce61aab1c13720bdad007132b5a1c2a8eb 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
 /* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
 
 float

diff --git a/gcc/testsuite/gcc.target/i386/avx512f-prefer.c b/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
index defe51eb92859b84970acac94d55a44495daf387..a74ce0754be337b1eddfc15ea3a71511e61b789f 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
 /* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
 /* { dg-final { scan-assembler "vmulpd" } } */
 

diff --git a/gcc/testsuite/gcc.target/i386/pr82460-2.c b/gcc/testsuite/gcc.target/i386/pr82460-2.c
index 4d965216b59cdccfe3f44210285f0f953ca8f574..4a45beed715e2cb4efa63386bc525545b71c1e37 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/pr82460-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr82460-2.c
@@ -1,6 +1,6 @@
 /* PR target/82460 */
 /* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mno-prefer-avx256" } */
+/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mprefer-vector-width=none" } */
 /* We want to reuse the permutation mask in the loop, so use vpermt2b rather
    than vpermi2b.  */
 /* { dg-final { scan-assembler-not {\mvpermi2b\M} } } */