--- /dev/null
+FULL_SYSTEM = 0
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MESI_CMP_directory'
--- /dev/null
+FULL_SYSTEM = 0
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MOESI_CMP_directory'
--- /dev/null
+FULL_SYSTEM = 0
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MOESI_CMP_token'
--- /dev/null
+FULL_SYSTEM = 0
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MOESI_hammer'
MESI_CMP_directory-dir.sm
MESI_CMP_directory-dma.sm
standard_CMP-protocol.sm
-
else:
configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
- 'inorder-timing']
+ 'inorder-timing', 'rubytest']
if env['RUBY']:
- # Hack for Ruby
- configs += [c + '-ruby' for c in configs]
+ # With Ruby, A protocol must be specified in the environment
+ assert(env['PROTOCOL'])
+
+ #
+ # Is there a way to determine what is Protocol EnumVariable
+ # default and eliminate the need to hard code the default protocol below?
+ #
+ # If the binary includes the default ruby protocol, run both ruby and
+ # non-ruby versions of the tests. Otherwise just run the ruby versions.
+ #
+ if env['PROTOCOL'] == 'MI_example':
+ configs += [c + "-ruby" for c in configs]
+ else:
+ configs = [c + "-ruby-" + env['PROTOCOL'] for c in configs]
cwd = os.getcwd()
os.chdir(str(Dir('.').srcdir))
# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
-cpus = [ MemTest() for i in xrange(nb_cores) ]
+
+# ruby does not support atomic, functional, or uncacheable accesses
+cpus = [ MemTest(atomic=False, percent_functional=0, \
+ percent_uncacheable=0) \
+ for i in xrange(nb_cores) ]
# overwrite options.num_cpus with the nb_cores value
options.num_cpus = nb_cores
root = Root(system = system)
root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
+++ /dev/null
-import os
-import subprocess
-
-from os.path import dirname, join as joinpath
-
-import m5
-from m5.params import *
-
-def generate(config_file, cores=1, memories=1, memory_size=1024, \
- cache_size=32768, cache_assoc=8, dmas=1,
- ruby_tick='1t', ports_per_cpu=2, protocol='MOESI_CMP_directory'):
- default = joinpath(dirname(__file__), '../../src/mem/ruby/config')
- ruby_config = os.environ.get('RUBY_CONFIG', default)
- args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"),
- "-c", str(protocol),
- "-r", joinpath(ruby_config, config_file), "-p", str(cores),
- "-m", str(memories), "-s", str(memory_size), "-C", str(cache_size),
- "-A", str(cache_assoc), "-D", str(dmas)]
-
- temp_config = joinpath(m5.options.outdir, "ruby.config")
- ret = subprocess.call(args, stdout=file(temp_config, "w"))
- if ret != 0:
- raise RuntimeError, "subprocess failed!"
-
- return m5.objects.RubyMemory(clock = ruby_tick,
- config_file = temp_config,
- num_cpus = cores,
- range = AddrRange(str(memory_size)+"MB"),
- num_dmas = dmas,
- ports_per_core = ports_per_cpu)
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+# Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+
+if buildEnv['FULL_SYSTEM']:
+ panic("This script requires system-emulation mode (*_SE).")
+
+# Get paths we might need. It's expected this file is in m5/configs/example.
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+
+parser = optparse.OptionParser()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+parser.add_option("--l1d_size", type="string", default="256B")
+parser.add_option("--l1i_size", type="string", default="256B")
+parser.add_option("--l2_size", type="string", default="512B")
+parser.add_option("--l1d_assoc", type="int", default=2)
+parser.add_option("--l1i_assoc", type="int", default=2)
+parser.add_option("--l2_assoc", type="int", default=2)
+
+execfile(os.path.join(config_root, "configs/common", "Options.py"))
+
+(options, args) = parser.parse_args()
+
+#
+# create the tester and system, including ruby
+#
+tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
+
+system = System(physmem = PhysicalMemory())
+
+system.ruby = Ruby.create_system(options, system.physmem)
+
+assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+
+#
+# The tester is most effective when randomization is turned on and
+# artifical delay is randomly inserted on messages
+#
+system.ruby.randomization = True
+
+for ruby_port in system.ruby.cpu_ruby_ports:
+ #
+ # Tie the ruby tester ports to the ruby cpu ports
+ #
+ tester.cpuPort = ruby_port.port
+
+ #
+ # Tell the sequencer this is the ruby tester so that it
+ # copies the subblock back to the checker
+ #
+ ruby_port.using_ruby_tester = True
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( system = system )
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-
-import m5
-from m5.objects import *
-
-import ruby_config
-ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
-
-system = System(cpu = AtomicSimpleCPU(cpu_id=0),
- physmem = ruby_memory,
- membus = Bus())
-system.physmem.port = system.membus.port
-system.cpu.connectMemPorts(system.membus)
-system.cpu.clock = '2GHz'
-
-root = Root(system = system)
import m5
from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+
+if buildEnv['FULL_SYSTEM']:
+ panic("This script requires system-emulation mode (*_SE).")
+
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+
+parser = optparse.OptionParser()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+parser.add_option("--l1d_size", type="string", default="256B")
+parser.add_option("--l1i_size", type="string", default="256B")
+parser.add_option("--l2_size", type="string", default="512B")
+parser.add_option("--l1d_assoc", type="int", default=2)
+parser.add_option("--l1i_assoc", type="int", default=2)
+parser.add_option("--l2_assoc", type="int", default=2)
+
+execfile(os.path.join(config_root, "configs/common", "Options.py"))
+
+(options, args) = parser.parse_args()
nb_cores = 4
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
-import ruby_config
-ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
+# overwrite the num_cpus to equal nb_cores
+options.num_cpus = nb_cores
# system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
+system = System(cpu = cpus,
+ physmem = PhysicalMemory())
-# add L1 caches
-for cpu in cpus:
- cpu.connectMemPorts(system.membus)
- cpu.clock = '2GHz'
+system.ruby = Ruby.create_system(options, system.physmem)
-# connect memory to membus
-system.physmem.port = system.membus.port
+assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+for (i, cpu) in enumerate(system.cpu):
+ #
+ # Tie the cpu ports to the ruby cpu ports
+ #
+ cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
+ cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
# -----------------------
# run simulation
root = Root( system = system )
root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
import m5
from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
-import ruby_config
-ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
+if buildEnv['FULL_SYSTEM']:
+ panic("This script requires system-emulation mode (*_SE).")
+
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+
+parser = optparse.OptionParser()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+parser.add_option("--l1d_size", type="string", default="256B")
+parser.add_option("--l1i_size", type="string", default="256B")
+parser.add_option("--l2_size", type="string", default="512B")
+parser.add_option("--l1d_assoc", type="int", default=2)
+parser.add_option("--l1i_assoc", type="int", default=2)
+parser.add_option("--l2_assoc", type="int", default=2)
+
+execfile(os.path.join(config_root, "configs/common", "Options.py"))
+
+(options, args) = parser.parse_args()
+
+# this is a uniprocessor only test
+options.num_cpus = 1
cpu = TimingSimpleCPU(cpu_id=0)
system = System(cpu = cpu,
- physmem = ruby_memory,
- membus = Bus())
-system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
-cpu.clock = '2GHz'
+ physmem = PhysicalMemory())
+
+system.ruby = Ruby.create_system(options, system.physmem)
+
+assert(len(system.ruby.cpu_ruby_ports) == 1)
+
+#
+# Tie the cpu cache ports to the ruby cpu ports and
+# physmem, respectively
+#
+cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
+cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
+
+# -----------------------
+# run simulation
+# -----------------------
root = Root(system = system)
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
+++ /dev/null
-[root]
-type=Root
-children=system
-dummy=0
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
-file=
-latency=30000
-latency_var=0
-null=false
-num_cpus=1
-phase=0
-range=0:134217727
-stats_file=ruby.stats
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-
-================ Begin RubySystem Configuration Print ================
-
-RubySystem config:
- random_seed: 952703
- randomization: 0
- tech_nm: 45
- freq_mhz: 3000
- block_size_bytes: 64
- block_size_bits: 6
- memory_size_bytes: 1073741824
- memory_size_bits: 30
-DMA_Controller config: DMAController_0
- version: 0
- buffer_size: 32
- dma_sequencer: DMASequencer_0
- number_of_TBEs: 128
- transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
- version: 0
- buffer_size: 32
- directory_latency: 6
- directory_name: DirectoryMemory_0
- memory_controller_name: MemoryControl_0
- memory_latency: 158
- number_of_TBEs: 128
- recycle_latency: 10
- to_mem_ctrl_latency: 1
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
- version: 0
- buffer_size: 32
- cache: l1u_0
- cache_response_latency: 12
- issue_latency: 2
- number_of_TBEs: 128
- sequencer: Sequencer_0
- transitions_per_cycle: 32
-Cache config: l1u_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 2
- num_cache_sets: 4
- cache_set_size_bytes: 256
- cache_set_size_Kbytes: 0.25
- cache_set_size_Mbytes: 0.000244141
- cache_size_bytes: 2048
- cache_size_Kbytes: 2
- cache_size_Mbytes: 0.00195312
-DirectoryMemory Global Config:
- number of directory memories: 1
- total memory size bytes: 1073741824
- total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
- controller: DirectoryController_0
- version: 0
- memory_bits: 30
- memory_size_bytes: 1073741824
- memory_size_Kbytes: 1.04858e+06
- memory_size_Mbytes: 1024
- memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
- controller: L1CacheController_0
- version: 0
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-
-Network Configuration
----------------------
-network: SIMPLE_NETWORK
-topology: theTopology
-
-virtual_net_0: active, ordered
-virtual_net_1: active, ordered
-virtual_net_2: active, ordered
-virtual_net_3: inactive
-virtual_net_4: active, ordered
-virtual_net_5: active, ordered
-
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
- L1Cache-0 -> Directory-0 net_lat: 7
- L1Cache-0 -> DMA-0 net_lat: 7
-
-Directory-0 Network Latencies
- Directory-0 -> L1Cache-0 net_lat: 7
- Directory-0 -> DMA-0 net_lat: 7
-
-DMA-0 Network Latencies
- DMA-0 -> L1Cache-0 net_lat: 7
- DMA-0 -> Directory-0 net_lat: 7
-
---- End Topology Print ---
-
-Profiler Configuration
-----------------------
-periodic_stats_period: 1000000
-
-================ End RubySystem Configuration Print ================
-
-
-Real time: Jul/06/2009 11:11:07
-
-Profiler Stats
---------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
-
-Virtual_time_in_seconds: 0.2
-Virtual_time_in_minutes: 0.00333333
-Virtual_time_in_hours: 5.55556e-05
-Virtual_time_in_days: 5.55556e-05
-
-Ruby_current_time: 3215001
-Ruby_start_time: 1
-Ruby_cycles: 3215000
-
-mbytes_resident: 144.742
-mbytes_total: 1329.5
-resident_ratio: 0.108872
-
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-instruction_executed: 1 [ 1 ]
-ruby_cycles_executed: 3215001 [ 3215001 ]
-cycles_per_instruction: 3.215e+06 [ 3.215e+06 ]
-misses_per_thousand_instructions: 0 [ 0 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-instructions_per_transaction: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
-L1D_cache cache stats:
- L1D_cache_total_misses: 0
- L1D_cache_total_demand_misses: 0
- L1D_cache_total_prefetches: 0
- L1D_cache_total_sw_prefetches: 0
- L1D_cache_total_hw_prefetches: 0
- L1D_cache_misses_per_transaction: 0
- L1D_cache_misses_per_instruction: 0
- L1D_cache_instructions_per_misses: NaN
-
- L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats:
- L1I_cache_total_misses: 0
- L1I_cache_total_demand_misses: 0
- L1I_cache_total_prefetches: 0
- L1I_cache_total_sw_prefetches: 0
- L1I_cache_total_hw_prefetches: 0
- L1I_cache_misses_per_transaction: 0
- L1I_cache_misses_per_instruction: 0
- L1I_cache_instructions_per_misses: NaN
-
- L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats:
- L2_cache_total_misses: 0
- L2_cache_total_demand_misses: 0
- L2_cache_total_prefetches: 0
- L2_cache_total_sw_prefetches: 0
- L2_cache_total_hw_prefetches: 0
- L2_cache_misses_per_transaction: 0
- L2_cache_misses_per_instruction: 0
- L2_cache_instructions_per_misses: NaN
-
- L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Busy Controller Counts:
-L1Cache-0:0
-Directory-0:0
-DMA-0:0
-
-Busy Bank Count:0
-
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle SW Prefetch Requests
-------------------------------------
-prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Resource Usage
---------------
-page_size: 4096
-user_time: 0
-system_time: 0
-page_reclaims: 37817
-page_faults: 0
-swaps: 0
-block_inputs: 0
-block_outputs: 40
-
-Network Stats
--------------
-
-switch_0_inlinks: 2
-switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0
- links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_1_inlinks: 2
-switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0
- links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_2_inlinks: 2
-switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_3_inlinks: 3
-switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0
- links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
-
-
- --- DMA ---
- - Event Counts -
-ReadRequest 0
-WriteRequest 0
-Data 0
-Ack 0
-
- - Transitions -
-READY ReadRequest 0 <--
-READY WriteRequest 0 <--
-
-BUSY_RD Data 0 <--
-
-BUSY_WR Ack 0 <--
-
- --- Directory ---
- - Event Counts -
-GETX 0
-GETS 0
-PUTX 0
-PUTX_NotOwner 0
-DMA_READ 0
-DMA_WRITE 0
-Memory_Data 0
-Memory_Ack 0
-
- - Transitions -
-I GETX 0 <--
-I PUTX_NotOwner 0 <--
-I DMA_READ 0 <--
-I DMA_WRITE 0 <--
-
-M GETX 0 <--
-M PUTX 0 <--
-M PUTX_NotOwner 0 <--
-M DMA_READ 0 <--
-M DMA_WRITE 0 <--
-
-M_DRD GETX 0 <--
-M_DRD PUTX 0 <--
-
-M_DWR GETX 0 <--
-M_DWR PUTX 0 <--
-
-M_DWRI Memory_Ack 0 <--
-
-IM GETX 0 <--
-IM GETS 0 <--
-IM PUTX 0 <--
-IM PUTX_NotOwner 0 <--
-IM DMA_READ 0 <--
-IM DMA_WRITE 0 <--
-IM Memory_Data 0 <--
-
-MI GETX 0 <--
-MI GETS 0 <--
-MI PUTX 0 <--
-MI PUTX_NotOwner 0 <--
-MI DMA_READ 0 <--
-MI DMA_WRITE 0 <--
-MI Memory_Ack 0 <--
-
-ID GETX 0 <--
-ID GETS 0 <--
-ID PUTX 0 <--
-ID PUTX_NotOwner 0 <--
-ID DMA_READ 0 <--
-ID DMA_WRITE 0 <--
-ID Memory_Data 0 <--
-
-ID_W GETX 0 <--
-ID_W GETS 0 <--
-ID_W PUTX 0 <--
-ID_W PUTX_NotOwner 0 <--
-ID_W DMA_READ 0 <--
-ID_W DMA_WRITE 0 <--
-ID_W Memory_Ack 0 <--
-
- --- L1Cache ---
- - Event Counts -
-Load 0
-Ifetch 0
-Store 0
-Data 0
-Fwd_GETX 0
-Inv 0
-Replacement 0
-Writeback_Ack 0
-Writeback_Nack 0
-
- - Transitions -
-I Load 0 <--
-I Ifetch 0 <--
-I Store 0 <--
-I Inv 0 <--
-I Replacement 0 <--
-
-II Writeback_Nack 0 <--
-
-M Load 0 <--
-M Ifetch 0 <--
-M Store 0 <--
-M Fwd_GETX 0 <--
-M Inv 0 <--
-M Replacement 0 <--
-
-MI Fwd_GETX 0 <--
-MI Inv 0 <--
-MI Writeback_Ack 0 <--
-
-IS Data 0 <--
-
-IM Data 0 <--
-
+++ /dev/null
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
-print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-hack: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:06
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby
-Global frequency set at 1000000000000 ticks per second
- Debug: Adding to filter: 'q' (Queue)
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 3215000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 105206 # Simulator instruction rate (inst/s)
-host_mem_usage 1361416 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 52654853 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 6404 # Number of instructions simulated
-sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 3215000 # Number of ticks simulated
-system.cpu.dtb.data_accesses 2060 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 2050 # DTB hits
-system.cpu.dtb.data_misses 10 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 1192 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 1185 # DTB read hits
-system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 865 # DTB write hits
-system.cpu.dtb.write_misses 3 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 6431 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 6414 # ITB hits
-system.cpu.itb.fetch_misses 17 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 6431 # number of cpu cycles simulated
-system.cpu.num_insts 6404 # Number of instructions executed
-system.cpu.num_refs 2060 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=1
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+num_int_nodes=4
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+buffer_size=0
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+recycle_latency=10
+to_l1_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links2.ext_node.directory
+directory_latency=6
+memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+to_mem_ctrl_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=3
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 13:57:44
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
+
+Virtual_time_in_seconds: 0.95
+Virtual_time_in_minutes: 0.0158333
+Virtual_time_in_hours: 0.000263889
+Virtual_time_in_days: 1.09954e-05
+
+Ruby_current_time: 275313
+Ruby_start_time: 0
+Ruby_cycles: 275313
+
+mbytes_resident: 34.4609
+mbytes_total: 34.4688
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 275314 [ 275314 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 30 count: 9645 average: 0.0134785 | standard deviation: 0.509043 | 9637 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standard deviation: 0 | 6920 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 30 count: 2725 average: 0.0477064 | standard deviation: 0.956852 | 2717 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 5879 average: 0 | standard deviation: 0 | 5879 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 7392
+page_faults: 2212
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.0889147
+ links_utilized_percent_switch_0_link_0: 0.0675913 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.110238 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Control: 1699 13592 [ 0 900 799 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.228653
+ links_utilized_percent_switch_1_link_0: 0.0938114 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.363495 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 1767 127224 [ 0 1767 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 1611 12888 [ 0 1611 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.144145
+ links_utilized_percent_switch_2_link_0: 0.0232826 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.265007 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Control: 1452 11616 [ 0 1452 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 3
+switch_3_outlinks: 3
+links_utilized_percent_switch_3: 0.246247
+ links_utilized_percent_switch_3_link_0: 0.270365 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.375246 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.0931304 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 1185
+Ifetch 6414
+Store 865
+Inv 1041
+L1_Replacement 1354
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_GET_INSTR 0
+Data 0
+Data_Exclusive 583
+DataS_fromL1 0
+Data_all_Acks 907
+Ack 0
+Ack_all 0
+WB_Ack 436
+
+ - Transitions -
+NP Load 525
+NP Ifetch 646
+NP Store 191
+NP Inv 356
+NP L1_Replacement 0 <--
+
+I Load 58
+I Ifetch 45
+I Store 25
+I Inv 0 <--
+I L1_Replacement 556
+
+S Load 0 <--
+S Ifetch 5723
+S Store 0 <--
+S Inv 325
+S L1_Replacement 362
+
+E Load 454
+E Ifetch 0 <--
+E Store 71
+E Inv 219
+E L1_Replacement 291
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 148
+M Ifetch 0 <--
+M Store 578
+M Inv 141
+M L1_Replacement 145
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 0 <--
+IS L1_Replacement 0 <--
+IS Data_Exclusive 583
+IS DataS_fromL1 0 <--
+IS Data_all_Acks 691
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 0 <--
+IM Data_all_Acks 216
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 0 <--
+SM L1_Replacement 0 <--
+SM Ack 0 <--
+SM Ack_all 0 <--
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 0 <--
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 436
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GET_INSTR 691
+L1_GETS 592
+L1_GETX 220
+L1_UPGRADE 0
+L1_PUTX 436
+L1_PUTX_old 0
+Fwd_L1_GETX 0
+Fwd_L1_GETS 0
+Fwd_L1_GET_INSTR 0
+L2_Replacement 142
+L2_Replacement_clean 1310
+Mem_Data 1460
+Mem_Ack 1452
+WB_Data 141
+WB_Data_clean 0
+Ack 0
+Ack_all 900
+Unblock 0
+Unblock_Cancel 0
+Exclusive_Unblock 799
+MEM_Inv 0
+
+ - Transitions -
+NP L1_GET_INSTR 686
+NP L1_GETS 570
+NP L1_GETX 204
+NP L1_PUTX 0 <--
+NP L1_PUTX_old 0 <--
+
+SS L1_GET_INSTR 5
+SS L1_GETS 0 <--
+SS L1_GETX 0 <--
+SS L1_UPGRADE 0 <--
+SS L1_PUTX 0 <--
+SS L1_PUTX_old 0 <--
+SS L2_Replacement 0 <--
+SS L2_Replacement_clean 681
+SS MEM_Inv 0 <--
+
+M L1_GET_INSTR 0 <--
+M L1_GETS 13
+M L1_GETX 12
+M L1_PUTX 0 <--
+M L1_PUTX_old 0 <--
+M L2_Replacement 134
+M L2_Replacement_clean 277
+M MEM_Inv 0 <--
+
+MT L1_GET_INSTR 0 <--
+MT L1_GETS 0 <--
+MT L1_GETX 0 <--
+MT L1_PUTX 436
+MT L1_PUTX_old 0 <--
+MT L2_Replacement 8
+MT L2_Replacement_clean 352
+MT MEM_Inv 0 <--
+
+M_I L1_GET_INSTR 0 <--
+M_I L1_GETS 9
+M_I L1_GETX 4
+M_I L1_UPGRADE 0 <--
+M_I L1_PUTX 0 <--
+M_I L1_PUTX_old 0 <--
+M_I Mem_Ack 1452
+M_I MEM_Inv 0 <--
+
+MT_I L1_GET_INSTR 0 <--
+MT_I L1_GETS 0 <--
+MT_I L1_GETX 0 <--
+MT_I L1_UPGRADE 0 <--
+MT_I L1_PUTX 0 <--
+MT_I L1_PUTX_old 0 <--
+MT_I WB_Data 6
+MT_I WB_Data_clean 0 <--
+MT_I Ack_all 2
+MT_I MEM_Inv 0 <--
+
+MCT_I L1_GET_INSTR 0 <--
+MCT_I L1_GETS 0 <--
+MCT_I L1_GETX 0 <--
+MCT_I L1_UPGRADE 0 <--
+MCT_I L1_PUTX 0 <--
+MCT_I L1_PUTX_old 0 <--
+MCT_I WB_Data 135
+MCT_I WB_Data_clean 0 <--
+MCT_I Ack_all 217
+
+I_I L1_GET_INSTR 0 <--
+I_I L1_GETS 0 <--
+I_I L1_GETX 0 <--
+I_I L1_UPGRADE 0 <--
+I_I L1_PUTX 0 <--
+I_I L1_PUTX_old 0 <--
+I_I Ack 0 <--
+I_I Ack_all 681
+
+S_I L1_GET_INSTR 0 <--
+S_I L1_GETS 0 <--
+S_I L1_GETX 0 <--
+S_I L1_UPGRADE 0 <--
+S_I L1_PUTX 0 <--
+S_I L1_PUTX_old 0 <--
+S_I Ack 0 <--
+S_I Ack_all 0 <--
+S_I MEM_Inv 0 <--
+
+ISS L1_GET_INSTR 0 <--
+ISS L1_GETS 0 <--
+ISS L1_GETX 0 <--
+ISS L1_PUTX 0 <--
+ISS L1_PUTX_old 0 <--
+ISS L2_Replacement 0 <--
+ISS L2_Replacement_clean 0 <--
+ISS Mem_Data 570
+ISS MEM_Inv 0 <--
+
+IS L1_GET_INSTR 0 <--
+IS L1_GETS 0 <--
+IS L1_GETX 0 <--
+IS L1_PUTX 0 <--
+IS L1_PUTX_old 0 <--
+IS L2_Replacement 0 <--
+IS L2_Replacement_clean 0 <--
+IS Mem_Data 686
+IS MEM_Inv 0 <--
+
+IM L1_GET_INSTR 0 <--
+IM L1_GETS 0 <--
+IM L1_GETX 0 <--
+IM L1_PUTX 0 <--
+IM L1_PUTX_old 0 <--
+IM L2_Replacement 0 <--
+IM L2_Replacement_clean 0 <--
+IM Mem_Data 204
+IM MEM_Inv 0 <--
+
+SS_MB L1_GET_INSTR 0 <--
+SS_MB L1_GETS 0 <--
+SS_MB L1_GETX 0 <--
+SS_MB L1_UPGRADE 0 <--
+SS_MB L1_PUTX 0 <--
+SS_MB L1_PUTX_old 0 <--
+SS_MB L2_Replacement 0 <--
+SS_MB L2_Replacement_clean 0 <--
+SS_MB Unblock_Cancel 0 <--
+SS_MB Exclusive_Unblock 0 <--
+SS_MB MEM_Inv 0 <--
+
+MT_MB L1_GET_INSTR 0 <--
+MT_MB L1_GETS 0 <--
+MT_MB L1_GETX 0 <--
+MT_MB L1_UPGRADE 0 <--
+MT_MB L1_PUTX 0 <--
+MT_MB L1_PUTX_old 0 <--
+MT_MB L2_Replacement 0 <--
+MT_MB L2_Replacement_clean 0 <--
+MT_MB Unblock_Cancel 0 <--
+MT_MB Exclusive_Unblock 799
+MT_MB MEM_Inv 0 <--
+
+M_MB L1_GET_INSTR 0 <--
+M_MB L1_GETS 0 <--
+M_MB L1_GETX 0 <--
+M_MB L1_UPGRADE 0 <--
+M_MB L1_PUTX 0 <--
+M_MB L1_PUTX_old 0 <--
+M_MB L2_Replacement 0 <--
+M_MB L2_Replacement_clean 0 <--
+M_MB Exclusive_Unblock 0 <--
+M_MB MEM_Inv 0 <--
+
+MT_IIB L1_GET_INSTR 0 <--
+MT_IIB L1_GETS 0 <--
+MT_IIB L1_GETX 0 <--
+MT_IIB L1_UPGRADE 0 <--
+MT_IIB L1_PUTX 0 <--
+MT_IIB L1_PUTX_old 0 <--
+MT_IIB L2_Replacement 0 <--
+MT_IIB L2_Replacement_clean 0 <--
+MT_IIB WB_Data 0 <--
+MT_IIB WB_Data_clean 0 <--
+MT_IIB Unblock 0 <--
+MT_IIB MEM_Inv 0 <--
+
+MT_IB L1_GET_INSTR 0 <--
+MT_IB L1_GETS 0 <--
+MT_IB L1_GETX 0 <--
+MT_IB L1_UPGRADE 0 <--
+MT_IB L1_PUTX 0 <--
+MT_IB L1_PUTX_old 0 <--
+MT_IB L2_Replacement 0 <--
+MT_IB L2_Replacement_clean 0 <--
+MT_IB WB_Data 0 <--
+MT_IB WB_Data_clean 0 <--
+MT_IB Unblock_Cancel 0 <--
+MT_IB MEM_Inv 0 <--
+
+MT_SB L1_GET_INSTR 0 <--
+MT_SB L1_GETS 0 <--
+MT_SB L1_GETX 0 <--
+MT_SB L1_UPGRADE 0 <--
+MT_SB L1_PUTX 0 <--
+MT_SB L1_PUTX_old 0 <--
+MT_SB L2_Replacement 0 <--
+MT_SB L2_Replacement_clean 0 <--
+MT_SB Unblock 0 <--
+MT_SB MEM_Inv 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+ memory_total_requests: 1737
+ memory_reads: 1460
+ memory_writes: 277
+ memory_refreshes: 574
+ memory_total_request_delays: 1092
+ memory_delays_per_request: 0.62867
+ memory_delays_in_input_queue: 133
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 959
+ memory_stalls_for_bank_busy: 199
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 32
+ memory_stalls_for_bus: 236
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 492
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61
+
+ --- Directory 0 ---
+ - Event Counts -
+Fetch 1460
+Data 277
+Memory_Data 1460
+Memory_Ack 277
+DMA_READ 0
+DMA_WRITE 0
+CleanReplacement 1175
+
+ - Transitions -
+I Fetch 1460
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+ID Fetch 0 <--
+ID Data 0 <--
+ID Memory_Data 0 <--
+ID DMA_READ 0 <--
+ID DMA_WRITE 0 <--
+
+ID_W Fetch 0 <--
+ID_W Data 0 <--
+ID_W Memory_Ack 0 <--
+ID_W DMA_READ 0 <--
+ID_W DMA_WRITE 0 <--
+
+M Data 277
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+M CleanReplacement 1175
+
+IM Fetch 0 <--
+IM Data 0 <--
+IM Memory_Data 1460
+IM DMA_READ 0 <--
+IM DMA_WRITE 0 <--
+
+MI Fetch 0 <--
+MI Data 0 <--
+MI Memory_Ack 277
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+
+M_DRD Data 0 <--
+M_DRD DMA_READ 0 <--
+M_DRD DMA_WRITE 0 <--
+
+M_DRDI Fetch 0 <--
+M_DRDI Data 0 <--
+M_DRDI Memory_Ack 0 <--
+M_DRDI DMA_READ 0 <--
+M_DRDI DMA_WRITE 0 <--
+
+M_DWR Data 0 <--
+M_DWR DMA_READ 0 <--
+M_DWR DMA_WRITE 0 <--
+
+M_DWRI Fetch 0 <--
+M_DWRI Data 0 <--
+M_DWRI Memory_Ack 0 <--
+M_DWRI DMA_READ 0 <--
+M_DWRI DMA_WRITE 0 <--
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 13:54:58
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 13:57:42
+M5 executing on svvint03
+command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 275313 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 8106 # Simulator instruction rate (inst/s)
+host_mem_usage 215916 # Number of bytes of host memory used
+host_seconds 0.79 # Real time elapsed on the host
+host_tick_rate 348501 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_insts 6404 # Number of instructions simulated
+sim_seconds 0.000275 # Number of seconds simulated
+sim_ticks 275313 # Number of ticks simulated
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1185 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 865 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 6415 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 275313 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=1
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+num_int_nodes=4
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+buffer_size=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+response_latency=2
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links2.ext_node.directory
+directory_latency=6
+memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=3
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 15:08:14
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
+
+Virtual_time_in_seconds: 0.8
+Virtual_time_in_minutes: 0.0133333
+Virtual_time_in_hours: 0.000222222
+Virtual_time_in_days: 9.25926e-06
+
+Ruby_current_time: 223854
+Ruby_start_time: 0
+Ruby_cycles: 223854
+
+mbytes_resident: 34.6055
+mbytes_total: 34.6133
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 223855 [ 223855 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L2Cache-0:0
+L1Cache-0:0
+
+Directory-0:0
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 7397
+page_faults: 2249
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.219641
+ links_utilized_percent_switch_0_link_0: 0.0760094 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.363272 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 248 17856 [ 0 0 248 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.295226
+ links_utilized_percent_switch_1_link_0: 0.152935 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.437517 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 2452 19616 [ 1354 1098 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 1114 8912 [ 0 1114 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 248 17856 [ 0 0 248 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 3356 26848 [ 1354 1098 904 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.140918
+ links_utilized_percent_switch_2_link_0: 0.03337 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.248466 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Request_Control: 1114 8912 [ 0 1114 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Control: 1098 8784 [ 0 1098 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 3
+switch_3_outlinks: 3
+links_utilized_percent_switch_3: 0.349752
+ links_utilized_percent_switch_3_link_0: 0.304037 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.611738 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.13348 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 248 17856 [ 0 0 248 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 1114 80208 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Control: 2452 19616 [ 1354 1098 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Request_Control: 1114 8912 [ 0 1114 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 1185
+Ifetch 6414
+Store 865
+L1_Replacement 1379
+Own_GETX 0
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_DMA 0
+Inv 0
+Ack 0
+Data 0
+Exclusive_Data 1362
+Writeback_Ack 0
+Writeback_Ack_Data 1354
+Writeback_Nack 0
+All_acks 191
+Use_Timeout 1361
+
+ - Transitions -
+I Load 525
+I Ifetch 646
+I Store 191
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_Replacement 0 <--
+O Fwd_GETX 0 <--
+O Fwd_GETS 0 <--
+O Fwd_DMA 0 <--
+
+M Load 308
+M Ifetch 3484
+M Store 51
+M L1_Replacement 1086
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_DMA 0 <--
+
+M_W Load 111
+M_W Ifetch 2284
+M_W Store 27
+M_W L1_Replacement 17
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 0 <--
+M_W Fwd_GETS 0 <--
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 1143
+
+MM Load 234
+MM Ifetch 0 <--
+MM Store 339
+MM L1_Replacement 268
+MM Fwd_GETX 0 <--
+MM Fwd_GETS 0 <--
+MM Fwd_DMA 0 <--
+
+MM_W Load 7
+MM_W Ifetch 0 <--
+MM_W Store 257
+MM_W L1_Replacement 8
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 0 <--
+MM_W Fwd_GETS 0 <--
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 218
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 0 <--
+IM Data 0 <--
+IM Exclusive_Data 191
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 0 <--
+SM Ack 0 <--
+SM Data 0 <--
+SM Exclusive_Data 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 0 <--
+OM Fwd_GETX 0 <--
+OM Fwd_GETS 0 <--
+OM Fwd_DMA 0 <--
+OM Ack 0 <--
+OM All_acks 191
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 0 <--
+IS Exclusive_Data 1171
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 1354
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GETS 1171
+L1_GETX 191
+L1_PUTO 0
+L1_PUTX 1354
+L1_PUTS_only 0
+L1_PUTS 0
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_DMA 0
+Own_GETX 0
+Inv 0
+IntAck 0
+ExtAck 0
+All_Acks 131
+Data 131
+Data_Exclusive 983
+L1_WBCLEANDATA 1059
+L1_WBDIRTYDATA 295
+Writeback_Ack 1098
+Writeback_Nack 0
+Unblock 0
+Exclusive_Unblock 1362
+L2_Replacement 1098
+
+ - Transitions -
+NP L1_GETS 983
+NP L1_GETX 131
+NP L1_PUTO 0 <--
+NP L1_PUTX 0 <--
+NP L1_PUTS 0 <--
+NP Inv 0 <--
+
+I L1_GETS 0 <--
+I L1_GETX 0 <--
+I L1_PUTO 0 <--
+I L1_PUTX 0 <--
+I L1_PUTS 0 <--
+I Inv 0 <--
+I L2_Replacement 0 <--
+
+ILS L1_GETS 0 <--
+ILS L1_GETX 0 <--
+ILS L1_PUTO 0 <--
+ILS L1_PUTX 0 <--
+ILS L1_PUTS_only 0 <--
+ILS L1_PUTS 0 <--
+ILS Inv 0 <--
+ILS L2_Replacement 0 <--
+
+ILX L1_GETS 0 <--
+ILX L1_GETX 0 <--
+ILX L1_PUTO 0 <--
+ILX L1_PUTX 1354
+ILX L1_PUTS_only 0 <--
+ILX L1_PUTS 0 <--
+ILX Fwd_GETX 0 <--
+ILX Fwd_GETS 0 <--
+ILX Fwd_DMA 0 <--
+ILX Inv 0 <--
+ILX Data 0 <--
+ILX L2_Replacement 0 <--
+
+ILO L1_GETS 0 <--
+ILO L1_GETX 0 <--
+ILO L1_PUTO 0 <--
+ILO L1_PUTX 0 <--
+ILO L1_PUTS 0 <--
+ILO Fwd_GETX 0 <--
+ILO Fwd_GETS 0 <--
+ILO Fwd_DMA 0 <--
+ILO Inv 0 <--
+ILO Data 0 <--
+ILO L2_Replacement 0 <--
+
+ILOX L1_GETS 0 <--
+ILOX L1_GETX 0 <--
+ILOX L1_PUTO 0 <--
+ILOX L1_PUTX 0 <--
+ILOX L1_PUTS 0 <--
+ILOX Fwd_GETX 0 <--
+ILOX Fwd_GETS 0 <--
+ILOX Fwd_DMA 0 <--
+ILOX Data 0 <--
+
+ILOS L1_GETS 0 <--
+ILOS L1_GETX 0 <--
+ILOS L1_PUTO 0 <--
+ILOS L1_PUTX 0 <--
+ILOS L1_PUTS_only 0 <--
+ILOS L1_PUTS 0 <--
+ILOS Fwd_GETX 0 <--
+ILOS Fwd_GETS 0 <--
+ILOS Fwd_DMA 0 <--
+ILOS Data 0 <--
+ILOS L2_Replacement 0 <--
+
+ILOSX L1_GETS 0 <--
+ILOSX L1_GETX 0 <--
+ILOSX L1_PUTO 0 <--
+ILOSX L1_PUTX 0 <--
+ILOSX L1_PUTS_only 0 <--
+ILOSX L1_PUTS 0 <--
+ILOSX Fwd_GETX 0 <--
+ILOSX Fwd_GETS 0 <--
+ILOSX Fwd_DMA 0 <--
+ILOSX Data 0 <--
+
+S L1_GETS 0 <--
+S L1_GETX 0 <--
+S L1_PUTX 0 <--
+S L1_PUTS 0 <--
+S Inv 0 <--
+S L2_Replacement 0 <--
+
+O L1_GETS 0 <--
+O L1_GETX 0 <--
+O L1_PUTX 0 <--
+O Fwd_GETX 0 <--
+O Fwd_GETS 0 <--
+O Fwd_DMA 0 <--
+O L2_Replacement 0 <--
+
+OLS L1_GETS 0 <--
+OLS L1_GETX 0 <--
+OLS L1_PUTX 0 <--
+OLS L1_PUTS_only 0 <--
+OLS L1_PUTS 0 <--
+OLS Fwd_GETX 0 <--
+OLS Fwd_GETS 0 <--
+OLS Fwd_DMA 0 <--
+OLS L2_Replacement 0 <--
+
+OLSX L1_GETS 0 <--
+OLSX L1_GETX 0 <--
+OLSX L1_PUTO 0 <--
+OLSX L1_PUTX 0 <--
+OLSX L1_PUTS_only 0 <--
+OLSX L1_PUTS 0 <--
+OLSX Fwd_GETX 0 <--
+OLSX Fwd_GETS 0 <--
+OLSX Fwd_DMA 0 <--
+OLSX L2_Replacement 0 <--
+
+SLS L1_GETS 0 <--
+SLS L1_GETX 0 <--
+SLS L1_PUTX 0 <--
+SLS L1_PUTS_only 0 <--
+SLS L1_PUTS 0 <--
+SLS Inv 0 <--
+SLS L2_Replacement 0 <--
+
+M L1_GETS 188
+M L1_GETX 60
+M L1_PUTO 0 <--
+M L1_PUTX 0 <--
+M L1_PUTS 0 <--
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_DMA 0 <--
+M L2_Replacement 1098
+
+IFGX L1_GETS 0 <--
+IFGX L1_GETX 0 <--
+IFGX L1_PUTO 0 <--
+IFGX L1_PUTX 0 <--
+IFGX L1_PUTS_only 0 <--
+IFGX L1_PUTS 0 <--
+IFGX Fwd_GETX 0 <--
+IFGX Fwd_GETS 0 <--
+IFGX Fwd_DMA 0 <--
+IFGX Inv 0 <--
+IFGX Data 0 <--
+IFGX Data_Exclusive 0 <--
+IFGX L2_Replacement 0 <--
+
+IFGS L1_GETS 0 <--
+IFGS L1_GETX 0 <--
+IFGS L1_PUTO 0 <--
+IFGS L1_PUTX 0 <--
+IFGS L1_PUTS_only 0 <--
+IFGS L1_PUTS 0 <--
+IFGS Fwd_GETX 0 <--
+IFGS Fwd_GETS 0 <--
+IFGS Fwd_DMA 0 <--
+IFGS Inv 0 <--
+IFGS Data 0 <--
+IFGS Data_Exclusive 0 <--
+IFGS L2_Replacement 0 <--
+
+ISFGS L1_GETS 0 <--
+ISFGS L1_GETX 0 <--
+ISFGS L1_PUTO 0 <--
+ISFGS L1_PUTX 0 <--
+ISFGS L1_PUTS_only 0 <--
+ISFGS L1_PUTS 0 <--
+ISFGS Fwd_GETX 0 <--
+ISFGS Fwd_GETS 0 <--
+ISFGS Fwd_DMA 0 <--
+ISFGS Inv 0 <--
+ISFGS Data 0 <--
+ISFGS L2_Replacement 0 <--
+
+IFGXX L1_GETS 0 <--
+IFGXX L1_GETX 0 <--
+IFGXX L1_PUTO 0 <--
+IFGXX L1_PUTX 0 <--
+IFGXX L1_PUTS_only 0 <--
+IFGXX L1_PUTS 0 <--
+IFGXX Fwd_GETX 0 <--
+IFGXX Fwd_GETS 0 <--
+IFGXX Fwd_DMA 0 <--
+IFGXX Inv 0 <--
+IFGXX IntAck 0 <--
+IFGXX All_Acks 0 <--
+IFGXX Data_Exclusive 0 <--
+IFGXX L2_Replacement 0 <--
+
+OFGX L1_GETS 0 <--
+OFGX L1_GETX 0 <--
+OFGX L1_PUTO 0 <--
+OFGX L1_PUTX 0 <--
+OFGX L1_PUTS_only 0 <--
+OFGX L1_PUTS 0 <--
+OFGX Fwd_GETX 0 <--
+OFGX Fwd_GETS 0 <--
+OFGX Fwd_DMA 0 <--
+OFGX Inv 0 <--
+OFGX L2_Replacement 0 <--
+
+OLSF L1_GETS 0 <--
+OLSF L1_GETX 0 <--
+OLSF L1_PUTO 0 <--
+OLSF L1_PUTX 0 <--
+OLSF L1_PUTS_only 0 <--
+OLSF L1_PUTS 0 <--
+OLSF Fwd_GETX 0 <--
+OLSF Fwd_GETS 0 <--
+OLSF Fwd_DMA 0 <--
+OLSF Inv 0 <--
+OLSF IntAck 0 <--
+OLSF All_Acks 0 <--
+OLSF L2_Replacement 0 <--
+
+ILOW L1_GETS 0 <--
+ILOW L1_GETX 0 <--
+ILOW L1_PUTO 0 <--
+ILOW L1_PUTX 0 <--
+ILOW L1_PUTS_only 0 <--
+ILOW L1_PUTS 0 <--
+ILOW Fwd_GETX 0 <--
+ILOW Fwd_GETS 0 <--
+ILOW Fwd_DMA 0 <--
+ILOW Inv 0 <--
+ILOW L1_WBCLEANDATA 0 <--
+ILOW L1_WBDIRTYDATA 0 <--
+ILOW Unblock 0 <--
+ILOW L2_Replacement 0 <--
+
+ILOXW L1_GETS 0 <--
+ILOXW L1_GETX 0 <--
+ILOXW L1_PUTO 0 <--
+ILOXW L1_PUTX 0 <--
+ILOXW L1_PUTS_only 0 <--
+ILOXW L1_PUTS 0 <--
+ILOXW Fwd_GETX 0 <--
+ILOXW Fwd_GETS 0 <--
+ILOXW Fwd_DMA 0 <--
+ILOXW Inv 0 <--
+ILOXW L1_WBCLEANDATA 0 <--
+ILOXW L1_WBDIRTYDATA 0 <--
+ILOXW Unblock 0 <--
+ILOXW L2_Replacement 0 <--
+
+ILOSW L1_GETS 0 <--
+ILOSW L1_GETX 0 <--
+ILOSW L1_PUTO 0 <--
+ILOSW L1_PUTX 0 <--
+ILOSW L1_PUTS_only 0 <--
+ILOSW L1_PUTS 0 <--
+ILOSW Fwd_GETX 0 <--
+ILOSW Fwd_GETS 0 <--
+ILOSW Fwd_DMA 0 <--
+ILOSW Inv 0 <--
+ILOSW L1_WBCLEANDATA 0 <--
+ILOSW L1_WBDIRTYDATA 0 <--
+ILOSW Unblock 0 <--
+ILOSW L2_Replacement 0 <--
+
+ILOSXW L1_GETS 0 <--
+ILOSXW L1_GETX 0 <--
+ILOSXW L1_PUTO 0 <--
+ILOSXW L1_PUTX 0 <--
+ILOSXW L1_PUTS_only 0 <--
+ILOSXW L1_PUTS 0 <--
+ILOSXW Fwd_GETX 0 <--
+ILOSXW Fwd_GETS 0 <--
+ILOSXW Fwd_DMA 0 <--
+ILOSXW Inv 0 <--
+ILOSXW L1_WBCLEANDATA 0 <--
+ILOSXW L1_WBDIRTYDATA 0 <--
+ILOSXW Unblock 0 <--
+ILOSXW L2_Replacement 0 <--
+
+SLSW L1_GETS 0 <--
+SLSW L1_GETX 0 <--
+SLSW L1_PUTO 0 <--
+SLSW L1_PUTX 0 <--
+SLSW L1_PUTS_only 0 <--
+SLSW L1_PUTS 0 <--
+SLSW Fwd_GETX 0 <--
+SLSW Fwd_GETS 0 <--
+SLSW Fwd_DMA 0 <--
+SLSW Inv 0 <--
+SLSW Unblock 0 <--
+SLSW L2_Replacement 0 <--
+
+OLSW L1_GETS 0 <--
+OLSW L1_GETX 0 <--
+OLSW L1_PUTO 0 <--
+OLSW L1_PUTX 0 <--
+OLSW L1_PUTS_only 0 <--
+OLSW L1_PUTS 0 <--
+OLSW Fwd_GETX 0 <--
+OLSW Fwd_GETS 0 <--
+OLSW Fwd_DMA 0 <--
+OLSW Inv 0 <--
+OLSW Unblock 0 <--
+OLSW L2_Replacement 0 <--
+
+ILSW L1_GETS 0 <--
+ILSW L1_GETX 0 <--
+ILSW L1_PUTO 0 <--
+ILSW L1_PUTX 0 <--
+ILSW L1_PUTS_only 0 <--
+ILSW L1_PUTS 0 <--
+ILSW Fwd_GETX 0 <--
+ILSW Fwd_GETS 0 <--
+ILSW Fwd_DMA 0 <--
+ILSW Inv 0 <--
+ILSW L1_WBCLEANDATA 0 <--
+ILSW Unblock 0 <--
+ILSW L2_Replacement 0 <--
+
+IW L1_GETS 0 <--
+IW L1_GETX 0 <--
+IW L1_PUTO 0 <--
+IW L1_PUTX 0 <--
+IW L1_PUTS_only 0 <--
+IW L1_PUTS 0 <--
+IW Fwd_GETX 0 <--
+IW Fwd_GETS 0 <--
+IW Fwd_DMA 0 <--
+IW Inv 0 <--
+IW L1_WBCLEANDATA 0 <--
+IW L2_Replacement 0 <--
+
+OW L1_GETS 0 <--
+OW L1_GETX 0 <--
+OW L1_PUTO 0 <--
+OW L1_PUTX 0 <--
+OW L1_PUTS_only 0 <--
+OW L1_PUTS 0 <--
+OW Fwd_GETX 0 <--
+OW Fwd_GETS 0 <--
+OW Fwd_DMA 0 <--
+OW Inv 0 <--
+OW Unblock 0 <--
+OW L2_Replacement 0 <--
+
+SW L1_GETS 0 <--
+SW L1_GETX 0 <--
+SW L1_PUTO 0 <--
+SW L1_PUTX 0 <--
+SW L1_PUTS_only 0 <--
+SW L1_PUTS 0 <--
+SW Fwd_GETX 0 <--
+SW Fwd_GETS 0 <--
+SW Fwd_DMA 0 <--
+SW Inv 0 <--
+SW Unblock 0 <--
+SW L2_Replacement 0 <--
+
+OXW L1_GETS 0 <--
+OXW L1_GETX 0 <--
+OXW L1_PUTO 0 <--
+OXW L1_PUTX 0 <--
+OXW L1_PUTS_only 0 <--
+OXW L1_PUTS 0 <--
+OXW Fwd_GETX 0 <--
+OXW Fwd_GETS 0 <--
+OXW Fwd_DMA 0 <--
+OXW Inv 0 <--
+OXW Unblock 0 <--
+OXW L2_Replacement 0 <--
+
+OLSXW L1_GETS 0 <--
+OLSXW L1_GETX 0 <--
+OLSXW L1_PUTO 0 <--
+OLSXW L1_PUTX 0 <--
+OLSXW L1_PUTS_only 0 <--
+OLSXW L1_PUTS 0 <--
+OLSXW Fwd_GETX 0 <--
+OLSXW Fwd_GETS 0 <--
+OLSXW Fwd_DMA 0 <--
+OLSXW Inv 0 <--
+OLSXW Unblock 0 <--
+OLSXW L2_Replacement 0 <--
+
+ILXW L1_GETS 0 <--
+ILXW L1_GETX 0 <--
+ILXW L1_PUTO 0 <--
+ILXW L1_PUTX 0 <--
+ILXW L1_PUTS_only 0 <--
+ILXW L1_PUTS 0 <--
+ILXW Fwd_GETX 0 <--
+ILXW Fwd_GETS 0 <--
+ILXW Fwd_DMA 0 <--
+ILXW Inv 0 <--
+ILXW Data 0 <--
+ILXW L1_WBCLEANDATA 1059
+ILXW L1_WBDIRTYDATA 295
+ILXW Unblock 0 <--
+ILXW L2_Replacement 0 <--
+
+IFLS L1_GETS 0 <--
+IFLS L1_GETX 0 <--
+IFLS L1_PUTO 0 <--
+IFLS L1_PUTX 0 <--
+IFLS L1_PUTS_only 0 <--
+IFLS L1_PUTS 0 <--
+IFLS Fwd_GETX 0 <--
+IFLS Fwd_GETS 0 <--
+IFLS Fwd_DMA 0 <--
+IFLS Inv 0 <--
+IFLS Unblock 0 <--
+IFLS L2_Replacement 0 <--
+
+IFLO L1_GETS 0 <--
+IFLO L1_GETX 0 <--
+IFLO L1_PUTO 0 <--
+IFLO L1_PUTX 0 <--
+IFLO L1_PUTS_only 0 <--
+IFLO L1_PUTS 0 <--
+IFLO Fwd_GETX 0 <--
+IFLO Fwd_GETS 0 <--
+IFLO Fwd_DMA 0 <--
+IFLO Inv 0 <--
+IFLO Unblock 0 <--
+IFLO L2_Replacement 0 <--
+
+IFLOX L1_GETS 0 <--
+IFLOX L1_GETX 0 <--
+IFLOX L1_PUTO 0 <--
+IFLOX L1_PUTX 0 <--
+IFLOX L1_PUTS_only 0 <--
+IFLOX L1_PUTS 0 <--
+IFLOX Fwd_GETX 0 <--
+IFLOX Fwd_GETS 0 <--
+IFLOX Fwd_DMA 0 <--
+IFLOX Inv 0 <--
+IFLOX Unblock 0 <--
+IFLOX Exclusive_Unblock 0 <--
+IFLOX L2_Replacement 0 <--
+
+IFLOXX L1_GETS 0 <--
+IFLOXX L1_GETX 0 <--
+IFLOXX L1_PUTO 0 <--
+IFLOXX L1_PUTX 0 <--
+IFLOXX L1_PUTS_only 0 <--
+IFLOXX L1_PUTS 0 <--
+IFLOXX Fwd_GETX 0 <--
+IFLOXX Fwd_GETS 0 <--
+IFLOXX Fwd_DMA 0 <--
+IFLOXX Inv 0 <--
+IFLOXX Unblock 0 <--
+IFLOXX Exclusive_Unblock 0 <--
+IFLOXX L2_Replacement 0 <--
+
+IFLOSX L1_GETS 0 <--
+IFLOSX L1_GETX 0 <--
+IFLOSX L1_PUTO 0 <--
+IFLOSX L1_PUTX 0 <--
+IFLOSX L1_PUTS_only 0 <--
+IFLOSX L1_PUTS 0 <--
+IFLOSX Fwd_GETX 0 <--
+IFLOSX Fwd_GETS 0 <--
+IFLOSX Fwd_DMA 0 <--
+IFLOSX Inv 0 <--
+IFLOSX Unblock 0 <--
+IFLOSX Exclusive_Unblock 0 <--
+IFLOSX L2_Replacement 0 <--
+
+IFLXO L1_GETS 0 <--
+IFLXO L1_GETX 0 <--
+IFLXO L1_PUTO 0 <--
+IFLXO L1_PUTX 0 <--
+IFLXO L1_PUTS_only 0 <--
+IFLXO L1_PUTS 0 <--
+IFLXO Fwd_GETX 0 <--
+IFLXO Fwd_GETS 0 <--
+IFLXO Fwd_DMA 0 <--
+IFLXO Inv 0 <--
+IFLXO Exclusive_Unblock 0 <--
+IFLXO L2_Replacement 0 <--
+
+IGS L1_GETS 0 <--
+IGS L1_GETX 0 <--
+IGS L1_PUTO 0 <--
+IGS L1_PUTX 0 <--
+IGS L1_PUTS_only 0 <--
+IGS L1_PUTS 0 <--
+IGS Fwd_GETX 0 <--
+IGS Fwd_GETS 0 <--
+IGS Fwd_DMA 0 <--
+IGS Own_GETX 0 <--
+IGS Inv 0 <--
+IGS Data 0 <--
+IGS Data_Exclusive 983
+IGS Unblock 0 <--
+IGS Exclusive_Unblock 983
+IGS L2_Replacement 0 <--
+
+IGM L1_GETS 0 <--
+IGM L1_GETX 0 <--
+IGM L1_PUTO 0 <--
+IGM L1_PUTX 0 <--
+IGM L1_PUTS_only 0 <--
+IGM L1_PUTS 0 <--
+IGM Fwd_GETX 0 <--
+IGM Fwd_GETS 0 <--
+IGM Fwd_DMA 0 <--
+IGM Own_GETX 0 <--
+IGM Inv 0 <--
+IGM ExtAck 0 <--
+IGM Data 131
+IGM Data_Exclusive 0 <--
+IGM L2_Replacement 0 <--
+
+IGMLS L1_GETS 0 <--
+IGMLS L1_GETX 0 <--
+IGMLS L1_PUTO 0 <--
+IGMLS L1_PUTX 0 <--
+IGMLS L1_PUTS_only 0 <--
+IGMLS L1_PUTS 0 <--
+IGMLS Inv 0 <--
+IGMLS IntAck 0 <--
+IGMLS ExtAck 0 <--
+IGMLS All_Acks 0 <--
+IGMLS Data 0 <--
+IGMLS Data_Exclusive 0 <--
+IGMLS L2_Replacement 0 <--
+
+IGMO L1_GETS 0 <--
+IGMO L1_GETX 0 <--
+IGMO L1_PUTO 0 <--
+IGMO L1_PUTX 0 <--
+IGMO L1_PUTS_only 0 <--
+IGMO L1_PUTS 0 <--
+IGMO Fwd_GETX 0 <--
+IGMO Fwd_GETS 0 <--
+IGMO Fwd_DMA 0 <--
+IGMO Own_GETX 0 <--
+IGMO ExtAck 0 <--
+IGMO All_Acks 131
+IGMO Exclusive_Unblock 131
+IGMO L2_Replacement 0 <--
+
+IGMIO L1_GETS 0 <--
+IGMIO L1_GETX 0 <--
+IGMIO L1_PUTO 0 <--
+IGMIO L1_PUTX 0 <--
+IGMIO L1_PUTS_only 0 <--
+IGMIO L1_PUTS 0 <--
+IGMIO Fwd_GETX 0 <--
+IGMIO Fwd_GETS 0 <--
+IGMIO Fwd_DMA 0 <--
+IGMIO Own_GETX 0 <--
+IGMIO ExtAck 0 <--
+IGMIO All_Acks 0 <--
+
+OGMIO L1_GETS 0 <--
+OGMIO L1_GETX 0 <--
+OGMIO L1_PUTO 0 <--
+OGMIO L1_PUTX 0 <--
+OGMIO L1_PUTS_only 0 <--
+OGMIO L1_PUTS 0 <--
+OGMIO Fwd_GETX 0 <--
+OGMIO Fwd_GETS 0 <--
+OGMIO Fwd_DMA 0 <--
+OGMIO Own_GETX 0 <--
+OGMIO ExtAck 0 <--
+OGMIO All_Acks 0 <--
+
+IGMIOF L1_GETS 0 <--
+IGMIOF L1_GETX 0 <--
+IGMIOF L1_PUTO 0 <--
+IGMIOF L1_PUTX 0 <--
+IGMIOF L1_PUTS_only 0 <--
+IGMIOF L1_PUTS 0 <--
+IGMIOF IntAck 0 <--
+IGMIOF All_Acks 0 <--
+IGMIOF Data_Exclusive 0 <--
+
+IGMIOFS L1_GETS 0 <--
+IGMIOFS L1_GETX 0 <--
+IGMIOFS L1_PUTO 0 <--
+IGMIOFS L1_PUTX 0 <--
+IGMIOFS L1_PUTS_only 0 <--
+IGMIOFS L1_PUTS 0 <--
+IGMIOFS Fwd_GETX 0 <--
+IGMIOFS Fwd_GETS 0 <--
+IGMIOFS Fwd_DMA 0 <--
+IGMIOFS Inv 0 <--
+IGMIOFS Data 0 <--
+IGMIOFS L2_Replacement 0 <--
+
+OGMIOF L1_GETS 0 <--
+OGMIOF L1_GETX 0 <--
+OGMIOF L1_PUTO 0 <--
+OGMIOF L1_PUTX 0 <--
+OGMIOF L1_PUTS_only 0 <--
+OGMIOF L1_PUTS 0 <--
+OGMIOF IntAck 0 <--
+OGMIOF All_Acks 0 <--
+
+II L1_GETS 0 <--
+II L1_GETX 0 <--
+II L1_PUTO 0 <--
+II L1_PUTX 0 <--
+II L1_PUTS_only 0 <--
+II L1_PUTS 0 <--
+II IntAck 0 <--
+II All_Acks 0 <--
+
+MM L1_GETS 0 <--
+MM L1_GETX 0 <--
+MM L1_PUTO 0 <--
+MM L1_PUTX 0 <--
+MM L1_PUTS_only 0 <--
+MM L1_PUTS 0 <--
+MM Fwd_GETX 0 <--
+MM Fwd_GETS 0 <--
+MM Fwd_DMA 0 <--
+MM Inv 0 <--
+MM Exclusive_Unblock 60
+MM L2_Replacement 0 <--
+
+SS L1_GETS 0 <--
+SS L1_GETX 0 <--
+SS L1_PUTO 0 <--
+SS L1_PUTX 0 <--
+SS L1_PUTS_only 0 <--
+SS L1_PUTS 0 <--
+SS Fwd_GETX 0 <--
+SS Fwd_GETS 0 <--
+SS Fwd_DMA 0 <--
+SS Inv 0 <--
+SS Unblock 0 <--
+SS L2_Replacement 0 <--
+
+OO L1_GETS 0 <--
+OO L1_GETX 0 <--
+OO L1_PUTO 0 <--
+OO L1_PUTX 0 <--
+OO L1_PUTS_only 0 <--
+OO L1_PUTS 0 <--
+OO Fwd_GETX 0 <--
+OO Fwd_GETS 0 <--
+OO Fwd_DMA 0 <--
+OO Inv 0 <--
+OO Unblock 0 <--
+OO Exclusive_Unblock 188
+OO L2_Replacement 0 <--
+
+OLSS L1_GETS 0 <--
+OLSS L1_GETX 0 <--
+OLSS L1_PUTO 0 <--
+OLSS L1_PUTX 0 <--
+OLSS L1_PUTS_only 0 <--
+OLSS L1_PUTS 0 <--
+OLSS Fwd_GETX 0 <--
+OLSS Fwd_GETS 0 <--
+OLSS Fwd_DMA 0 <--
+OLSS Inv 0 <--
+OLSS Unblock 0 <--
+OLSS L2_Replacement 0 <--
+
+OLSXS L1_GETS 0 <--
+OLSXS L1_GETX 0 <--
+OLSXS L1_PUTO 0 <--
+OLSXS L1_PUTX 0 <--
+OLSXS L1_PUTS_only 0 <--
+OLSXS L1_PUTS 0 <--
+OLSXS Fwd_GETX 0 <--
+OLSXS Fwd_GETS 0 <--
+OLSXS Fwd_DMA 0 <--
+OLSXS Inv 0 <--
+OLSXS Unblock 0 <--
+OLSXS L2_Replacement 0 <--
+
+SLSS L1_GETS 0 <--
+SLSS L1_GETX 0 <--
+SLSS L1_PUTO 0 <--
+SLSS L1_PUTX 0 <--
+SLSS L1_PUTS_only 0 <--
+SLSS L1_PUTS 0 <--
+SLSS Fwd_GETX 0 <--
+SLSS Fwd_GETS 0 <--
+SLSS Fwd_DMA 0 <--
+SLSS Inv 0 <--
+SLSS Unblock 0 <--
+SLSS L2_Replacement 0 <--
+
+OI L1_GETS 0 <--
+OI L1_GETX 0 <--
+OI L1_PUTO 0 <--
+OI L1_PUTX 0 <--
+OI L1_PUTS_only 0 <--
+OI L1_PUTS 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Nack 0 <--
+OI L2_Replacement 0 <--
+
+MI L1_GETS 0 <--
+MI L1_GETX 0 <--
+MI L1_PUTO 0 <--
+MI L1_PUTX 0 <--
+MI L1_PUTS_only 0 <--
+MI L1_PUTS 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 1098
+MI L2_Replacement 0 <--
+
+MII L1_GETS 0 <--
+MII L1_GETX 0 <--
+MII L1_PUTO 0 <--
+MII L1_PUTX 0 <--
+MII L1_PUTS_only 0 <--
+MII L1_PUTS 0 <--
+MII Writeback_Ack 0 <--
+MII Writeback_Nack 0 <--
+MII L2_Replacement 0 <--
+
+OLSI L1_GETS 0 <--
+OLSI L1_GETX 0 <--
+OLSI L1_PUTO 0 <--
+OLSI L1_PUTX 0 <--
+OLSI L1_PUTS_only 0 <--
+OLSI L1_PUTS 0 <--
+OLSI Fwd_GETX 0 <--
+OLSI Fwd_GETS 0 <--
+OLSI Fwd_DMA 0 <--
+OLSI Writeback_Ack 0 <--
+OLSI L2_Replacement 0 <--
+
+ILSI L1_GETS 0 <--
+ILSI L1_GETX 0 <--
+ILSI L1_PUTO 0 <--
+ILSI L1_PUTX 0 <--
+ILSI L1_PUTS_only 0 <--
+ILSI L1_PUTS 0 <--
+ILSI IntAck 0 <--
+ILSI All_Acks 0 <--
+ILSI Writeback_Ack 0 <--
+ILSI L2_Replacement 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+ memory_total_requests: 1308
+ memory_reads: 1114
+ memory_writes: 194
+ memory_refreshes: 467
+ memory_total_request_delays: 250
+ memory_delays_per_request: 0.191131
+ memory_delays_in_input_queue: 4
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 246
+ memory_stalls_for_bank_busy: 94
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 11
+ memory_stalls_for_bus: 62
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 79
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 75 17 45 40 54 99 29 16 19 22 32 34 52 48 38 30 39 21 21 27 28 37 55 22 31 22 32 70 84 104 13 52
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 131
+GETS 983
+PUTX 1098
+PUTO 0
+PUTO_SHARERS 0
+Unblock 0
+Last_Unblock 0
+Exclusive_Unblock 1114
+Clean_Writeback 904
+Dirty_Writeback 194
+Memory_Data 1114
+Memory_Ack 194
+DMA_READ 0
+DMA_WRITE 0
+Data 0
+
+ - Transitions -
+I GETX 131
+I GETS 983
+I PUTX 0 <--
+I PUTO 0 <--
+I Memory_Data 0 <--
+I Memory_Ack 191
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+S GETX 0 <--
+S GETS 0 <--
+S PUTX 0 <--
+S PUTO 0 <--
+S Memory_Data 0 <--
+S Memory_Ack 0 <--
+S DMA_READ 0 <--
+S DMA_WRITE 0 <--
+
+O GETX 0 <--
+O GETS 0 <--
+O PUTX 0 <--
+O PUTO 0 <--
+O PUTO_SHARERS 0 <--
+O Memory_Data 0 <--
+O Memory_Ack 0 <--
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+
+M GETX 0 <--
+M GETS 0 <--
+M PUTX 1098
+M PUTO 0 <--
+M PUTO_SHARERS 0 <--
+M Memory_Data 0 <--
+M Memory_Ack 0 <--
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+
+IS GETX 0 <--
+IS GETS 0 <--
+IS PUTX 0 <--
+IS PUTO 0 <--
+IS PUTO_SHARERS 0 <--
+IS Unblock 0 <--
+IS Exclusive_Unblock 983
+IS Memory_Data 983
+IS Memory_Ack 2
+IS DMA_READ 0 <--
+IS DMA_WRITE 0 <--
+
+SS GETX 0 <--
+SS GETS 0 <--
+SS PUTX 0 <--
+SS PUTO 0 <--
+SS PUTO_SHARERS 0 <--
+SS Unblock 0 <--
+SS Last_Unblock 0 <--
+SS Memory_Data 0 <--
+SS Memory_Ack 0 <--
+SS DMA_READ 0 <--
+SS DMA_WRITE 0 <--
+
+OO GETX 0 <--
+OO GETS 0 <--
+OO PUTX 0 <--
+OO PUTO 0 <--
+OO PUTO_SHARERS 0 <--
+OO Unblock 0 <--
+OO Last_Unblock 0 <--
+OO Memory_Data 0 <--
+OO Memory_Ack 0 <--
+OO DMA_READ 0 <--
+OO DMA_WRITE 0 <--
+
+MO GETX 0 <--
+MO GETS 0 <--
+MO PUTX 0 <--
+MO PUTO 0 <--
+MO PUTO_SHARERS 0 <--
+MO Unblock 0 <--
+MO Exclusive_Unblock 0 <--
+MO Memory_Data 0 <--
+MO Memory_Ack 0 <--
+MO DMA_READ 0 <--
+MO DMA_WRITE 0 <--
+
+MM GETX 0 <--
+MM GETS 0 <--
+MM PUTX 0 <--
+MM PUTO 0 <--
+MM PUTO_SHARERS 0 <--
+MM Exclusive_Unblock 131
+MM Memory_Data 131
+MM Memory_Ack 1
+MM DMA_READ 0 <--
+MM DMA_WRITE 0 <--
+
+
+MI GETX 0 <--
+MI GETS 0 <--
+MI PUTX 0 <--
+MI PUTO 0 <--
+MI PUTO_SHARERS 0 <--
+MI Unblock 0 <--
+MI Clean_Writeback 904
+MI Dirty_Writeback 194
+MI Memory_Data 0 <--
+MI Memory_Ack 0 <--
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+
+MIS GETX 0 <--
+MIS GETS 0 <--
+MIS PUTX 0 <--
+MIS PUTO 0 <--
+MIS PUTO_SHARERS 0 <--
+MIS Unblock 0 <--
+MIS Clean_Writeback 0 <--
+MIS Dirty_Writeback 0 <--
+MIS Memory_Data 0 <--
+MIS Memory_Ack 0 <--
+MIS DMA_READ 0 <--
+MIS DMA_WRITE 0 <--
+
+OS GETX 0 <--
+OS GETS 0 <--
+OS PUTX 0 <--
+OS PUTO 0 <--
+OS PUTO_SHARERS 0 <--
+OS Unblock 0 <--
+OS Clean_Writeback 0 <--
+OS Dirty_Writeback 0 <--
+OS Memory_Data 0 <--
+OS Memory_Ack 0 <--
+OS DMA_READ 0 <--
+OS DMA_WRITE 0 <--
+
+OSS GETX 0 <--
+OSS GETS 0 <--
+OSS PUTX 0 <--
+OSS PUTO 0 <--
+OSS PUTO_SHARERS 0 <--
+OSS Unblock 0 <--
+OSS Clean_Writeback 0 <--
+OSS Dirty_Writeback 0 <--
+OSS Memory_Data 0 <--
+OSS Memory_Ack 0 <--
+OSS DMA_READ 0 <--
+OSS DMA_WRITE 0 <--
+
+XI_M GETX 0 <--
+XI_M GETS 0 <--
+XI_M PUTX 0 <--
+XI_M PUTO 0 <--
+XI_M PUTO_SHARERS 0 <--
+XI_M Memory_Data 0 <--
+XI_M Memory_Ack 0 <--
+XI_M DMA_READ 0 <--
+XI_M DMA_WRITE 0 <--
+
+XI_U GETX 0 <--
+XI_U GETS 0 <--
+XI_U PUTX 0 <--
+XI_U PUTO 0 <--
+XI_U PUTO_SHARERS 0 <--
+XI_U Exclusive_Unblock 0 <--
+XI_U Memory_Ack 0 <--
+XI_U DMA_READ 0 <--
+XI_U DMA_WRITE 0 <--
+
+OI_D GETX 0 <--
+OI_D GETS 0 <--
+OI_D PUTX 0 <--
+OI_D PUTO 0 <--
+OI_D PUTO_SHARERS 0 <--
+OI_D DMA_READ 0 <--
+OI_D DMA_WRITE 0 <--
+OI_D Data 0 <--
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 14:49:51
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 15:08:13
+M5 executing on svvint05
+command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 223854 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 11859 # Simulator instruction rate (inst/s)
+host_mem_usage 216064 # Number of bytes of host memory used
+host_seconds 0.55 # Real time elapsed on the host
+host_tick_rate 407003 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_insts 6404 # Number of instructions simulated
+sim_seconds 0.000224 # Number of seconds simulated
+sim_ticks 223854 # Number of ticks simulated
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1185 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 865 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 6415 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 223854 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=1
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+num_int_nodes=4
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+N_tokens=2
+buffer_size=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+N_tokens=2
+buffer_size=0
+filtering_enabled=true
+l2_request_latency=10
+l2_response_latency=10
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links2.ext_node.directory
+directory_latency=6
+distributed_persistent=true
+fixed_timeout_latency=300
+l2_select_num_bits=0
+memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=3
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: active, ordered
+virtual_net_3: active, unordered
+virtual_net_4: active, unordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 15:55:45
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.43
+Virtual_time_in_minutes: 0.00716667
+Virtual_time_in_hours: 0.000119444
+Virtual_time_in_days: 4.97685e-06
+
+Ruby_current_time: 236654
+Ruby_start_time: 0
+Ruby_cycles: 236654
+
+mbytes_resident: 34.4141
+mbytes_total: 34.4219
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 236655 [ 236655 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 2 max: 279 count: 8464 average: 26.9601 | standard deviation: 58.5578 | 0 7082 0 0 0 0 0 0 0 0 0 0 0 220 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 268 180 200 165 117 12 3 8 3 4 46 30 32 33 37 0 1 1 1 2 1 4 1 3 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 279 count: 6414 average: 18.8457 | standard deviation: 49.2277 | 0 5768 0 0 0 0 0 0 0 0 0 0 0 55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125 84 121 94 59 8 2 4 1 3 20 12 18 22 8 0 1 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 279 count: 1185 average: 66.1527 | standard deviation: 80.7635 | 0 660 0 0 0 0 0 0 0 0 0 0 0 99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 56 67 56 46 4 0 3 2 0 24 12 14 10 10 0 0 0 1 1 1 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 213 count: 865 average: 33.437 | standard deviation: 63.4371 | 0 654 0 0 0 0 0 0 0 0 0 0 0 66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 40 12 15 12 0 1 1 0 1 2 6 0 1 19 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 7348
+page_faults: 2239
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.164956
+ links_utilized_percent_switch_0_link_0: 0.0658979 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.264014 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.0968503
+ links_utilized_percent_switch_1_link_0: 0.0660035 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.127697 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.12111
+ links_utilized_percent_switch_2_link_0: 0.0212652 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.220955 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 3
+switch_3_outlinks: 3
+links_utilized_percent_switch_3: 0.204222
+ links_utilized_percent_switch_3_link_0: 0.263592 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.264014 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.0850609 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 1185
+Ifetch 6414
+Store 865
+L1_Replacement 1375
+Data_Shared 154
+Data_Owner 0
+Data_All_Tokens 1228
+Ack 38
+Ack_All_Tokens 0
+Transient_GETX 0
+Transient_Local_GETX 0
+Transient_GETS 0
+Transient_Local_GETS 0
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 0
+Persistent_GETS 0
+Own_Lock_or_Unlock 0
+Request_Timeout 0
+Use_TimeoutStarverX 0
+Use_TimeoutStarverS 0
+Use_TimeoutNoStarvers 1227
+
+ - Transitions -
+NP Load 525
+NP Ifetch 646
+NP Store 191
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 0 <--
+
+S Load 166
+S Ifetch 314
+S Store 20
+S L1_Replacement 134
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 0 <--
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 0 <--
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 0 <--
+
+M Load 184
+M Ifetch 3447
+M Store 33
+M L1_Replacement 952
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 0 <--
+M Persistent_GETS 0 <--
+M Own_Lock_or_Unlock 0 <--
+
+MM Load 221
+MM Ifetch 0 <--
+MM Store 333
+MM L1_Replacement 268
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 0 <--
+MM Persistent_GETS 0 <--
+MM Own_Lock_or_Unlock 0 <--
+
+M_W Load 69
+M_W Ifetch 2007
+M_W Store 25
+M_W L1_Replacement 14
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 0 <--
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 0 <--
+M_W Persistent_GETX 0 <--
+M_W Persistent_GETS 0 <--
+M_W Own_Lock_or_Unlock 0 <--
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 991
+
+MM_W Load 20
+MM_W Ifetch 0 <--
+MM_W Store 263
+MM_W L1_Replacement 7
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 0 <--
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 0 <--
+MM_W Persistent_GETX 0 <--
+MM_W Persistent_GETS 0 <--
+MM_W Own_Lock_or_Unlock 0 <--
+MM_W Use_TimeoutStarverX 0 <--
+MM_W Use_TimeoutStarverS 0 <--
+MM_W Use_TimeoutNoStarvers 236
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 0 <--
+IM Data_All_Tokens 191
+IM Ack 7
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 0 <--
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 0 <--
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 0 <--
+IM Persistent_GETS 0 <--
+IM Own_Lock_or_Unlock 0 <--
+IM Request_Timeout 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 20
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 0 <--
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 0 <--
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 0 <--
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 0 <--
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 0 <--
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 0 <--
+OM Persistent_GETS 0 <--
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 154
+IS Data_Owner 0 <--
+IS Data_All_Tokens 1017
+IS Ack 31
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 0 <--
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 0 <--
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 0 <--
+IS Persistent_GETS 0 <--
+IS Own_Lock_or_Unlock 0 <--
+IS Request_Timeout 0 <--
+
+I_L Load 0 <--
+I_L Ifetch 0 <--
+I_L Store 0 <--
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 0 <--
+I_L Persistent_GETS 0 <--
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 0 <--
+S_L Ifetch 0 <--
+S_L Store 0 <--
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 0 <--
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 0 <--
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 0 <--
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 0 <--
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 0 <--
+IM_L Persistent_GETS 0 <--
+IM_L Own_Lock_or_Unlock 0 <--
+IM_L Request_Timeout 0 <--
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 0 <--
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 0 <--
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 0 <--
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 0 <--
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 0 <--
+IS_L Persistent_GETS 0 <--
+IS_L Own_Lock_or_Unlock 0 <--
+IS_L Request_Timeout 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GETS 1140
+L1_GETS_Last_Token 31
+L1_GETX 211
+L1_INV 0
+Transient_GETX 0
+Transient_GETS 0
+Transient_GETS_Last_Token 0
+L2_Replacement 1276
+Writeback_Tokens 82
+Writeback_Shared_Data 0
+Writeback_All_Tokens 1272
+Writeback_Owned 0
+Data_Shared 0
+Data_Owner 0
+Data_All_Tokens 0
+Ack 0
+Ack_All_Tokens 0
+Persistent_GETX 0
+Persistent_GETS 0
+Own_Lock_or_Unlock 0
+
+ - Transitions -
+NP L1_GETS 986
+NP L1_GETX 138
+NP L1_INV 0 <--
+NP Transient_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Writeback_Tokens 82
+NP Writeback_Shared_Data 0 <--
+NP Writeback_All_Tokens 1202
+NP Writeback_Owned 0 <--
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I L1_GETS 0 <--
+I L1_GETS_Last_Token 31
+I L1_GETX 7
+I L1_INV 0 <--
+I Transient_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I L2_Replacement 130
+I Writeback_Tokens 0 <--
+I Writeback_Shared_Data 0 <--
+I Writeback_All_Tokens 18
+I Writeback_Owned 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 0 <--
+
+S L1_GETS 0 <--
+S L1_GETS_Last_Token 0 <--
+S L1_GETX 0 <--
+S L1_INV 0 <--
+S Transient_GETX 0 <--
+S Transient_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S L2_Replacement 0 <--
+S Writeback_Tokens 0 <--
+S Writeback_Shared_Data 0 <--
+S Writeback_All_Tokens 0 <--
+S Writeback_Owned 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O L1_GETS 0 <--
+O L1_GETS_Last_Token 0 <--
+O L1_GETX 18
+O L1_INV 0 <--
+O Transient_GETX 0 <--
+O Transient_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O L2_Replacement 84
+O Writeback_Tokens 0 <--
+O Writeback_Shared_Data 0 <--
+O Writeback_All_Tokens 52
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 0 <--
+
+M L1_GETS 154
+M L1_GETX 48
+M L1_INV 0 <--
+M Transient_GETX 0 <--
+M Transient_GETS 0 <--
+M L2_Replacement 1062
+M Persistent_GETX 0 <--
+M Persistent_GETS 0 <--
+M Own_Lock_or_Unlock 0 <--
+
+I_L L1_GETS 0 <--
+I_L L1_GETX 0 <--
+I_L L1_INV 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L L2_Replacement 0 <--
+I_L Writeback_Tokens 0 <--
+I_L Writeback_Shared_Data 0 <--
+I_L Writeback_All_Tokens 0 <--
+I_L Writeback_Owned 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Persistent_GETX 0 <--
+I_L Persistent_GETS 0 <--
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L L1_GETS 0 <--
+S_L L1_GETS_Last_Token 0 <--
+S_L L1_GETX 0 <--
+S_L L1_INV 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L L2_Replacement 0 <--
+S_L Writeback_Tokens 0 <--
+S_L Writeback_Shared_Data 0 <--
+S_L Writeback_All_Tokens 0 <--
+S_L Writeback_Owned 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+ memory_total_requests: 1369
+ memory_reads: 1162
+ memory_writes: 207
+ memory_refreshes: 493
+ memory_total_request_delays: 529
+ memory_delays_per_request: 0.386413
+ memory_delays_in_input_queue: 185
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 344
+ memory_stalls_for_bank_busy: 101
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 19
+ memory_stalls_for_bus: 222
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 2
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 75 17 45 46 54 108 37 16 19 22 32 34 52 49 39 31 39 21 21 21 28 38 61 27 30 22 32 72 90 124 14 53
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 163
+GETS 1017
+Lockdown 0
+Unlockdown 0
+Own_Lock_or_Unlock 0
+Data_Owner 19
+Data_All_Tokens 188
+Ack_Owner 65
+Ack_Owner_All_Tokens 874
+Tokens 0
+Ack_All_Tokens 44
+Request_Timeout 0
+Memory_Data 1162
+Memory_Ack 207
+DMA_READ 0
+DMA_WRITE 0
+DMA_WRITE_All_Tokens 0
+
+ - Transitions -
+O GETX 145
+O GETS 1017
+O Lockdown 0 <--
+O Own_Lock_or_Unlock 0 <--
+O Data_Owner 0 <--
+O Data_All_Tokens 0 <--
+O Tokens 0 <--
+O Ack_All_Tokens 44
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+O DMA_WRITE_All_Tokens 0 <--
+
+NO GETX 18
+NO GETS 0 <--
+NO Lockdown 0 <--
+NO Own_Lock_or_Unlock 0 <--
+NO Data_Owner 19
+NO Data_All_Tokens 188
+NO Ack_Owner 65
+NO Ack_Owner_All_Tokens 874
+NO Tokens 0 <--
+NO DMA_READ 0 <--
+NO DMA_WRITE 0 <--
+
+L GETX 0 <--
+L GETS 0 <--
+L Lockdown 0 <--
+L Unlockdown 0 <--
+L Own_Lock_or_Unlock 0 <--
+L Data_Owner 0 <--
+L Data_All_Tokens 0 <--
+L Ack_Owner 0 <--
+L Ack_Owner_All_Tokens 0 <--
+L Tokens 0 <--
+L DMA_READ 0 <--
+L DMA_WRITE 0 <--
+
+O_W GETX 0 <--
+O_W GETS 0 <--
+O_W Lockdown 0 <--
+O_W Unlockdown 0 <--
+O_W Own_Lock_or_Unlock 0 <--
+O_W Data_Owner 0 <--
+O_W Ack_Owner 0 <--
+O_W Tokens 0 <--
+O_W Ack_All_Tokens 0 <--
+O_W Memory_Data 0 <--
+O_W Memory_Ack 207
+O_W DMA_READ 0 <--
+O_W DMA_WRITE 0 <--
+
+L_O_W GETX 0 <--
+L_O_W GETS 0 <--
+L_O_W Lockdown 0 <--
+L_O_W Unlockdown 0 <--
+L_O_W Own_Lock_or_Unlock 0 <--
+L_O_W Data_Owner 0 <--
+L_O_W Ack_Owner 0 <--
+L_O_W Tokens 0 <--
+L_O_W Ack_All_Tokens 0 <--
+L_O_W Memory_Data 0 <--
+L_O_W Memory_Ack 0 <--
+L_O_W DMA_READ 0 <--
+L_O_W DMA_WRITE 0 <--
+
+L_NO_W GETX 0 <--
+L_NO_W GETS 0 <--
+L_NO_W Lockdown 0 <--
+L_NO_W Unlockdown 0 <--
+L_NO_W Own_Lock_or_Unlock 0 <--
+L_NO_W Data_Owner 0 <--
+L_NO_W Ack_Owner 0 <--
+L_NO_W Tokens 0 <--
+L_NO_W Ack_All_Tokens 0 <--
+L_NO_W Memory_Data 0 <--
+L_NO_W DMA_READ 0 <--
+L_NO_W DMA_WRITE 0 <--
+
+DR_L_W GETX 0 <--
+DR_L_W GETS 0 <--
+DR_L_W Lockdown 0 <--
+DR_L_W Unlockdown 0 <--
+DR_L_W Own_Lock_or_Unlock 0 <--
+DR_L_W Data_Owner 0 <--
+DR_L_W Ack_Owner 0 <--
+DR_L_W Tokens 0 <--
+DR_L_W Ack_All_Tokens 0 <--
+DR_L_W Request_Timeout 0 <--
+DR_L_W Memory_Data 0 <--
+DR_L_W DMA_READ 0 <--
+DR_L_W DMA_WRITE 0 <--
+
+NO_W GETX 0 <--
+NO_W GETS 0 <--
+NO_W Lockdown 0 <--
+NO_W Unlockdown 0 <--
+NO_W Own_Lock_or_Unlock 0 <--
+NO_W Data_Owner 0 <--
+NO_W Ack_Owner 0 <--
+NO_W Tokens 0 <--
+NO_W Ack_All_Tokens 0 <--
+NO_W Memory_Data 1162
+NO_W DMA_READ 0 <--
+NO_W DMA_WRITE 0 <--
+
+O_DW_W GETX 0 <--
+O_DW_W GETS 0 <--
+O_DW_W Data_Owner 0 <--
+O_DW_W Ack_Owner 0 <--
+O_DW_W Tokens 0 <--
+O_DW_W Ack_All_Tokens 0 <--
+O_DW_W Memory_Ack 0 <--
+O_DW_W DMA_READ 0 <--
+O_DW_W DMA_WRITE 0 <--
+
+O_DR_W GETX 0 <--
+O_DR_W GETS 0 <--
+O_DR_W Lockdown 0 <--
+O_DR_W Unlockdown 0 <--
+O_DR_W Own_Lock_or_Unlock 0 <--
+O_DR_W Data_Owner 0 <--
+O_DR_W Ack_Owner 0 <--
+O_DR_W Tokens 0 <--
+O_DR_W Ack_All_Tokens 0 <--
+O_DR_W Memory_Data 0 <--
+O_DR_W DMA_READ 0 <--
+O_DR_W DMA_WRITE 0 <--
+
+O_DW GETX 0 <--
+O_DW GETS 0 <--
+O_DW Lockdown 0 <--
+O_DW Own_Lock_or_Unlock 0 <--
+O_DW Data_Owner 0 <--
+O_DW Data_All_Tokens 0 <--
+O_DW Ack_Owner 0 <--
+O_DW Ack_Owner_All_Tokens 0 <--
+O_DW Tokens 0 <--
+O_DW Ack_All_Tokens 0 <--
+O_DW DMA_READ 0 <--
+O_DW DMA_WRITE 0 <--
+
+NO_DW GETX 0 <--
+NO_DW GETS 0 <--
+NO_DW Lockdown 0 <--
+NO_DW Own_Lock_or_Unlock 0 <--
+NO_DW Data_Owner 0 <--
+NO_DW Data_All_Tokens 0 <--
+NO_DW Tokens 0 <--
+NO_DW Request_Timeout 0 <--
+NO_DW DMA_READ 0 <--
+NO_DW DMA_WRITE 0 <--
+
+NO_DR GETX 0 <--
+NO_DR GETS 0 <--
+NO_DR Lockdown 0 <--
+NO_DR Own_Lock_or_Unlock 0 <--
+NO_DR Data_Owner 0 <--
+NO_DR Data_All_Tokens 0 <--
+NO_DR Tokens 0 <--
+NO_DR Request_Timeout 0 <--
+NO_DR DMA_READ 0 <--
+NO_DR DMA_WRITE 0 <--
+
+DW_L GETX 0 <--
+DW_L GETS 0 <--
+DW_L Lockdown 0 <--
+DW_L Unlockdown 0 <--
+DW_L Own_Lock_or_Unlock 0 <--
+DW_L Data_Owner 0 <--
+DW_L Data_All_Tokens 0 <--
+DW_L Ack_Owner 0 <--
+DW_L Ack_Owner_All_Tokens 0 <--
+DW_L Tokens 0 <--
+DW_L Request_Timeout 0 <--
+DW_L DMA_READ 0 <--
+DW_L DMA_WRITE 0 <--
+
+DR_L GETX 0 <--
+DR_L GETS 0 <--
+DR_L Lockdown 0 <--
+DR_L Unlockdown 0 <--
+DR_L Own_Lock_or_Unlock 0 <--
+DR_L Data_Owner 0 <--
+DR_L Data_All_Tokens 0 <--
+DR_L Ack_Owner 0 <--
+DR_L Ack_Owner_All_Tokens 0 <--
+DR_L Tokens 0 <--
+DR_L Request_Timeout 0 <--
+DR_L DMA_READ 0 <--
+DR_L DMA_WRITE 0 <--
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 15:54:34
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 15:55:45
+M5 executing on svvint04
+command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 236654 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 35577 # Simulator instruction rate (inst/s)
+host_mem_usage 215884 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
+host_tick_rate 1314701 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_insts 6404 # Number of instructions simulated
+sim_seconds 0.000237 # Number of seconds simulated
+sim_ticks 236654 # Number of ticks simulated
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1185 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 865 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 6415 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 236654 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=1
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
+buffer_size=0
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+memory_controller_latency=12
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: active, unordered
+virtual_net_4: active, ordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 11:55:11
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.39
+Virtual_time_in_minutes: 0.0065
+Virtual_time_in_hours: 0.000108333
+Virtual_time_in_days: 4.51389e-06
+
+Ruby_current_time: 215528
+Ruby_start_time: 0
+Ruby_cycles: 215528
+
+mbytes_resident: 33.1406
+mbytes_total: 33.1484
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 215529 [ 215529 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 2 max: 377 count: 8464 average: 24.4641 | standard deviation: 54.9689 | 0 7305 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 199 174 167 309 200 14 3 4 1 4 0 15 1 5 2 1 0 0 0 1 3 4 4 7 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 1 0 1 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 15 4 1 1 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 261 count: 6414 average: 16.7424 | standard deviation: 43.645 | 0 5833 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 113 72 159 92 10 2 2 1 2 0 0 0 1 0 0 0 0 0 1 3 1 4 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 333 count: 1185 average: 57.908 | standard deviation: 75.2483 | 0 765 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 52 60 116 72 4 1 0 0 1 0 12 1 2 2 1 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 377 count: 865 average: 35.904 | standard deviation: 74.7708 | 0 707 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 35 34 36 0 0 2 0 1 0 3 0 2 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 3 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 7120
+page_faults: 2128
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.107382
+ links_utilized_percent_switch_0_link_0: 0.0671258 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.147637 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.152706
+ links_utilized_percent_switch_1_link_0: 0.0369094 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.268503 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.20807
+ links_utilized_percent_switch_2_link_0: 0.268503 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.147637 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 581
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 581
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 581 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 581 average: 4 | standard deviation: 0 | 0 0 0 0 581 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 578
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 578
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 72.6644%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 27.3356%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 578 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 578 average: 7.5917 | standard deviation: 1.2123 | 0 0 0 0 59 0 0 0 519 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 1209
+Ifetch 6447
+Store 946
+L2_Replacement 1143
+L1_to_L2 1354
+L2_to_L1D 138
+L2_to_L1I 65
+Other_GETX 0
+Other_GETS 0
+Ack 0
+Shared_Ack 0
+Data 0
+Shared_Data 0
+Exclusive_Data 1159
+Writeback_Ack 1143
+Writeback_Nack 0
+All_acks 0
+All_acks_no_sharers 1159
+
+ - Transitions -
+I Load 420
+I Ifetch 581
+I Store 158
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 0 <--
+S Other_GETS 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 0 <--
+O Other_GETS 0 <--
+
+M Load 368
+M Ifetch 5833
+M Store 66
+M L2_Replacement 923
+M L1_to_L2 1061
+M L2_to_L1D 68
+M L2_to_L1I 65
+M Other_GETX 0 <--
+M Other_GETS 0 <--
+
+MM Load 397
+MM Ifetch 0 <--
+MM Store 641
+MM L2_Replacement 220
+MM L1_to_L2 293
+MM L2_to_L1D 70
+MM L2_to_L1I 0 <--
+MM Other_GETX 0 <--
+MM Other_GETS 0 <--
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 0 <--
+IM Other_GETS 0 <--
+IM Ack 0 <--
+IM Data 0 <--
+IM Exclusive_Data 158
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 0 <--
+SM Other_GETS 0 <--
+SM Ack 0 <--
+SM Data 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 0 <--
+OM Other_GETS 0 <--
+OM Ack 0 <--
+OM All_acks 0 <--
+OM All_acks_no_sharers 0 <--
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 0 <--
+ISM All_acks_no_sharers 0 <--
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 0 <--
+M_W All_acks_no_sharers 1001
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 0 <--
+MM_W All_acks_no_sharers 158
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 0 <--
+IS Other_GETS 0 <--
+IS Ack 0 <--
+IS Shared_Ack 0 <--
+IS Data 0 <--
+IS Shared_Data 0 <--
+IS Exclusive_Data 1001
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 0 <--
+SS Shared_Ack 0 <--
+SS All_acks 0 <--
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 24
+MI Ifetch 33
+MI Store 81
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 1143
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+ memory_total_requests: 1379
+ memory_reads: 1159
+ memory_writes: 220
+ memory_refreshes: 449
+ memory_total_request_delays: 342
+ memory_delays_per_request: 0.248006
+ memory_delays_in_input_queue: 1
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 341
+ memory_stalls_for_bank_busy: 167
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 19
+ memory_stalls_for_bus: 57
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 98
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 519
+GETS 1114
+PUT 1143
+Unblock 1159
+Writeback_Clean 0
+Writeback_Dirty 0
+Writeback_Exclusive_Clean 923
+Writeback_Exclusive_Dirty 220
+DMA_READ 0
+DMA_WRITE 0
+Memory_Data 1159
+Memory_Ack 220
+Ack 0
+Shared_Ack 0
+Shared_Data 0
+Exclusive_Data 0
+All_acks_and_data 0
+All_acks_and_data_no_sharers 0
+
+ - Transitions -
+NO GETX 0 <--
+NO GETS 0 <--
+NO PUT 1143
+NO DMA_READ 0 <--
+NO DMA_WRITE 0 <--
+
+O GETX 0 <--
+O GETS 0 <--
+O PUT 0 <--
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+
+E GETX 158
+E GETS 1001
+E PUT 0 <--
+E DMA_READ 0 <--
+E DMA_WRITE 0 <--
+
+NO_B GETX 0 <--
+NO_B GETS 0 <--
+NO_B PUT 0 <--
+NO_B Unblock 1159
+NO_B DMA_READ 0 <--
+NO_B DMA_WRITE 0 <--
+
+O_B GETX 0 <--
+O_B GETS 0 <--
+O_B PUT 0 <--
+O_B Unblock 0 <--
+O_B DMA_READ 0 <--
+O_B DMA_WRITE 0 <--
+
+NO_B_W GETX 0 <--
+NO_B_W GETS 0 <--
+NO_B_W PUT 0 <--
+NO_B_W Unblock 0 <--
+NO_B_W DMA_READ 0 <--
+NO_B_W DMA_WRITE 0 <--
+NO_B_W Memory_Data 1159
+
+O_B_W GETX 0 <--
+O_B_W GETS 0 <--
+O_B_W PUT 0 <--
+O_B_W Unblock 0 <--
+O_B_W DMA_READ 0 <--
+O_B_W DMA_WRITE 0 <--
+O_B_W Memory_Data 0 <--
+
+NO_W GETX 0 <--
+NO_W GETS 0 <--
+NO_W PUT 0 <--
+NO_W DMA_READ 0 <--
+NO_W DMA_WRITE 0 <--
+NO_W Memory_Data 0 <--
+
+O_W GETX 0 <--
+O_W GETS 0 <--
+O_W PUT 0 <--
+O_W DMA_READ 0 <--
+O_W DMA_WRITE 0 <--
+O_W Memory_Data 0 <--
+
+NO_DW_B_W GETX 0 <--
+NO_DW_B_W GETS 0 <--
+NO_DW_B_W PUT 0 <--
+NO_DW_B_W DMA_READ 0 <--
+NO_DW_B_W DMA_WRITE 0 <--
+NO_DW_B_W Ack 0 <--
+NO_DW_B_W Exclusive_Data 0 <--
+NO_DW_B_W All_acks_and_data_no_sharers 0 <--
+
+NO_DR_B_W GETX 0 <--
+NO_DR_B_W GETS 0 <--
+NO_DR_B_W PUT 0 <--
+NO_DR_B_W DMA_READ 0 <--
+NO_DR_B_W DMA_WRITE 0 <--
+NO_DR_B_W Memory_Data 0 <--
+NO_DR_B_W Ack 0 <--
+NO_DR_B_W Shared_Ack 0 <--
+NO_DR_B_W Shared_Data 0 <--
+NO_DR_B_W Exclusive_Data 0 <--
+
+NO_DR_B_D GETX 0 <--
+NO_DR_B_D GETS 0 <--
+NO_DR_B_D PUT 0 <--
+NO_DR_B_D DMA_READ 0 <--
+NO_DR_B_D DMA_WRITE 0 <--
+NO_DR_B_D Ack 0 <--
+NO_DR_B_D Shared_Ack 0 <--
+NO_DR_B_D Shared_Data 0 <--
+NO_DR_B_D Exclusive_Data 0 <--
+NO_DR_B_D All_acks_and_data 0 <--
+NO_DR_B_D All_acks_and_data_no_sharers 0 <--
+
+NO_DR_B GETX 0 <--
+NO_DR_B GETS 0 <--
+NO_DR_B PUT 0 <--
+NO_DR_B DMA_READ 0 <--
+NO_DR_B DMA_WRITE 0 <--
+NO_DR_B Ack 0 <--
+NO_DR_B Shared_Ack 0 <--
+NO_DR_B Shared_Data 0 <--
+NO_DR_B Exclusive_Data 0 <--
+NO_DR_B All_acks_and_data 0 <--
+NO_DR_B All_acks_and_data_no_sharers 0 <--
+
+NO_DW_W GETX 0 <--
+NO_DW_W GETS 0 <--
+NO_DW_W PUT 0 <--
+NO_DW_W DMA_READ 0 <--
+NO_DW_W DMA_WRITE 0 <--
+NO_DW_W Memory_Ack 0 <--
+
+O_DR_B_W GETX 0 <--
+O_DR_B_W GETS 0 <--
+O_DR_B_W PUT 0 <--
+O_DR_B_W DMA_READ 0 <--
+O_DR_B_W DMA_WRITE 0 <--
+O_DR_B_W Memory_Data 0 <--
+
+O_DR_B GETX 0 <--
+O_DR_B GETS 0 <--
+O_DR_B PUT 0 <--
+O_DR_B DMA_READ 0 <--
+O_DR_B DMA_WRITE 0 <--
+O_DR_B Ack 0 <--
+O_DR_B All_acks_and_data_no_sharers 0 <--
+
+WB GETX 27
+WB GETS 20
+WB PUT 0 <--
+WB Unblock 0 <--
+WB Writeback_Clean 0 <--
+WB Writeback_Dirty 0 <--
+WB Writeback_Exclusive_Clean 923
+WB Writeback_Exclusive_Dirty 220
+WB DMA_READ 0 <--
+WB DMA_WRITE 0 <--
+
+WB_O_W GETX 0 <--
+WB_O_W GETS 0 <--
+WB_O_W PUT 0 <--
+WB_O_W DMA_READ 0 <--
+WB_O_W DMA_WRITE 0 <--
+WB_O_W Memory_Ack 0 <--
+
+WB_E_W GETX 334
+WB_E_W GETS 93
+WB_E_W PUT 0 <--
+WB_E_W DMA_READ 0 <--
+WB_E_W DMA_WRITE 0 <--
+WB_E_W Memory_Ack 220
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 11:30:01
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 11:55:11
+M5 executing on svvint06
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 215528 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 45742 # Simulator instruction rate (inst/s)
+host_mem_usage 213100 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
+host_tick_rate 1539442 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_insts 6404 # Number of instructions simulated
+sim_seconds 0.000216 # Number of seconds simulated
+sim_ticks 215528 # Number of ticks simulated
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1185 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 865 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 6415 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 215528 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
[system]
type=System
-children=cpu membus physmem
-mem_mode=atomic
+children=cpu physmem ruby
+mem_mode=timing
physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dtb itb tracer workload
checker=Null
-clock=500
+clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
system=system
uid=100
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
+type=PhysicalMemory
file=
-latency=30000
+latency=30
latency_var=0
null=false
-num_cpus=1
-phase=0
range=0:134217727
-stats_file=ruby.stats
zero=false
-port=system.membus.port[0]
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
================ Begin RubySystem Configuration Print ================
RubySystem config:
- random_seed: 380268
+ random_seed: 1234
randomization: 0
- tech_nm: 45
- freq_mhz: 3000
+ cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
- memory_size_bytes: 1073741824
- memory_size_bits: 30
-DMA_Controller config: DMAController_0
- version: 0
- buffer_size: 32
- dma_sequencer: DMASequencer_0
- number_of_TBEs: 128
- transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
- version: 0
- buffer_size: 32
- directory_latency: 6
- directory_name: DirectoryMemory_0
- memory_controller_name: MemoryControl_0
- memory_latency: 158
- number_of_TBEs: 128
- recycle_latency: 10
- to_mem_ctrl_latency: 1
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
- version: 0
- buffer_size: 32
- cache: l1u_0
- cache_response_latency: 12
- issue_latency: 2
- number_of_TBEs: 128
- sequencer: Sequencer_0
- transitions_per_cycle: 32
-Cache config: l1u_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 2
- num_cache_sets: 4
- cache_set_size_bytes: 256
- cache_set_size_Kbytes: 0.25
- cache_set_size_Mbytes: 0.000244141
- cache_size_bytes: 2048
- cache_size_Kbytes: 2
- cache_size_Mbytes: 0.00195312
-DirectoryMemory Global Config:
- number of directory memories: 1
- total memory size bytes: 1073741824
- total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
- controller: DirectoryController_0
- version: 0
- memory_bits: 30
- memory_size_bytes: 1073741824
- memory_size_Kbytes: 1.04858e+06
- memory_size_Mbytes: 1024
- memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
- controller: L1CacheController_0
- version: 0
- max_outstanding_requests: 16
- deadlock_threshold: 500000
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: theTopology
+topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
- L1Cache-0 -> Directory-0 net_lat: 7
- L1Cache-0 -> DMA-0 net_lat: 7
-
-Directory-0 Network Latencies
- Directory-0 -> L1Cache-0 net_lat: 7
- Directory-0 -> DMA-0 net_lat: 7
-
-DMA-0 Network Latencies
- DMA-0 -> L1Cache-0 net_lat: 7
- DMA-0 -> Directory-0 net_lat: 7
-
---- End Topology Print ---
Profiler Configuration
----------------------
================ End RubySystem Configuration Print ================
-Real time: Jul/06/2009 11:11:08
+Real time: Jan/28/2010 10:15:29
Profiler Stats
--------------
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.84
-Virtual_time_in_minutes: 0.014
-Virtual_time_in_hours: 0.000233333
-Virtual_time_in_days: 0.000233333
+Virtual_time_in_seconds: 0.5
+Virtual_time_in_minutes: 0.00833333
+Virtual_time_in_hours: 0.000138889
+Virtual_time_in_days: 5.78704e-06
-Ruby_current_time: 25390001
-Ruby_start_time: 1
-Ruby_cycles: 25390000
+Ruby_current_time: 342698
+Ruby_start_time: 0
+Ruby_cycles: 342698
-mbytes_resident: 145.145
-mbytes_total: 1329.68
-resident_ratio: 0.109161
+mbytes_resident: 34.2148
+mbytes_total: 34.2227
+resident_ratio: 1
Total_misses: 0
total_misses: 0 [ 0 ]
user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
-instruction_executed: 1 [ 1 ]
-ruby_cycles_executed: 25390001 [ 25390001 ]
-cycles_per_instruction: 2.539e+07 [ 2.539e+07 ]
-misses_per_thousand_instructions: 0 [ 0 ]
+ruby_cycles_executed: 342699 [ 342699 ]
transactions_started: 0 [ 0 ]
transactions_ended: 0 [ 0 ]
-instructions_per_transaction: 0 [ 0 ]
cycles_per_transaction: 0 [ 0 ]
misses_per_transaction: 0 [ 0 ]
-L1D_cache cache stats:
- L1D_cache_total_misses: 0
- L1D_cache_total_demand_misses: 0
- L1D_cache_total_prefetches: 0
- L1D_cache_total_sw_prefetches: 0
- L1D_cache_total_hw_prefetches: 0
- L1D_cache_misses_per_transaction: 0
- L1D_cache_misses_per_instruction: 0
- L1D_cache_instructions_per_misses: NaN
-
- L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats:
- L1I_cache_total_misses: 0
- L1I_cache_total_demand_misses: 0
- L1I_cache_total_prefetches: 0
- L1I_cache_total_sw_prefetches: 0
- L1I_cache_total_hw_prefetches: 0
- L1I_cache_misses_per_transaction: 0
- L1I_cache_misses_per_instruction: 0
- L1I_cache_instructions_per_misses: NaN
-
- L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats:
- L2_cache_total_misses: 0
- L2_cache_total_demand_misses: 0
- L2_cache_total_prefetches: 0
- L2_cache_total_sw_prefetches: 0
- L2_cache_total_hw_prefetches: 0
- L2_cache_misses_per_transaction: 0
- L2_cache_misses_per_instruction: 0
- L2_cache_instructions_per_misses: NaN
-
- L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Memory control:
- memory_total_requests: 1554
- memory_reads: 793
- memory_writes: 761
- memory_refreshes: 14035
- memory_total_request_delays: 1878
- memory_delays_per_request: 1.20849
- memory_delays_in_input_queue: 761
- memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 1117
- memory_stalls_for_bank_busy: 223
- memory_stalls_for_random_busy: 0
- memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 62
- memory_stalls_for_bus: 804
- memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 28
- memory_stalls_for_read_read_turnaround: 0
- accesses_per_bank: 58 26 38 28 28 95 36 22 26 30 48 48 82 65 56 48 61 37 36 30 52 58 52 34 45 35 40 98 78 83 22 59
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
-DMA-0:0
+
Busy Bank Count:0
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 1 count: 1554 average: 0.489704 | standard deviation: 0.500483 | 793 761 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8464 average: 1 | standard deviation: 0 | 0 8464 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 279 count: 8464 average: 17.852 | standard deviation: 49.5344 | 0 7671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 15 0 0 0 0 687 0 0 0 0 16 0 0 0 0 24 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 1 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 12.6723 | standard deviation: 41.1839 | 0 6008 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 11 0 0 0 0 362 0 0 0 0 8 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 279 count: 1185 average: 42.865 | standard deviation: 73.1137 | 0 900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 0 0 0 1 0 0 0 0 241 0 0 0 0 7 0 0 0 0 12 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 279 count: 865 average: 21.9931 | standard deviation: 55.1781 | 0 763 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 3 0 0 0 0 84 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
Request vs. RubySystem State Profile
--------------------------------
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 1554 average: 0 | standard deviation: 0 | 1554 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1554 average: 0 | standard deviation: 0 | 1554 ]
+Total_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 793 average: 0 | standard deviation: 0 | 793 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 761 average: 0 | standard deviation: 0 | 761 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1730 average: 0 | standard deviation: 0 | 1730 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1726 average: 0 | standard deviation: 0 | 1726 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 37916
-page_faults: 0
+page_reclaims: 7357
+page_faults: 2195
swaps: 0
block_inputs: 0
-block_outputs: 48
+block_outputs: 0
Network Stats
-------------
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.000191266
- links_utilized_percent_switch_0_link_0: 7.65065e-05 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.000306026 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.157486
+ links_utilized_percent_switch_0_link_0: 0.0630876 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.251884 bw: 160000 base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 793 6344 [ 0 793 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Writeback_Control: 761 6088 [ 0 0 761 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Control: 793 6344 [ 793 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Data: 761 6088 [ 761 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.000191266
- links_utilized_percent_switch_1_link_0: 7.65065e-05 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.000306026 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.157661
+ links_utilized_percent_switch_1_link_0: 0.0629709 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.25235 bw: 160000 base_latency: 1
- outgoing_messages_switch_1_link_0_Control: 793 6344 [ 793 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Data: 761 6088 [ 761 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Data: 793 6344 [ 0 793 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 761 6088 [ 0 0 761 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_3_inlinks: 3
-switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0.000204017
- links_utilized_percent_switch_3_link_0: 0.000306026 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0.000306026 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_3_link_0_Response_Data: 793 6344 [ 0 793 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Writeback_Control: 761 6088 [ 0 0 761 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Control: 793 6344 [ 793 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Data: 761 6088 [ 761 0 0 0 0 0 ] base_latency: 1
-
- --- DMA ---
+links_utilized_percent_switch_2: 0.252117
+ links_utilized_percent_switch_2_link_0: 0.25235 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.251884 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1730
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1730
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 42.0231%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 15.7803%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 42.1965%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1730 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1730 average: 6.00925 | standard deviation: 2.00058 | 0 0 0 0 861 0 0 0 869 ]
+
+ --- L1Cache 0 ---
- Event Counts -
-ReadRequest 0
-WriteRequest 0
-Data 0
-Ack 0
+Load 1185
+Ifetch 6414
+Store 865
+Data 1730
+Fwd_GETX 0
+Inv 0
+Replacement 1726
+Writeback_Ack 1726
+Writeback_Nack 0
- Transitions -
-READY ReadRequest 0 <--
-READY WriteRequest 0 <--
+I Load 727
+I Ifetch 730
+I Store 273
+I Inv 0 <--
+I Replacement 0 <--
-BUSY_RD Data 0 <--
+II Writeback_Nack 0 <--
-BUSY_WR Ack 0 <--
+M Load 458
+M Ifetch 5684
+M Store 592
+M Fwd_GETX 0 <--
+M Inv 0 <--
+M Replacement 1726
+
+MI Fwd_GETX 0 <--
+MI Inv 0 <--
+MI Writeback_Ack 1726
+MI Writeback_Nack 0 <--
+
+MII Fwd_GETX 0 <--
+
+IS Data 1457
+
+IM Data 273
+
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+ memory_total_requests: 3456
+ memory_reads: 1730
+ memory_writes: 1726
+ memory_refreshes: 714
+ memory_total_request_delays: 5050
+ memory_delays_per_request: 1.46123
+ memory_delays_in_input_queue: 1722
+ memory_delays_behind_head_of_bank_queue: 8
+ memory_delays_stalled_at_head_of_bank_queue: 3320
+ memory_stalls_for_bank_busy: 1509
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 99
+ memory_stalls_for_bus: 1677
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 35
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98
- --- Directory ---
+ --- Directory 0 ---
- Event Counts -
-GETX 793
+GETX 1730
GETS 0
-PUTX 761
+PUTX 1726
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
-Memory_Data 793
-Memory_Ack 761
+Memory_Data 1730
+Memory_Ack 1726
- Transitions -
-I GETX 793
+I GETX 1730
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
M GETX 0 <--
-M PUTX 761
+M PUTX 1726
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
+M_DWRI GETX 0 <--
M_DWRI Memory_Ack 0 <--
+M_DRDI GETX 0 <--
+M_DRDI Memory_Ack 0 <--
+
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
-IM Memory_Data 793
+IM Memory_Data 1730
MI GETX 0 <--
MI GETS 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
-MI Memory_Ack 761
+MI Memory_Ack 1726
ID GETX 0 <--
ID GETS 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
- --- L1Cache ---
- - Event Counts -
-Load 1185
-Ifetch 6414
-Store 865
-Data 793
-Fwd_GETX 0
-Inv 0
-Replacement 761
-Writeback_Ack 761
-Writeback_Nack 0
-
- - Transitions -
-I Load 285
-I Ifetch 406
-I Store 102
-I Inv 0 <--
-I Replacement 0 <--
-
-II Writeback_Nack 0 <--
-
-M Load 900
-M Ifetch 6008
-M Store 763
-M Fwd_GETX 0 <--
-M Inv 0 <--
-M Replacement 761
-
-MI Fwd_GETX 0 <--
-MI Inv 0 <--
-MI Writeback_Ack 761
-
-IS Data 691
-
-IM Data 102
-
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
-print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:07
-M5 executing on maize
+M5 compiled Jan 27 2010 22:23:20
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 10:15:28
+M5 executing on svvint07
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
-Global frequency set at 1000000000000 ticks per second
- Debug: Adding to filter: 'q' (Queue)
+Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 25390000 because target called exit()
+Exiting @ tick 342698 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 8064 # Simulator instruction rate (inst/s)
-host_mem_usage 1361592 # Number of bytes of host memory used
-host_seconds 0.79 # Real time elapsed on the host
-host_tick_rate 31966299 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 19405 # Simulator instruction rate (inst/s)
+host_mem_usage 215700 # Number of bytes of host memory used
+host_seconds 0.33 # Real time elapsed on the host
+host_tick_rate 1038428 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
-sim_seconds 0.000025 # Number of seconds simulated
-sim_ticks 25390000 # Number of ticks simulated
+sim_seconds 0.000343 # Number of seconds simulated
+sim_ticks 342698 # Number of ticks simulated
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 50780 # number of cpu cycles simulated
+system.cpu.numCycles 342698 # number of cpu cycles simulated
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+++ /dev/null
-[root]
-type=Root
-children=system
-dummy=0
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
-file=
-latency=30000
-latency_var=0
-null=false
-num_cpus=1
-phase=0
-range=0:134217727
-stats_file=ruby.stats
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-
-================ Begin RubySystem Configuration Print ================
-
-RubySystem config:
- random_seed: 613394
- randomization: 0
- tech_nm: 45
- freq_mhz: 3000
- block_size_bytes: 64
- block_size_bits: 6
- memory_size_bytes: 1073741824
- memory_size_bits: 30
-DMA_Controller config: DMAController_0
- version: 0
- buffer_size: 32
- dma_sequencer: DMASequencer_0
- number_of_TBEs: 128
- transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
- version: 0
- buffer_size: 32
- directory_latency: 6
- directory_name: DirectoryMemory_0
- memory_controller_name: MemoryControl_0
- memory_latency: 158
- number_of_TBEs: 128
- recycle_latency: 10
- to_mem_ctrl_latency: 1
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
- version: 0
- buffer_size: 32
- cache: l1u_0
- cache_response_latency: 12
- issue_latency: 2
- number_of_TBEs: 128
- sequencer: Sequencer_0
- transitions_per_cycle: 32
-Cache config: l1u_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 2
- num_cache_sets: 4
- cache_set_size_bytes: 256
- cache_set_size_Kbytes: 0.25
- cache_set_size_Mbytes: 0.000244141
- cache_size_bytes: 2048
- cache_size_Kbytes: 2
- cache_size_Mbytes: 0.00195312
-DirectoryMemory Global Config:
- number of directory memories: 1
- total memory size bytes: 1073741824
- total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
- controller: DirectoryController_0
- version: 0
- memory_bits: 30
- memory_size_bytes: 1073741824
- memory_size_Kbytes: 1.04858e+06
- memory_size_Mbytes: 1024
- memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
- controller: L1CacheController_0
- version: 0
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-
-Network Configuration
----------------------
-network: SIMPLE_NETWORK
-topology: theTopology
-
-virtual_net_0: active, ordered
-virtual_net_1: active, ordered
-virtual_net_2: active, ordered
-virtual_net_3: inactive
-virtual_net_4: active, ordered
-virtual_net_5: active, ordered
-
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
- L1Cache-0 -> Directory-0 net_lat: 7
- L1Cache-0 -> DMA-0 net_lat: 7
-
-Directory-0 Network Latencies
- Directory-0 -> L1Cache-0 net_lat: 7
- Directory-0 -> DMA-0 net_lat: 7
-
-DMA-0 Network Latencies
- DMA-0 -> L1Cache-0 net_lat: 7
- DMA-0 -> Directory-0 net_lat: 7
-
---- End Topology Print ---
-
-Profiler Configuration
-----------------------
-periodic_stats_period: 1000000
-
-================ End RubySystem Configuration Print ================
-
-
-Real time: Jul/06/2009 11:11:05
-
-Profiler Stats
---------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
-
-Virtual_time_in_seconds: 0.21
-Virtual_time_in_minutes: 0.0035
-Virtual_time_in_hours: 5.83333e-05
-Virtual_time_in_days: 5.83333e-05
-
-Ruby_current_time: 1297501
-Ruby_start_time: 1
-Ruby_cycles: 1297500
-
-mbytes_resident: 143.516
-mbytes_total: 1328.64
-resident_ratio: 0.10802
-
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-instruction_executed: 1 [ 1 ]
-ruby_cycles_executed: 1297501 [ 1297501 ]
-cycles_per_instruction: 1.2975e+06 [ 1.2975e+06 ]
-misses_per_thousand_instructions: 0 [ 0 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-instructions_per_transaction: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
-L1D_cache cache stats:
- L1D_cache_total_misses: 0
- L1D_cache_total_demand_misses: 0
- L1D_cache_total_prefetches: 0
- L1D_cache_total_sw_prefetches: 0
- L1D_cache_total_hw_prefetches: 0
- L1D_cache_misses_per_transaction: 0
- L1D_cache_misses_per_instruction: 0
- L1D_cache_instructions_per_misses: NaN
-
- L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats:
- L1I_cache_total_misses: 0
- L1I_cache_total_demand_misses: 0
- L1I_cache_total_prefetches: 0
- L1I_cache_total_sw_prefetches: 0
- L1I_cache_total_hw_prefetches: 0
- L1I_cache_misses_per_transaction: 0
- L1I_cache_misses_per_instruction: 0
- L1I_cache_instructions_per_misses: NaN
-
- L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats:
- L2_cache_total_misses: 0
- L2_cache_total_demand_misses: 0
- L2_cache_total_prefetches: 0
- L2_cache_total_sw_prefetches: 0
- L2_cache_total_hw_prefetches: 0
- L2_cache_misses_per_transaction: 0
- L2_cache_misses_per_instruction: 0
- L2_cache_instructions_per_misses: NaN
-
- L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Busy Controller Counts:
-L1Cache-0:0
-Directory-0:0
-DMA-0:0
-
-Busy Bank Count:0
-
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle SW Prefetch Requests
-------------------------------------
-prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Resource Usage
---------------
-page_size: 4096
-user_time: 0
-system_time: 0
-page_reclaims: 37503
-page_faults: 0
-swaps: 0
-block_inputs: 24
-block_outputs: 48
-
-Network Stats
--------------
-
-switch_0_inlinks: 2
-switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0
- links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_1_inlinks: 2
-switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0
- links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_2_inlinks: 2
-switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_3_inlinks: 3
-switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0
- links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
-
-
- --- DMA ---
- - Event Counts -
-ReadRequest 0
-WriteRequest 0
-Data 0
-Ack 0
-
- - Transitions -
-READY ReadRequest 0 <--
-READY WriteRequest 0 <--
-
-BUSY_RD Data 0 <--
-
-BUSY_WR Ack 0 <--
-
- --- Directory ---
- - Event Counts -
-GETX 0
-GETS 0
-PUTX 0
-PUTX_NotOwner 0
-DMA_READ 0
-DMA_WRITE 0
-Memory_Data 0
-Memory_Ack 0
-
- - Transitions -
-I GETX 0 <--
-I PUTX_NotOwner 0 <--
-I DMA_READ 0 <--
-I DMA_WRITE 0 <--
-
-M GETX 0 <--
-M PUTX 0 <--
-M PUTX_NotOwner 0 <--
-M DMA_READ 0 <--
-M DMA_WRITE 0 <--
-
-M_DRD GETX 0 <--
-M_DRD PUTX 0 <--
-
-M_DWR GETX 0 <--
-M_DWR PUTX 0 <--
-
-M_DWRI Memory_Ack 0 <--
-
-IM GETX 0 <--
-IM GETS 0 <--
-IM PUTX 0 <--
-IM PUTX_NotOwner 0 <--
-IM DMA_READ 0 <--
-IM DMA_WRITE 0 <--
-IM Memory_Data 0 <--
-
-MI GETX 0 <--
-MI GETS 0 <--
-MI PUTX 0 <--
-MI PUTX_NotOwner 0 <--
-MI DMA_READ 0 <--
-MI DMA_WRITE 0 <--
-MI Memory_Ack 0 <--
-
-ID GETX 0 <--
-ID GETS 0 <--
-ID PUTX 0 <--
-ID PUTX_NotOwner 0 <--
-ID DMA_READ 0 <--
-ID DMA_WRITE 0 <--
-ID Memory_Data 0 <--
-
-ID_W GETX 0 <--
-ID_W GETS 0 <--
-ID_W PUTX 0 <--
-ID_W PUTX_NotOwner 0 <--
-ID_W DMA_READ 0 <--
-ID_W DMA_WRITE 0 <--
-ID_W Memory_Ack 0 <--
-
- --- L1Cache ---
- - Event Counts -
-Load 0
-Ifetch 0
-Store 0
-Data 0
-Fwd_GETX 0
-Inv 0
-Replacement 0
-Writeback_Ack 0
-Writeback_Nack 0
-
- - Transitions -
-I Load 0 <--
-I Ifetch 0 <--
-I Store 0 <--
-I Inv 0 <--
-I Replacement 0 <--
-
-II Writeback_Nack 0 <--
-
-M Load 0 <--
-M Ifetch 0 <--
-M Store 0 <--
-M Fwd_GETX 0 <--
-M Inv 0 <--
-M Replacement 0 <--
-
-MI Fwd_GETX 0 <--
-MI Inv 0 <--
-MI Writeback_Ack 0 <--
-
-IS Data 0 <--
-
-IM Data 0 <--
-
+++ /dev/null
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
-print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
-hack: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:05
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby
-Global frequency set at 1000000000000 ticks per second
- Debug: Adding to filter: 'q' (Queue)
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 1297500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 10832 # Simulator instruction rate (inst/s)
-host_mem_usage 1360528 # Number of bytes of host memory used
-host_seconds 0.24 # Real time elapsed on the host
-host_tick_rate 5450330 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2577 # Number of instructions simulated
-sim_seconds 0.000001 # Number of seconds simulated
-sim_ticks 1297500 # Number of ticks simulated
-system.cpu.dtb.data_accesses 717 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 709 # DTB hits
-system.cpu.dtb.data_misses 8 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 415 # DTB read hits
-system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 294 # DTB write hits
-system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 2596 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 2585 # ITB hits
-system.cpu.itb.fetch_misses 11 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2596 # number of cpu cycles simulated
-system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_refs 717 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=1
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+num_int_nodes=4
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+buffer_size=0
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+recycle_latency=10
+to_l1_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links2.ext_node.directory
+directory_latency=6
+memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+to_mem_ctrl_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=3
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 13:57:45
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.45
+Virtual_time_in_minutes: 0.0075
+Virtual_time_in_hours: 0.000125
+Virtual_time_in_days: 5.20833e-06
+
+Ruby_current_time: 103637
+Ruby_start_time: 0
+Ruby_cycles: 103637
+
+mbytes_resident: 33.0938
+mbytes_total: 33.1016
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 103638 [ 103638 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
+miss_latency_2: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 20 count: 3612 average: 0.0221484 | standard deviation: 0.622437 | 3607 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 3 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2644 average: 0 | standard deviation: 0 | 2644 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 968 average: 0.0826446 | standard deviation: 1.20065 | 963 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 3 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 2213 average: 0 | standard deviation: 0 | 2213 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 7156
+page_faults: 2112
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.0891754
+ links_utilized_percent_switch_0_link_0: 0.0687858 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.109565 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 124 992 [ 0 124 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Control: 641 5128 [ 0 369 272 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.230281
+ links_utilized_percent_switch_1_link_0: 0.0932703 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.367292 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Control: 1180 9440 [ 0 908 272 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 675 48600 [ 0 675 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 560 4480 [ 0 560 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.143277
+ links_utilized_percent_switch_2_link_0: 0.0230371 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.263516 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Control: 539 4312 [ 0 539 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 3
+switch_3_outlinks: 3
+links_utilized_percent_switch_3: 0.246791
+ links_utilized_percent_switch_3_link_0: 0.275143 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.373081 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.0921486 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 124 992 [ 0 124 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Control: 1180 9440 [ 0 908 272 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 415
+Ifetch 2585
+Store 294
+Inv 431
+L1_Replacement 502
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_GET_INSTR 0
+Data 0
+Data_Exclusive 204
+DataS_fromL1 0
+Data_all_Acks 368
+Ack 0
+Ack_all 0
+WB_Ack 124
+
+ - Transitions -
+NP Load 182
+NP Ifetch 270
+NP Store 58
+NP Inv 162
+NP L1_Replacement 0 <--
+
+I Load 22
+I Ifetch 30
+I Store 10
+I Inv 0 <--
+I L1_Replacement 206
+
+S Load 0 <--
+S Ifetch 2285
+S Store 0 <--
+S Inv 124
+S L1_Replacement 172
+
+E Load 140
+E Ifetch 0 <--
+E Store 41
+E Inv 83
+E L1_Replacement 79
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 71
+M Ifetch 0 <--
+M Store 185
+M Inv 62
+M L1_Replacement 45
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 0 <--
+IS L1_Replacement 0 <--
+IS Data_Exclusive 204
+IS DataS_fromL1 0 <--
+IS Data_all_Acks 300
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 0 <--
+IM Data_all_Acks 68
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 0 <--
+SM L1_Replacement 0 <--
+SM Ack 0 <--
+SM Ack_all 0 <--
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 0 <--
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 124
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GET_INSTR 300
+L1_GETS 209
+L1_GETX 71
+L1_UPGRADE 0
+L1_PUTX 124
+L1_PUTX_old 0
+Fwd_L1_GETX 0
+Fwd_L1_GETS 0
+Fwd_L1_GET_INSTR 0
+L2_Replacement 43
+L2_Replacement_clean 496
+Mem_Data 547
+Mem_Ack 539
+WB_Data 62
+WB_Data_clean 0
+Ack 0
+Ack_all 369
+Unblock 0
+Unblock_Cancel 0
+Exclusive_Unblock 272
+MEM_Inv 0
+
+ - Transitions -
+NP L1_GET_INSTR 291
+NP L1_GETS 192
+NP L1_GETX 64
+NP L1_PUTX 0 <--
+NP L1_PUTX_old 0 <--
+
+SS L1_GET_INSTR 9
+SS L1_GETS 0 <--
+SS L1_GETX 0 <--
+SS L1_UPGRADE 0 <--
+SS L1_PUTX 0 <--
+SS L1_PUTX_old 0 <--
+SS L2_Replacement 0 <--
+SS L2_Replacement_clean 286
+SS MEM_Inv 0 <--
+
+M L1_GET_INSTR 0 <--
+M L1_GETS 12
+M L1_GETX 4
+M L1_PUTX 0 <--
+M L1_PUTX_old 0 <--
+M L2_Replacement 39
+M L2_Replacement_clean 69
+M MEM_Inv 0 <--
+
+MT L1_GET_INSTR 0 <--
+MT L1_GETS 0 <--
+MT L1_GETX 0 <--
+MT L1_PUTX 124
+MT L1_PUTX_old 0 <--
+MT L2_Replacement 4
+MT L2_Replacement_clean 141
+MT MEM_Inv 0 <--
+
+M_I L1_GET_INSTR 0 <--
+M_I L1_GETS 5
+M_I L1_GETX 3
+M_I L1_UPGRADE 0 <--
+M_I L1_PUTX 0 <--
+M_I L1_PUTX_old 0 <--
+M_I Mem_Ack 539
+M_I MEM_Inv 0 <--
+
+MT_I L1_GET_INSTR 0 <--
+MT_I L1_GETS 0 <--
+MT_I L1_GETX 0 <--
+MT_I L1_UPGRADE 0 <--
+MT_I L1_PUTX 0 <--
+MT_I L1_PUTX_old 0 <--
+MT_I WB_Data 2
+MT_I WB_Data_clean 0 <--
+MT_I Ack_all 2
+MT_I MEM_Inv 0 <--
+
+MCT_I L1_GET_INSTR 0 <--
+MCT_I L1_GETS 0 <--
+MCT_I L1_GETX 0 <--
+MCT_I L1_UPGRADE 0 <--
+MCT_I L1_PUTX 0 <--
+MCT_I L1_PUTX_old 0 <--
+MCT_I WB_Data 60
+MCT_I WB_Data_clean 0 <--
+MCT_I Ack_all 81
+
+I_I L1_GET_INSTR 0 <--
+I_I L1_GETS 0 <--
+I_I L1_GETX 0 <--
+I_I L1_UPGRADE 0 <--
+I_I L1_PUTX 0 <--
+I_I L1_PUTX_old 0 <--
+I_I Ack 0 <--
+I_I Ack_all 286
+
+S_I L1_GET_INSTR 0 <--
+S_I L1_GETS 0 <--
+S_I L1_GETX 0 <--
+S_I L1_UPGRADE 0 <--
+S_I L1_PUTX 0 <--
+S_I L1_PUTX_old 0 <--
+S_I Ack 0 <--
+S_I Ack_all 0 <--
+S_I MEM_Inv 0 <--
+
+ISS L1_GET_INSTR 0 <--
+ISS L1_GETS 0 <--
+ISS L1_GETX 0 <--
+ISS L1_PUTX 0 <--
+ISS L1_PUTX_old 0 <--
+ISS L2_Replacement 0 <--
+ISS L2_Replacement_clean 0 <--
+ISS Mem_Data 192
+ISS MEM_Inv 0 <--
+
+IS L1_GET_INSTR 0 <--
+IS L1_GETS 0 <--
+IS L1_GETX 0 <--
+IS L1_PUTX 0 <--
+IS L1_PUTX_old 0 <--
+IS L2_Replacement 0 <--
+IS L2_Replacement_clean 0 <--
+IS Mem_Data 291
+IS MEM_Inv 0 <--
+
+IM L1_GET_INSTR 0 <--
+IM L1_GETS 0 <--
+IM L1_GETX 0 <--
+IM L1_PUTX 0 <--
+IM L1_PUTX_old 0 <--
+IM L2_Replacement 0 <--
+IM L2_Replacement_clean 0 <--
+IM Mem_Data 64
+IM MEM_Inv 0 <--
+
+SS_MB L1_GET_INSTR 0 <--
+SS_MB L1_GETS 0 <--
+SS_MB L1_GETX 0 <--
+SS_MB L1_UPGRADE 0 <--
+SS_MB L1_PUTX 0 <--
+SS_MB L1_PUTX_old 0 <--
+SS_MB L2_Replacement 0 <--
+SS_MB L2_Replacement_clean 0 <--
+SS_MB Unblock_Cancel 0 <--
+SS_MB Exclusive_Unblock 0 <--
+SS_MB MEM_Inv 0 <--
+
+MT_MB L1_GET_INSTR 0 <--
+MT_MB L1_GETS 0 <--
+MT_MB L1_GETX 0 <--
+MT_MB L1_UPGRADE 0 <--
+MT_MB L1_PUTX 0 <--
+MT_MB L1_PUTX_old 0 <--
+MT_MB L2_Replacement 0 <--
+MT_MB L2_Replacement_clean 0 <--
+MT_MB Unblock_Cancel 0 <--
+MT_MB Exclusive_Unblock 272
+MT_MB MEM_Inv 0 <--
+
+M_MB L1_GET_INSTR 0 <--
+M_MB L1_GETS 0 <--
+M_MB L1_GETX 0 <--
+M_MB L1_UPGRADE 0 <--
+M_MB L1_PUTX 0 <--
+M_MB L1_PUTX_old 0 <--
+M_MB L2_Replacement 0 <--
+M_MB L2_Replacement_clean 0 <--
+M_MB Exclusive_Unblock 0 <--
+M_MB MEM_Inv 0 <--
+
+MT_IIB L1_GET_INSTR 0 <--
+MT_IIB L1_GETS 0 <--
+MT_IIB L1_GETX 0 <--
+MT_IIB L1_UPGRADE 0 <--
+MT_IIB L1_PUTX 0 <--
+MT_IIB L1_PUTX_old 0 <--
+MT_IIB L2_Replacement 0 <--
+MT_IIB L2_Replacement_clean 0 <--
+MT_IIB WB_Data 0 <--
+MT_IIB WB_Data_clean 0 <--
+MT_IIB Unblock 0 <--
+MT_IIB MEM_Inv 0 <--
+
+MT_IB L1_GET_INSTR 0 <--
+MT_IB L1_GETS 0 <--
+MT_IB L1_GETX 0 <--
+MT_IB L1_UPGRADE 0 <--
+MT_IB L1_PUTX 0 <--
+MT_IB L1_PUTX_old 0 <--
+MT_IB L2_Replacement 0 <--
+MT_IB L2_Replacement_clean 0 <--
+MT_IB WB_Data 0 <--
+MT_IB WB_Data_clean 0 <--
+MT_IB Unblock_Cancel 0 <--
+MT_IB MEM_Inv 0 <--
+
+MT_SB L1_GET_INSTR 0 <--
+MT_SB L1_GETS 0 <--
+MT_SB L1_GETX 0 <--
+MT_SB L1_UPGRADE 0 <--
+MT_SB L1_PUTX 0 <--
+MT_SB L1_PUTX_old 0 <--
+MT_SB L2_Replacement 0 <--
+MT_SB L2_Replacement_clean 0 <--
+MT_SB Unblock 0 <--
+MT_SB MEM_Inv 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+ memory_total_requests: 650
+ memory_reads: 547
+ memory_writes: 103
+ memory_refreshes: 216
+ memory_total_request_delays: 375
+ memory_delays_per_request: 0.576923
+ memory_delays_in_input_queue: 39
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 336
+ memory_stalls_for_bank_busy: 44
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 6
+ memory_stalls_for_bus: 91
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 195
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92
+
+ --- Directory 0 ---
+ - Event Counts -
+Fetch 547
+Data 103
+Memory_Data 547
+Memory_Ack 103
+DMA_READ 0
+DMA_WRITE 0
+CleanReplacement 436
+
+ - Transitions -
+I Fetch 547
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+ID Fetch 0 <--
+ID Data 0 <--
+ID Memory_Data 0 <--
+ID DMA_READ 0 <--
+ID DMA_WRITE 0 <--
+
+ID_W Fetch 0 <--
+ID_W Data 0 <--
+ID_W Memory_Ack 0 <--
+ID_W DMA_READ 0 <--
+ID_W DMA_WRITE 0 <--
+
+M Data 103
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+M CleanReplacement 436
+
+IM Fetch 0 <--
+IM Data 0 <--
+IM Memory_Data 547
+IM DMA_READ 0 <--
+IM DMA_WRITE 0 <--
+
+MI Fetch 0 <--
+MI Data 0 <--
+MI Memory_Ack 103
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+
+M_DRD Data 0 <--
+M_DRD DMA_READ 0 <--
+M_DRD DMA_WRITE 0 <--
+
+M_DRDI Fetch 0 <--
+M_DRDI Data 0 <--
+M_DRDI Memory_Ack 0 <--
+M_DRDI DMA_READ 0 <--
+M_DRDI DMA_WRITE 0 <--
+
+M_DWR Data 0 <--
+M_DWR DMA_READ 0 <--
+M_DWR DMA_WRITE 0 <--
+
+M_DWRI Fetch 0 <--
+M_DWRI Data 0 <--
+M_DWRI Memory_Ack 0 <--
+M_DWRI DMA_READ 0 <--
+M_DWRI DMA_WRITE 0 <--
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 13:54:58
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 13:57:44
+M5 executing on svvint03
+command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 103637 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 21475 # Simulator instruction rate (inst/s)
+host_mem_usage 214848 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
+host_tick_rate 863649 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_insts 2577 # Number of instructions simulated
+sim_seconds 0.000104 # Number of seconds simulated
+sim_ticks 103637 # Number of ticks simulated
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 419 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 415 # DTB read hits
+system.cpu.dtb.read_misses 4 # DTB read misses
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 294 # DTB write hits
+system.cpu.dtb.write_misses 4 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 2586 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 103637 # number of cpu cycles simulated
+system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.num_refs 717 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=1
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+num_int_nodes=4
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+buffer_size=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+response_latency=2
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links2.ext_node.directory
+directory_latency=6
+memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=3
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 15:08:15
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.51
+Virtual_time_in_minutes: 0.0085
+Virtual_time_in_hours: 0.000141667
+Virtual_time_in_days: 5.90278e-06
+
+Ruby_current_time: 85988
+Ruby_start_time: 0
+Ruby_cycles: 85988
+
+mbytes_resident: 33.25
+mbytes_total: 33.2578
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 85989 [ 85989 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L2Cache-0:0
+L1Cache-0:0
+
+Directory-0:0
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 7143
+page_faults: 2153
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.212617
+ links_utilized_percent_switch_0_link_0: 0.074022 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.351212 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 427 30744 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 83 5976 [ 0 0 83 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 502 4016 [ 502 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 502 36144 [ 0 0 502 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 502 4016 [ 502 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 510 4080 [ 0 0 510 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.289503
+ links_utilized_percent_switch_1_link_0: 0.149643 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.429362 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 427 30744 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 502 36144 [ 0 0 502 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 913 7304 [ 502 411 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Unblock_Control: 510 4080 [ 0 0 510 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 427 3416 [ 0 427 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 427 30744 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 83 5976 [ 0 0 83 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 77 5544 [ 0 0 77 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 1247 9976 [ 502 411 334 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.140332
+ links_utilized_percent_switch_2_link_0: 0.0333041 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.24736 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Request_Control: 427 3416 [ 0 427 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 77 5544 [ 0 0 77 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Unblock_Control: 426 3408 [ 0 0 426 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 427 30744 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Control: 411 3288 [ 0 411 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 3
+switch_3_outlinks: 3
+links_utilized_percent_switch_3: 0.342645
+ links_utilized_percent_switch_3_link_0: 0.296088 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.598572 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.133274 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Response_Data: 427 30744 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 83 5976 [ 0 0 83 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Writeback_Control: 502 4016 [ 502 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 427 30744 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 502 36144 [ 0 0 502 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Control: 913 7304 [ 502 411 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Unblock_Control: 510 4080 [ 0 0 510 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Request_Control: 427 3416 [ 0 427 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Data: 77 5544 [ 0 0 77 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 415
+Ifetch 2585
+Store 294
+L1_Replacement 506
+Own_GETX 0
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_DMA 0
+Inv 0
+Ack 0
+Data 0
+Exclusive_Data 510
+Writeback_Ack 0
+Writeback_Ack_Data 502
+Writeback_Nack 0
+All_acks 58
+Use_Timeout 509
+
+ - Transitions -
+I Load 182
+I Ifetch 270
+I Store 58
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_Replacement 0 <--
+O Fwd_GETX 0 <--
+O Fwd_GETS 0 <--
+O Fwd_DMA 0 <--
+
+M Load 82
+M Ifetch 1224
+M Store 33
+M L1_Replacement 406
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_DMA 0 <--
+
+M_W Load 49
+M_W Ifetch 1091
+M_W Store 7
+M_W L1_Replacement 4
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 0 <--
+M_W Fwd_GETS 0 <--
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 444
+
+MM Load 99
+MM Ifetch 0 <--
+MM Store 114
+MM L1_Replacement 96
+MM Fwd_GETX 0 <--
+MM Fwd_GETS 0 <--
+MM Fwd_DMA 0 <--
+
+MM_W Load 3
+MM_W Ifetch 0 <--
+MM_W Store 82
+MM_W L1_Replacement 0 <--
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 0 <--
+MM_W Fwd_GETS 0 <--
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 65
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 0 <--
+IM Data 0 <--
+IM Exclusive_Data 58
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 0 <--
+SM Ack 0 <--
+SM Data 0 <--
+SM Exclusive_Data 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 0 <--
+OM Fwd_GETX 0 <--
+OM Fwd_GETS 0 <--
+OM Fwd_DMA 0 <--
+OM Ack 0 <--
+OM All_acks 58
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 0 <--
+IS Exclusive_Data 452
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 502
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GETS 455
+L1_GETX 58
+L1_PUTO 0
+L1_PUTX 502
+L1_PUTS_only 0
+L1_PUTS 0
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_DMA 0
+Own_GETX 0
+Inv 0
+IntAck 0
+ExtAck 0
+All_Acks 44
+Data 44
+Data_Exclusive 383
+L1_WBCLEANDATA 396
+L1_WBDIRTYDATA 106
+Writeback_Ack 411
+Writeback_Nack 0
+Unblock 0
+Exclusive_Unblock 510
+L2_Replacement 411
+
+ - Transitions -
+NP L1_GETS 383
+NP L1_GETX 44
+NP L1_PUTO 0 <--
+NP L1_PUTX 0 <--
+NP L1_PUTS 0 <--
+NP Inv 0 <--
+
+I L1_GETS 0 <--
+I L1_GETX 0 <--
+I L1_PUTO 0 <--
+I L1_PUTX 0 <--
+I L1_PUTS 0 <--
+I Inv 0 <--
+I L2_Replacement 0 <--
+
+ILS L1_GETS 0 <--
+ILS L1_GETX 0 <--
+ILS L1_PUTO 0 <--
+ILS L1_PUTX 0 <--
+ILS L1_PUTS_only 0 <--
+ILS L1_PUTS 0 <--
+ILS Inv 0 <--
+ILS L2_Replacement 0 <--
+
+ILX L1_GETS 0 <--
+ILX L1_GETX 0 <--
+ILX L1_PUTO 0 <--
+ILX L1_PUTX 502
+ILX L1_PUTS_only 0 <--
+ILX L1_PUTS 0 <--
+ILX Fwd_GETX 0 <--
+ILX Fwd_GETS 0 <--
+ILX Fwd_DMA 0 <--
+ILX Inv 0 <--
+ILX Data 0 <--
+ILX L2_Replacement 0 <--
+
+ILO L1_GETS 0 <--
+ILO L1_GETX 0 <--
+ILO L1_PUTO 0 <--
+ILO L1_PUTX 0 <--
+ILO L1_PUTS 0 <--
+ILO Fwd_GETX 0 <--
+ILO Fwd_GETS 0 <--
+ILO Fwd_DMA 0 <--
+ILO Inv 0 <--
+ILO Data 0 <--
+ILO L2_Replacement 0 <--
+
+ILOX L1_GETS 0 <--
+ILOX L1_GETX 0 <--
+ILOX L1_PUTO 0 <--
+ILOX L1_PUTX 0 <--
+ILOX L1_PUTS 0 <--
+ILOX Fwd_GETX 0 <--
+ILOX Fwd_GETS 0 <--
+ILOX Fwd_DMA 0 <--
+ILOX Data 0 <--
+
+ILOS L1_GETS 0 <--
+ILOS L1_GETX 0 <--
+ILOS L1_PUTO 0 <--
+ILOS L1_PUTX 0 <--
+ILOS L1_PUTS_only 0 <--
+ILOS L1_PUTS 0 <--
+ILOS Fwd_GETX 0 <--
+ILOS Fwd_GETS 0 <--
+ILOS Fwd_DMA 0 <--
+ILOS Data 0 <--
+ILOS L2_Replacement 0 <--
+
+ILOSX L1_GETS 0 <--
+ILOSX L1_GETX 0 <--
+ILOSX L1_PUTO 0 <--
+ILOSX L1_PUTX 0 <--
+ILOSX L1_PUTS_only 0 <--
+ILOSX L1_PUTS 0 <--
+ILOSX Fwd_GETX 0 <--
+ILOSX Fwd_GETS 0 <--
+ILOSX Fwd_DMA 0 <--
+ILOSX Data 0 <--
+
+S L1_GETS 0 <--
+S L1_GETX 0 <--
+S L1_PUTX 0 <--
+S L1_PUTS 0 <--
+S Inv 0 <--
+S L2_Replacement 0 <--
+
+O L1_GETS 0 <--
+O L1_GETX 0 <--
+O L1_PUTX 0 <--
+O Fwd_GETX 0 <--
+O Fwd_GETS 0 <--
+O Fwd_DMA 0 <--
+O L2_Replacement 0 <--
+
+OLS L1_GETS 0 <--
+OLS L1_GETX 0 <--
+OLS L1_PUTX 0 <--
+OLS L1_PUTS_only 0 <--
+OLS L1_PUTS 0 <--
+OLS Fwd_GETX 0 <--
+OLS Fwd_GETS 0 <--
+OLS Fwd_DMA 0 <--
+OLS L2_Replacement 0 <--
+
+OLSX L1_GETS 0 <--
+OLSX L1_GETX 0 <--
+OLSX L1_PUTO 0 <--
+OLSX L1_PUTX 0 <--
+OLSX L1_PUTS_only 0 <--
+OLSX L1_PUTS 0 <--
+OLSX Fwd_GETX 0 <--
+OLSX Fwd_GETS 0 <--
+OLSX Fwd_DMA 0 <--
+OLSX L2_Replacement 0 <--
+
+SLS L1_GETS 0 <--
+SLS L1_GETX 0 <--
+SLS L1_PUTX 0 <--
+SLS L1_PUTS_only 0 <--
+SLS L1_PUTS 0 <--
+SLS Inv 0 <--
+SLS L2_Replacement 0 <--
+
+M L1_GETS 69
+M L1_GETX 14
+M L1_PUTO 0 <--
+M L1_PUTX 0 <--
+M L1_PUTS 0 <--
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_DMA 0 <--
+M L2_Replacement 411
+
+IFGX L1_GETS 0 <--
+IFGX L1_GETX 0 <--
+IFGX L1_PUTO 0 <--
+IFGX L1_PUTX 0 <--
+IFGX L1_PUTS_only 0 <--
+IFGX L1_PUTS 0 <--
+IFGX Fwd_GETX 0 <--
+IFGX Fwd_GETS 0 <--
+IFGX Fwd_DMA 0 <--
+IFGX Inv 0 <--
+IFGX Data 0 <--
+IFGX Data_Exclusive 0 <--
+IFGX L2_Replacement 0 <--
+
+IFGS L1_GETS 0 <--
+IFGS L1_GETX 0 <--
+IFGS L1_PUTO 0 <--
+IFGS L1_PUTX 0 <--
+IFGS L1_PUTS_only 0 <--
+IFGS L1_PUTS 0 <--
+IFGS Fwd_GETX 0 <--
+IFGS Fwd_GETS 0 <--
+IFGS Fwd_DMA 0 <--
+IFGS Inv 0 <--
+IFGS Data 0 <--
+IFGS Data_Exclusive 0 <--
+IFGS L2_Replacement 0 <--
+
+ISFGS L1_GETS 0 <--
+ISFGS L1_GETX 0 <--
+ISFGS L1_PUTO 0 <--
+ISFGS L1_PUTX 0 <--
+ISFGS L1_PUTS_only 0 <--
+ISFGS L1_PUTS 0 <--
+ISFGS Fwd_GETX 0 <--
+ISFGS Fwd_GETS 0 <--
+ISFGS Fwd_DMA 0 <--
+ISFGS Inv 0 <--
+ISFGS Data 0 <--
+ISFGS L2_Replacement 0 <--
+
+IFGXX L1_GETS 0 <--
+IFGXX L1_GETX 0 <--
+IFGXX L1_PUTO 0 <--
+IFGXX L1_PUTX 0 <--
+IFGXX L1_PUTS_only 0 <--
+IFGXX L1_PUTS 0 <--
+IFGXX Fwd_GETX 0 <--
+IFGXX Fwd_GETS 0 <--
+IFGXX Fwd_DMA 0 <--
+IFGXX Inv 0 <--
+IFGXX IntAck 0 <--
+IFGXX All_Acks 0 <--
+IFGXX Data_Exclusive 0 <--
+IFGXX L2_Replacement 0 <--
+
+OFGX L1_GETS 0 <--
+OFGX L1_GETX 0 <--
+OFGX L1_PUTO 0 <--
+OFGX L1_PUTX 0 <--
+OFGX L1_PUTS_only 0 <--
+OFGX L1_PUTS 0 <--
+OFGX Fwd_GETX 0 <--
+OFGX Fwd_GETS 0 <--
+OFGX Fwd_DMA 0 <--
+OFGX Inv 0 <--
+OFGX L2_Replacement 0 <--
+
+OLSF L1_GETS 0 <--
+OLSF L1_GETX 0 <--
+OLSF L1_PUTO 0 <--
+OLSF L1_PUTX 0 <--
+OLSF L1_PUTS_only 0 <--
+OLSF L1_PUTS 0 <--
+OLSF Fwd_GETX 0 <--
+OLSF Fwd_GETS 0 <--
+OLSF Fwd_DMA 0 <--
+OLSF Inv 0 <--
+OLSF IntAck 0 <--
+OLSF All_Acks 0 <--
+OLSF L2_Replacement 0 <--
+
+ILOW L1_GETS 0 <--
+ILOW L1_GETX 0 <--
+ILOW L1_PUTO 0 <--
+ILOW L1_PUTX 0 <--
+ILOW L1_PUTS_only 0 <--
+ILOW L1_PUTS 0 <--
+ILOW Fwd_GETX 0 <--
+ILOW Fwd_GETS 0 <--
+ILOW Fwd_DMA 0 <--
+ILOW Inv 0 <--
+ILOW L1_WBCLEANDATA 0 <--
+ILOW L1_WBDIRTYDATA 0 <--
+ILOW Unblock 0 <--
+ILOW L2_Replacement 0 <--
+
+ILOXW L1_GETS 0 <--
+ILOXW L1_GETX 0 <--
+ILOXW L1_PUTO 0 <--
+ILOXW L1_PUTX 0 <--
+ILOXW L1_PUTS_only 0 <--
+ILOXW L1_PUTS 0 <--
+ILOXW Fwd_GETX 0 <--
+ILOXW Fwd_GETS 0 <--
+ILOXW Fwd_DMA 0 <--
+ILOXW Inv 0 <--
+ILOXW L1_WBCLEANDATA 0 <--
+ILOXW L1_WBDIRTYDATA 0 <--
+ILOXW Unblock 0 <--
+ILOXW L2_Replacement 0 <--
+
+ILOSW L1_GETS 0 <--
+ILOSW L1_GETX 0 <--
+ILOSW L1_PUTO 0 <--
+ILOSW L1_PUTX 0 <--
+ILOSW L1_PUTS_only 0 <--
+ILOSW L1_PUTS 0 <--
+ILOSW Fwd_GETX 0 <--
+ILOSW Fwd_GETS 0 <--
+ILOSW Fwd_DMA 0 <--
+ILOSW Inv 0 <--
+ILOSW L1_WBCLEANDATA 0 <--
+ILOSW L1_WBDIRTYDATA 0 <--
+ILOSW Unblock 0 <--
+ILOSW L2_Replacement 0 <--
+
+ILOSXW L1_GETS 0 <--
+ILOSXW L1_GETX 0 <--
+ILOSXW L1_PUTO 0 <--
+ILOSXW L1_PUTX 0 <--
+ILOSXW L1_PUTS_only 0 <--
+ILOSXW L1_PUTS 0 <--
+ILOSXW Fwd_GETX 0 <--
+ILOSXW Fwd_GETS 0 <--
+ILOSXW Fwd_DMA 0 <--
+ILOSXW Inv 0 <--
+ILOSXW L1_WBCLEANDATA 0 <--
+ILOSXW L1_WBDIRTYDATA 0 <--
+ILOSXW Unblock 0 <--
+ILOSXW L2_Replacement 0 <--
+
+SLSW L1_GETS 0 <--
+SLSW L1_GETX 0 <--
+SLSW L1_PUTO 0 <--
+SLSW L1_PUTX 0 <--
+SLSW L1_PUTS_only 0 <--
+SLSW L1_PUTS 0 <--
+SLSW Fwd_GETX 0 <--
+SLSW Fwd_GETS 0 <--
+SLSW Fwd_DMA 0 <--
+SLSW Inv 0 <--
+SLSW Unblock 0 <--
+SLSW L2_Replacement 0 <--
+
+OLSW L1_GETS 0 <--
+OLSW L1_GETX 0 <--
+OLSW L1_PUTO 0 <--
+OLSW L1_PUTX 0 <--
+OLSW L1_PUTS_only 0 <--
+OLSW L1_PUTS 0 <--
+OLSW Fwd_GETX 0 <--
+OLSW Fwd_GETS 0 <--
+OLSW Fwd_DMA 0 <--
+OLSW Inv 0 <--
+OLSW Unblock 0 <--
+OLSW L2_Replacement 0 <--
+
+ILSW L1_GETS 0 <--
+ILSW L1_GETX 0 <--
+ILSW L1_PUTO 0 <--
+ILSW L1_PUTX 0 <--
+ILSW L1_PUTS_only 0 <--
+ILSW L1_PUTS 0 <--
+ILSW Fwd_GETX 0 <--
+ILSW Fwd_GETS 0 <--
+ILSW Fwd_DMA 0 <--
+ILSW Inv 0 <--
+ILSW L1_WBCLEANDATA 0 <--
+ILSW Unblock 0 <--
+ILSW L2_Replacement 0 <--
+
+IW L1_GETS 0 <--
+IW L1_GETX 0 <--
+IW L1_PUTO 0 <--
+IW L1_PUTX 0 <--
+IW L1_PUTS_only 0 <--
+IW L1_PUTS 0 <--
+IW Fwd_GETX 0 <--
+IW Fwd_GETS 0 <--
+IW Fwd_DMA 0 <--
+IW Inv 0 <--
+IW L1_WBCLEANDATA 0 <--
+IW L2_Replacement 0 <--
+
+OW L1_GETS 0 <--
+OW L1_GETX 0 <--
+OW L1_PUTO 0 <--
+OW L1_PUTX 0 <--
+OW L1_PUTS_only 0 <--
+OW L1_PUTS 0 <--
+OW Fwd_GETX 0 <--
+OW Fwd_GETS 0 <--
+OW Fwd_DMA 0 <--
+OW Inv 0 <--
+OW Unblock 0 <--
+OW L2_Replacement 0 <--
+
+SW L1_GETS 0 <--
+SW L1_GETX 0 <--
+SW L1_PUTO 0 <--
+SW L1_PUTX 0 <--
+SW L1_PUTS_only 0 <--
+SW L1_PUTS 0 <--
+SW Fwd_GETX 0 <--
+SW Fwd_GETS 0 <--
+SW Fwd_DMA 0 <--
+SW Inv 0 <--
+SW Unblock 0 <--
+SW L2_Replacement 0 <--
+
+OXW L1_GETS 0 <--
+OXW L1_GETX 0 <--
+OXW L1_PUTO 0 <--
+OXW L1_PUTX 0 <--
+OXW L1_PUTS_only 0 <--
+OXW L1_PUTS 0 <--
+OXW Fwd_GETX 0 <--
+OXW Fwd_GETS 0 <--
+OXW Fwd_DMA 0 <--
+OXW Inv 0 <--
+OXW Unblock 0 <--
+OXW L2_Replacement 0 <--
+
+OLSXW L1_GETS 0 <--
+OLSXW L1_GETX 0 <--
+OLSXW L1_PUTO 0 <--
+OLSXW L1_PUTX 0 <--
+OLSXW L1_PUTS_only 0 <--
+OLSXW L1_PUTS 0 <--
+OLSXW Fwd_GETX 0 <--
+OLSXW Fwd_GETS 0 <--
+OLSXW Fwd_DMA 0 <--
+OLSXW Inv 0 <--
+OLSXW Unblock 0 <--
+OLSXW L2_Replacement 0 <--
+
+ILXW L1_GETS 0 <--
+ILXW L1_GETX 0 <--
+ILXW L1_PUTO 0 <--
+ILXW L1_PUTX 0 <--
+ILXW L1_PUTS_only 0 <--
+ILXW L1_PUTS 0 <--
+ILXW Fwd_GETX 0 <--
+ILXW Fwd_GETS 0 <--
+ILXW Fwd_DMA 0 <--
+ILXW Inv 0 <--
+ILXW Data 0 <--
+ILXW L1_WBCLEANDATA 396
+ILXW L1_WBDIRTYDATA 106
+ILXW Unblock 0 <--
+ILXW L2_Replacement 0 <--
+
+IFLS L1_GETS 0 <--
+IFLS L1_GETX 0 <--
+IFLS L1_PUTO 0 <--
+IFLS L1_PUTX 0 <--
+IFLS L1_PUTS_only 0 <--
+IFLS L1_PUTS 0 <--
+IFLS Fwd_GETX 0 <--
+IFLS Fwd_GETS 0 <--
+IFLS Fwd_DMA 0 <--
+IFLS Inv 0 <--
+IFLS Unblock 0 <--
+IFLS L2_Replacement 0 <--
+
+IFLO L1_GETS 0 <--
+IFLO L1_GETX 0 <--
+IFLO L1_PUTO 0 <--
+IFLO L1_PUTX 0 <--
+IFLO L1_PUTS_only 0 <--
+IFLO L1_PUTS 0 <--
+IFLO Fwd_GETX 0 <--
+IFLO Fwd_GETS 0 <--
+IFLO Fwd_DMA 0 <--
+IFLO Inv 0 <--
+IFLO Unblock 0 <--
+IFLO L2_Replacement 0 <--
+
+IFLOX L1_GETS 0 <--
+IFLOX L1_GETX 0 <--
+IFLOX L1_PUTO 0 <--
+IFLOX L1_PUTX 0 <--
+IFLOX L1_PUTS_only 0 <--
+IFLOX L1_PUTS 0 <--
+IFLOX Fwd_GETX 0 <--
+IFLOX Fwd_GETS 0 <--
+IFLOX Fwd_DMA 0 <--
+IFLOX Inv 0 <--
+IFLOX Unblock 0 <--
+IFLOX Exclusive_Unblock 0 <--
+IFLOX L2_Replacement 0 <--
+
+IFLOXX L1_GETS 0 <--
+IFLOXX L1_GETX 0 <--
+IFLOXX L1_PUTO 0 <--
+IFLOXX L1_PUTX 0 <--
+IFLOXX L1_PUTS_only 0 <--
+IFLOXX L1_PUTS 0 <--
+IFLOXX Fwd_GETX 0 <--
+IFLOXX Fwd_GETS 0 <--
+IFLOXX Fwd_DMA 0 <--
+IFLOXX Inv 0 <--
+IFLOXX Unblock 0 <--
+IFLOXX Exclusive_Unblock 0 <--
+IFLOXX L2_Replacement 0 <--
+
+IFLOSX L1_GETS 0 <--
+IFLOSX L1_GETX 0 <--
+IFLOSX L1_PUTO 0 <--
+IFLOSX L1_PUTX 0 <--
+IFLOSX L1_PUTS_only 0 <--
+IFLOSX L1_PUTS 0 <--
+IFLOSX Fwd_GETX 0 <--
+IFLOSX Fwd_GETS 0 <--
+IFLOSX Fwd_DMA 0 <--
+IFLOSX Inv 0 <--
+IFLOSX Unblock 0 <--
+IFLOSX Exclusive_Unblock 0 <--
+IFLOSX L2_Replacement 0 <--
+
+IFLXO L1_GETS 0 <--
+IFLXO L1_GETX 0 <--
+IFLXO L1_PUTO 0 <--
+IFLXO L1_PUTX 0 <--
+IFLXO L1_PUTS_only 0 <--
+IFLXO L1_PUTS 0 <--
+IFLXO Fwd_GETX 0 <--
+IFLXO Fwd_GETS 0 <--
+IFLXO Fwd_DMA 0 <--
+IFLXO Inv 0 <--
+IFLXO Exclusive_Unblock 0 <--
+IFLXO L2_Replacement 0 <--
+
+IGS L1_GETS 0 <--
+IGS L1_GETX 0 <--
+IGS L1_PUTO 0 <--
+IGS L1_PUTX 0 <--
+IGS L1_PUTS_only 0 <--
+IGS L1_PUTS 0 <--
+IGS Fwd_GETX 0 <--
+IGS Fwd_GETS 0 <--
+IGS Fwd_DMA 0 <--
+IGS Own_GETX 0 <--
+IGS Inv 0 <--
+IGS Data 0 <--
+IGS Data_Exclusive 383
+IGS Unblock 0 <--
+IGS Exclusive_Unblock 383
+IGS L2_Replacement 0 <--
+
+IGM L1_GETS 0 <--
+IGM L1_GETX 0 <--
+IGM L1_PUTO 0 <--
+IGM L1_PUTX 0 <--
+IGM L1_PUTS_only 0 <--
+IGM L1_PUTS 0 <--
+IGM Fwd_GETX 0 <--
+IGM Fwd_GETS 0 <--
+IGM Fwd_DMA 0 <--
+IGM Own_GETX 0 <--
+IGM Inv 0 <--
+IGM ExtAck 0 <--
+IGM Data 44
+IGM Data_Exclusive 0 <--
+IGM L2_Replacement 0 <--
+
+IGMLS L1_GETS 0 <--
+IGMLS L1_GETX 0 <--
+IGMLS L1_PUTO 0 <--
+IGMLS L1_PUTX 0 <--
+IGMLS L1_PUTS_only 0 <--
+IGMLS L1_PUTS 0 <--
+IGMLS Inv 0 <--
+IGMLS IntAck 0 <--
+IGMLS ExtAck 0 <--
+IGMLS All_Acks 0 <--
+IGMLS Data 0 <--
+IGMLS Data_Exclusive 0 <--
+IGMLS L2_Replacement 0 <--
+
+IGMO L1_GETS 0 <--
+IGMO L1_GETX 0 <--
+IGMO L1_PUTO 0 <--
+IGMO L1_PUTX 0 <--
+IGMO L1_PUTS_only 0 <--
+IGMO L1_PUTS 0 <--
+IGMO Fwd_GETX 0 <--
+IGMO Fwd_GETS 0 <--
+IGMO Fwd_DMA 0 <--
+IGMO Own_GETX 0 <--
+IGMO ExtAck 0 <--
+IGMO All_Acks 44
+IGMO Exclusive_Unblock 44
+IGMO L2_Replacement 0 <--
+
+IGMIO L1_GETS 0 <--
+IGMIO L1_GETX 0 <--
+IGMIO L1_PUTO 0 <--
+IGMIO L1_PUTX 0 <--
+IGMIO L1_PUTS_only 0 <--
+IGMIO L1_PUTS 0 <--
+IGMIO Fwd_GETX 0 <--
+IGMIO Fwd_GETS 0 <--
+IGMIO Fwd_DMA 0 <--
+IGMIO Own_GETX 0 <--
+IGMIO ExtAck 0 <--
+IGMIO All_Acks 0 <--
+
+OGMIO L1_GETS 0 <--
+OGMIO L1_GETX 0 <--
+OGMIO L1_PUTO 0 <--
+OGMIO L1_PUTX 0 <--
+OGMIO L1_PUTS_only 0 <--
+OGMIO L1_PUTS 0 <--
+OGMIO Fwd_GETX 0 <--
+OGMIO Fwd_GETS 0 <--
+OGMIO Fwd_DMA 0 <--
+OGMIO Own_GETX 0 <--
+OGMIO ExtAck 0 <--
+OGMIO All_Acks 0 <--
+
+IGMIOF L1_GETS 0 <--
+IGMIOF L1_GETX 0 <--
+IGMIOF L1_PUTO 0 <--
+IGMIOF L1_PUTX 0 <--
+IGMIOF L1_PUTS_only 0 <--
+IGMIOF L1_PUTS 0 <--
+IGMIOF IntAck 0 <--
+IGMIOF All_Acks 0 <--
+IGMIOF Data_Exclusive 0 <--
+
+IGMIOFS L1_GETS 0 <--
+IGMIOFS L1_GETX 0 <--
+IGMIOFS L1_PUTO 0 <--
+IGMIOFS L1_PUTX 0 <--
+IGMIOFS L1_PUTS_only 0 <--
+IGMIOFS L1_PUTS 0 <--
+IGMIOFS Fwd_GETX 0 <--
+IGMIOFS Fwd_GETS 0 <--
+IGMIOFS Fwd_DMA 0 <--
+IGMIOFS Inv 0 <--
+IGMIOFS Data 0 <--
+IGMIOFS L2_Replacement 0 <--
+
+OGMIOF L1_GETS 0 <--
+OGMIOF L1_GETX 0 <--
+OGMIOF L1_PUTO 0 <--
+OGMIOF L1_PUTX 0 <--
+OGMIOF L1_PUTS_only 0 <--
+OGMIOF L1_PUTS 0 <--
+OGMIOF IntAck 0 <--
+OGMIOF All_Acks 0 <--
+
+II L1_GETS 0 <--
+II L1_GETX 0 <--
+II L1_PUTO 0 <--
+II L1_PUTX 0 <--
+II L1_PUTS_only 0 <--
+II L1_PUTS 0 <--
+II IntAck 0 <--
+II All_Acks 0 <--
+
+MM L1_GETS 0 <--
+MM L1_GETX 0 <--
+MM L1_PUTO 0 <--
+MM L1_PUTX 0 <--
+MM L1_PUTS_only 0 <--
+MM L1_PUTS 0 <--
+MM Fwd_GETX 0 <--
+MM Fwd_GETS 0 <--
+MM Fwd_DMA 0 <--
+MM Inv 0 <--
+MM Exclusive_Unblock 14
+MM L2_Replacement 0 <--
+
+SS L1_GETS 0 <--
+SS L1_GETX 0 <--
+SS L1_PUTO 0 <--
+SS L1_PUTX 0 <--
+SS L1_PUTS_only 0 <--
+SS L1_PUTS 0 <--
+SS Fwd_GETX 0 <--
+SS Fwd_GETS 0 <--
+SS Fwd_DMA 0 <--
+SS Inv 0 <--
+SS Unblock 0 <--
+SS L2_Replacement 0 <--
+
+OO L1_GETS 0 <--
+OO L1_GETX 0 <--
+OO L1_PUTO 0 <--
+OO L1_PUTX 0 <--
+OO L1_PUTS_only 0 <--
+OO L1_PUTS 0 <--
+OO Fwd_GETX 0 <--
+OO Fwd_GETS 0 <--
+OO Fwd_DMA 0 <--
+OO Inv 0 <--
+OO Unblock 0 <--
+OO Exclusive_Unblock 69
+OO L2_Replacement 0 <--
+
+OLSS L1_GETS 0 <--
+OLSS L1_GETX 0 <--
+OLSS L1_PUTO 0 <--
+OLSS L1_PUTX 0 <--
+OLSS L1_PUTS_only 0 <--
+OLSS L1_PUTS 0 <--
+OLSS Fwd_GETX 0 <--
+OLSS Fwd_GETS 0 <--
+OLSS Fwd_DMA 0 <--
+OLSS Inv 0 <--
+OLSS Unblock 0 <--
+OLSS L2_Replacement 0 <--
+
+OLSXS L1_GETS 0 <--
+OLSXS L1_GETX 0 <--
+OLSXS L1_PUTO 0 <--
+OLSXS L1_PUTX 0 <--
+OLSXS L1_PUTS_only 0 <--
+OLSXS L1_PUTS 0 <--
+OLSXS Fwd_GETX 0 <--
+OLSXS Fwd_GETS 0 <--
+OLSXS Fwd_DMA 0 <--
+OLSXS Inv 0 <--
+OLSXS Unblock 0 <--
+OLSXS L2_Replacement 0 <--
+
+SLSS L1_GETS 0 <--
+SLSS L1_GETX 0 <--
+SLSS L1_PUTO 0 <--
+SLSS L1_PUTX 0 <--
+SLSS L1_PUTS_only 0 <--
+SLSS L1_PUTS 0 <--
+SLSS Fwd_GETX 0 <--
+SLSS Fwd_GETS 0 <--
+SLSS Fwd_DMA 0 <--
+SLSS Inv 0 <--
+SLSS Unblock 0 <--
+SLSS L2_Replacement 0 <--
+
+OI L1_GETS 0 <--
+OI L1_GETX 0 <--
+OI L1_PUTO 0 <--
+OI L1_PUTX 0 <--
+OI L1_PUTS_only 0 <--
+OI L1_PUTS 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Nack 0 <--
+OI L2_Replacement 0 <--
+
+MI L1_GETS 3
+MI L1_GETX 0 <--
+MI L1_PUTO 0 <--
+MI L1_PUTX 0 <--
+MI L1_PUTS_only 0 <--
+MI L1_PUTS 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 411
+MI L2_Replacement 0 <--
+
+MII L1_GETS 0 <--
+MII L1_GETX 0 <--
+MII L1_PUTO 0 <--
+MII L1_PUTX 0 <--
+MII L1_PUTS_only 0 <--
+MII L1_PUTS 0 <--
+MII Writeback_Ack 0 <--
+MII Writeback_Nack 0 <--
+MII L2_Replacement 0 <--
+
+OLSI L1_GETS 0 <--
+OLSI L1_GETX 0 <--
+OLSI L1_PUTO 0 <--
+OLSI L1_PUTX 0 <--
+OLSI L1_PUTS_only 0 <--
+OLSI L1_PUTS 0 <--
+OLSI Fwd_GETX 0 <--
+OLSI Fwd_GETS 0 <--
+OLSI Fwd_DMA 0 <--
+OLSI Writeback_Ack 0 <--
+OLSI L2_Replacement 0 <--
+
+ILSI L1_GETS 0 <--
+ILSI L1_GETX 0 <--
+ILSI L1_PUTO 0 <--
+ILSI L1_PUTX 0 <--
+ILSI L1_PUTS_only 0 <--
+ILSI L1_PUTS 0 <--
+ILSI IntAck 0 <--
+ILSI All_Acks 0 <--
+ILSI Writeback_Ack 0 <--
+ILSI L2_Replacement 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+ memory_total_requests: 504
+ memory_reads: 427
+ memory_writes: 77
+ memory_refreshes: 180
+ memory_total_request_delays: 114
+ memory_delays_per_request: 0.22619
+ memory_delays_in_input_queue: 2
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 112
+ memory_stalls_for_bank_busy: 58
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 8
+ memory_stalls_for_bus: 22
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 24
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 18 10 0 35 20 20 28 21 5 3 6 4 21 40 20 3 4 5 7 13 10 16 14 41 16 5 5 12 12 18 14 58
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 44
+GETS 383
+PUTX 411
+PUTO 0
+PUTO_SHARERS 0
+Unblock 0
+Last_Unblock 0
+Exclusive_Unblock 426
+Clean_Writeback 334
+Dirty_Writeback 77
+Memory_Data 427
+Memory_Ack 77
+DMA_READ 0
+DMA_WRITE 0
+Data 0
+
+ - Transitions -
+I GETX 44
+I GETS 383
+I PUTX 0 <--
+I PUTO 0 <--
+I Memory_Data 0 <--
+I Memory_Ack 75
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+S GETX 0 <--
+S GETS 0 <--
+S PUTX 0 <--
+S PUTO 0 <--
+S Memory_Data 0 <--
+S Memory_Ack 0 <--
+S DMA_READ 0 <--
+S DMA_WRITE 0 <--
+
+O GETX 0 <--
+O GETS 0 <--
+O PUTX 0 <--
+O PUTO 0 <--
+O PUTO_SHARERS 0 <--
+O Memory_Data 0 <--
+O Memory_Ack 0 <--
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+
+M GETX 0 <--
+M GETS 0 <--
+M PUTX 411
+M PUTO 0 <--
+M PUTO_SHARERS 0 <--
+M Memory_Data 0 <--
+M Memory_Ack 0 <--
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+
+IS GETX 0 <--
+IS GETS 0 <--
+IS PUTX 0 <--
+IS PUTO 0 <--
+IS PUTO_SHARERS 0 <--
+IS Unblock 0 <--
+IS Exclusive_Unblock 382
+IS Memory_Data 383
+IS Memory_Ack 1
+IS DMA_READ 0 <--
+IS DMA_WRITE 0 <--
+
+SS GETX 0 <--
+SS GETS 0 <--
+SS PUTX 0 <--
+SS PUTO 0 <--
+SS PUTO_SHARERS 0 <--
+SS Unblock 0 <--
+SS Last_Unblock 0 <--
+SS Memory_Data 0 <--
+SS Memory_Ack 0 <--
+SS DMA_READ 0 <--
+SS DMA_WRITE 0 <--
+
+OO GETX 0 <--
+OO GETS 0 <--
+OO PUTX 0 <--
+OO PUTO 0 <--
+OO PUTO_SHARERS 0 <--
+OO Unblock 0 <--
+OO Last_Unblock 0 <--
+OO Memory_Data 0 <--
+OO Memory_Ack 0 <--
+OO DMA_READ 0 <--
+OO DMA_WRITE 0 <--
+
+MO GETX 0 <--
+MO GETS 0 <--
+MO PUTX 0 <--
+MO PUTO 0 <--
+MO PUTO_SHARERS 0 <--
+MO Unblock 0 <--
+MO Exclusive_Unblock 0 <--
+MO Memory_Data 0 <--
+MO Memory_Ack 0 <--
+MO DMA_READ 0 <--
+MO DMA_WRITE 0 <--
+
+MM GETX 0 <--
+MM GETS 0 <--
+MM PUTX 0 <--
+MM PUTO 0 <--
+MM PUTO_SHARERS 0 <--
+MM Exclusive_Unblock 44
+MM Memory_Data 44
+MM Memory_Ack 1
+MM DMA_READ 0 <--
+MM DMA_WRITE 0 <--
+
+
+MI GETX 0 <--
+MI GETS 0 <--
+MI PUTX 0 <--
+MI PUTO 0 <--
+MI PUTO_SHARERS 0 <--
+MI Unblock 0 <--
+MI Clean_Writeback 334
+MI Dirty_Writeback 77
+MI Memory_Data 0 <--
+MI Memory_Ack 0 <--
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+
+MIS GETX 0 <--
+MIS GETS 0 <--
+MIS PUTX 0 <--
+MIS PUTO 0 <--
+MIS PUTO_SHARERS 0 <--
+MIS Unblock 0 <--
+MIS Clean_Writeback 0 <--
+MIS Dirty_Writeback 0 <--
+MIS Memory_Data 0 <--
+MIS Memory_Ack 0 <--
+MIS DMA_READ 0 <--
+MIS DMA_WRITE 0 <--
+
+OS GETX 0 <--
+OS GETS 0 <--
+OS PUTX 0 <--
+OS PUTO 0 <--
+OS PUTO_SHARERS 0 <--
+OS Unblock 0 <--
+OS Clean_Writeback 0 <--
+OS Dirty_Writeback 0 <--
+OS Memory_Data 0 <--
+OS Memory_Ack 0 <--
+OS DMA_READ 0 <--
+OS DMA_WRITE 0 <--
+
+OSS GETX 0 <--
+OSS GETS 0 <--
+OSS PUTX 0 <--
+OSS PUTO 0 <--
+OSS PUTO_SHARERS 0 <--
+OSS Unblock 0 <--
+OSS Clean_Writeback 0 <--
+OSS Dirty_Writeback 0 <--
+OSS Memory_Data 0 <--
+OSS Memory_Ack 0 <--
+OSS DMA_READ 0 <--
+OSS DMA_WRITE 0 <--
+
+XI_M GETX 0 <--
+XI_M GETS 0 <--
+XI_M PUTX 0 <--
+XI_M PUTO 0 <--
+XI_M PUTO_SHARERS 0 <--
+XI_M Memory_Data 0 <--
+XI_M Memory_Ack 0 <--
+XI_M DMA_READ 0 <--
+XI_M DMA_WRITE 0 <--
+
+XI_U GETX 0 <--
+XI_U GETS 0 <--
+XI_U PUTX 0 <--
+XI_U PUTO 0 <--
+XI_U PUTO_SHARERS 0 <--
+XI_U Exclusive_Unblock 0 <--
+XI_U Memory_Ack 0 <--
+XI_U DMA_READ 0 <--
+XI_U DMA_WRITE 0 <--
+
+OI_D GETX 0 <--
+OI_D GETS 0 <--
+OI_D PUTX 0 <--
+OI_D PUTO 0 <--
+OI_D PUTO_SHARERS 0 <--
+OI_D DMA_READ 0 <--
+OI_D DMA_WRITE 0 <--
+OI_D Data 0 <--
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 14:49:51
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 15:08:15
+M5 executing on svvint05
+command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 85988 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 14317 # Simulator instruction rate (inst/s)
+host_mem_usage 214996 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
+host_tick_rate 477706 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_insts 2577 # Number of instructions simulated
+sim_seconds 0.000086 # Number of seconds simulated
+sim_ticks 85988 # Number of ticks simulated
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 419 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 415 # DTB read hits
+system.cpu.dtb.read_misses 4 # DTB read misses
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 294 # DTB write hits
+system.cpu.dtb.write_misses 4 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 2586 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 85988 # number of cpu cycles simulated
+system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.num_refs 717 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=1
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+num_int_nodes=4
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+N_tokens=2
+buffer_size=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+N_tokens=2
+buffer_size=0
+filtering_enabled=true
+l2_request_latency=10
+l2_response_latency=10
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links2.ext_node.directory
+directory_latency=6
+distributed_persistent=true
+fixed_timeout_latency=300
+l2_select_num_bits=0
+memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=3
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: active, ordered
+virtual_net_3: active, unordered
+virtual_net_4: active, unordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 15:55:46
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.35
+Virtual_time_in_minutes: 0.00583333
+Virtual_time_in_hours: 9.72222e-05
+Virtual_time_in_days: 4.05093e-06
+
+Ruby_current_time: 90308
+Ruby_start_time: 0
+Ruby_cycles: 90308
+
+mbytes_resident: 33.1172
+mbytes_total: 33.125
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 90309 [ 90309 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 2 max: 283 count: 3294 average: 26.4159 | standard deviation: 58.1846 | 0 2776 0 0 0 0 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 89 61 81 78 45 5 4 1 0 2 20 13 13 11 10 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 283 count: 2585 average: 19.2785 | standard deviation: 49.8133 | 0 2315 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 44 38 49 22 3 4 0 0 0 9 11 3 8 6 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 273 count: 415 average: 66.3494 | standard deviation: 81.4668 | 0 233 0 0 0 0 0 0 0 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 34 18 20 1 0 1 0 2 6 2 10 2 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 259 count: 294 average: 32.8027 | standard deviation: 63.5503 | 0 228 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 2 9 11 3 1 0 0 0 0 5 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 7136
+page_faults: 2141
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.160659
+ links_utilized_percent_switch_0_link_0: 0.0646399 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.256677 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.0939286
+ links_utilized_percent_switch_1_link_0: 0.0641693 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.123688 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.120795
+ links_utilized_percent_switch_2_link_0: 0.0213436 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.220246 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 3
+switch_3_outlinks: 3
+links_utilized_percent_switch_3: 0.200204
+ links_utilized_percent_switch_3_link_0: 0.25856 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.256677 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.0853745 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 415
+Ifetch 2585
+Store 294
+L1_Replacement 502
+Data_Shared 59
+Data_Owner 0
+Data_All_Tokens 459
+Ack 8
+Ack_All_Tokens 0
+Transient_GETX 0
+Transient_Local_GETX 0
+Transient_GETS 0
+Transient_Local_GETS 0
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 0
+Persistent_GETS 0
+Own_Lock_or_Unlock 0
+Request_Timeout 0
+Use_TimeoutStarverX 0
+Use_TimeoutStarverS 0
+Use_TimeoutNoStarvers 458
+
+ - Transitions -
+NP Load 182
+NP Ifetch 270
+NP Store 58
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 0 <--
+
+S Load 30
+S Ifetch 188
+S Store 8
+S L1_Replacement 50
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 0 <--
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 0 <--
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 0 <--
+
+M Load 67
+M Ifetch 1196
+M Store 29
+M L1_Replacement 356
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 0 <--
+M Persistent_GETS 0 <--
+M Own_Lock_or_Unlock 0 <--
+
+MM Load 96
+MM Ifetch 0 <--
+MM Store 111
+MM L1_Replacement 96
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 0 <--
+MM Persistent_GETS 0 <--
+MM Own_Lock_or_Unlock 0 <--
+
+M_W Load 34
+M_W Ifetch 931
+M_W Store 3
+M_W L1_Replacement 0 <--
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 0 <--
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 0 <--
+M_W Persistent_GETX 0 <--
+M_W Persistent_GETS 0 <--
+M_W Own_Lock_or_Unlock 0 <--
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 389
+
+MM_W Load 6
+MM_W Ifetch 0 <--
+MM_W Store 85
+MM_W L1_Replacement 0 <--
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 0 <--
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 0 <--
+MM_W Persistent_GETX 0 <--
+MM_W Persistent_GETS 0 <--
+MM_W Own_Lock_or_Unlock 0 <--
+MM_W Use_TimeoutStarverX 0 <--
+MM_W Use_TimeoutStarverS 0 <--
+MM_W Use_TimeoutNoStarvers 69
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 0 <--
+IM Data_All_Tokens 58
+IM Ack 1
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 0 <--
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 0 <--
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 0 <--
+IM Persistent_GETS 0 <--
+IM Own_Lock_or_Unlock 0 <--
+IM Request_Timeout 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 8
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 0 <--
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 0 <--
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 0 <--
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 0 <--
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 0 <--
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 0 <--
+OM Persistent_GETS 0 <--
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 59
+IS Data_Owner 0 <--
+IS Data_All_Tokens 393
+IS Ack 7
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 0 <--
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 0 <--
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 0 <--
+IS Persistent_GETS 0 <--
+IS Own_Lock_or_Unlock 0 <--
+IS Request_Timeout 0 <--
+
+I_L Load 0 <--
+I_L Ifetch 0 <--
+I_L Store 0 <--
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 0 <--
+I_L Persistent_GETS 0 <--
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 0 <--
+S_L Ifetch 0 <--
+S_L Store 0 <--
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 0 <--
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 0 <--
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 0 <--
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 0 <--
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 0 <--
+IM_L Persistent_GETS 0 <--
+IM_L Own_Lock_or_Unlock 0 <--
+IM_L Request_Timeout 0 <--
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 0 <--
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 0 <--
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 0 <--
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 0 <--
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 0 <--
+IS_L Persistent_GETS 0 <--
+IS_L Own_Lock_or_Unlock 0 <--
+IS_L Request_Timeout 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GETS 445
+L1_GETS_Last_Token 7
+L1_GETX 66
+L1_INV 0
+Transient_GETX 0
+Transient_GETS 0
+Transient_GETS_Last_Token 0
+L2_Replacement 463
+Writeback_Tokens 27
+Writeback_Shared_Data 0
+Writeback_All_Tokens 475
+Writeback_Owned 0
+Data_Shared 0
+Data_Owner 0
+Data_All_Tokens 0
+Ack 0
+Ack_All_Tokens 0
+Persistent_GETX 0
+Persistent_GETS 0
+Own_Lock_or_Unlock 0
+
+ - Transitions -
+NP L1_GETS 386
+NP L1_GETX 48
+NP L1_INV 0 <--
+NP Transient_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Writeback_Tokens 27
+NP Writeback_Shared_Data 0 <--
+NP Writeback_All_Tokens 444
+NP Writeback_Owned 0 <--
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I L1_GETS 0 <--
+I L1_GETS_Last_Token 7
+I L1_GETX 1
+I L1_INV 0 <--
+I Transient_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I L2_Replacement 34
+I Writeback_Tokens 0 <--
+I Writeback_Shared_Data 0 <--
+I Writeback_All_Tokens 8
+I Writeback_Owned 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 0 <--
+
+S L1_GETS 0 <--
+S L1_GETS_Last_Token 0 <--
+S L1_GETX 0 <--
+S L1_INV 0 <--
+S Transient_GETX 0 <--
+S Transient_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S L2_Replacement 0 <--
+S Writeback_Tokens 0 <--
+S Writeback_Shared_Data 0 <--
+S Writeback_All_Tokens 0 <--
+S Writeback_Owned 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O L1_GETS 0 <--
+O L1_GETS_Last_Token 0 <--
+O L1_GETX 5
+O L1_INV 0 <--
+O Transient_GETX 0 <--
+O Transient_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O L2_Replacement 31
+O Writeback_Tokens 0 <--
+O Writeback_Shared_Data 0 <--
+O Writeback_All_Tokens 23
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 0 <--
+
+M L1_GETS 59
+M L1_GETX 12
+M L1_INV 0 <--
+M Transient_GETX 0 <--
+M Transient_GETS 0 <--
+M L2_Replacement 398
+M Persistent_GETX 0 <--
+M Persistent_GETS 0 <--
+M Own_Lock_or_Unlock 0 <--
+
+I_L L1_GETS 0 <--
+I_L L1_GETX 0 <--
+I_L L1_INV 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L L2_Replacement 0 <--
+I_L Writeback_Tokens 0 <--
+I_L Writeback_Shared_Data 0 <--
+I_L Writeback_All_Tokens 0 <--
+I_L Writeback_Owned 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Persistent_GETX 0 <--
+I_L Persistent_GETS 0 <--
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L L1_GETS 0 <--
+S_L L1_GETS_Last_Token 0 <--
+S_L L1_GETX 0 <--
+S_L L1_INV 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L L2_Replacement 0 <--
+S_L Writeback_Tokens 0 <--
+S_L Writeback_Shared_Data 0 <--
+S_L Writeback_All_Tokens 0 <--
+S_L Writeback_Owned 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+ memory_total_requests: 523
+ memory_reads: 442
+ memory_writes: 81
+ memory_refreshes: 189
+ memory_total_request_delays: 199
+ memory_delays_per_request: 0.380497
+ memory_delays_in_input_queue: 67
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 132
+ memory_stalls_for_bank_busy: 41
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 7
+ memory_stalls_for_bus: 80
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 4
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 19 10 0 41 20 19 31 22 5 3 6 4 21 40 20 3 4 6 7 14 10 16 14 41 16 5 5 12 12 18 14 65
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 63
+GETS 409
+Lockdown 0
+Unlockdown 0
+Own_Lock_or_Unlock 0
+Data_Owner 6
+Data_All_Tokens 75
+Ack_Owner 25
+Ack_Owner_All_Tokens 323
+Tokens 0
+Ack_All_Tokens 18
+Request_Timeout 0
+Memory_Data 442
+Memory_Ack 81
+DMA_READ 0
+DMA_WRITE 0
+DMA_WRITE_All_Tokens 0
+
+ - Transitions -
+O GETX 49
+O GETS 393
+O Lockdown 0 <--
+O Own_Lock_or_Unlock 0 <--
+O Data_Owner 0 <--
+O Data_All_Tokens 0 <--
+O Tokens 0 <--
+O Ack_All_Tokens 18
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+O DMA_WRITE_All_Tokens 0 <--
+
+NO GETX 5
+NO GETS 0 <--
+NO Lockdown 0 <--
+NO Own_Lock_or_Unlock 0 <--
+NO Data_Owner 6
+NO Data_All_Tokens 75
+NO Ack_Owner 25
+NO Ack_Owner_All_Tokens 323
+NO Tokens 0 <--
+NO DMA_READ 0 <--
+NO DMA_WRITE 0 <--
+
+L GETX 0 <--
+L GETS 0 <--
+L Lockdown 0 <--
+L Unlockdown 0 <--
+L Own_Lock_or_Unlock 0 <--
+L Data_Owner 0 <--
+L Data_All_Tokens 0 <--
+L Ack_Owner 0 <--
+L Ack_Owner_All_Tokens 0 <--
+L Tokens 0 <--
+L DMA_READ 0 <--
+L DMA_WRITE 0 <--
+
+O_W GETX 9
+O_W GETS 16
+O_W Lockdown 0 <--
+O_W Unlockdown 0 <--
+O_W Own_Lock_or_Unlock 0 <--
+O_W Data_Owner 0 <--
+O_W Ack_Owner 0 <--
+O_W Tokens 0 <--
+O_W Ack_All_Tokens 0 <--
+O_W Memory_Data 0 <--
+O_W Memory_Ack 81
+O_W DMA_READ 0 <--
+O_W DMA_WRITE 0 <--
+
+L_O_W GETX 0 <--
+L_O_W GETS 0 <--
+L_O_W Lockdown 0 <--
+L_O_W Unlockdown 0 <--
+L_O_W Own_Lock_or_Unlock 0 <--
+L_O_W Data_Owner 0 <--
+L_O_W Ack_Owner 0 <--
+L_O_W Tokens 0 <--
+L_O_W Ack_All_Tokens 0 <--
+L_O_W Memory_Data 0 <--
+L_O_W Memory_Ack 0 <--
+L_O_W DMA_READ 0 <--
+L_O_W DMA_WRITE 0 <--
+
+L_NO_W GETX 0 <--
+L_NO_W GETS 0 <--
+L_NO_W Lockdown 0 <--
+L_NO_W Unlockdown 0 <--
+L_NO_W Own_Lock_or_Unlock 0 <--
+L_NO_W Data_Owner 0 <--
+L_NO_W Ack_Owner 0 <--
+L_NO_W Tokens 0 <--
+L_NO_W Ack_All_Tokens 0 <--
+L_NO_W Memory_Data 0 <--
+L_NO_W DMA_READ 0 <--
+L_NO_W DMA_WRITE 0 <--
+
+DR_L_W GETX 0 <--
+DR_L_W GETS 0 <--
+DR_L_W Lockdown 0 <--
+DR_L_W Unlockdown 0 <--
+DR_L_W Own_Lock_or_Unlock 0 <--
+DR_L_W Data_Owner 0 <--
+DR_L_W Ack_Owner 0 <--
+DR_L_W Tokens 0 <--
+DR_L_W Ack_All_Tokens 0 <--
+DR_L_W Request_Timeout 0 <--
+DR_L_W Memory_Data 0 <--
+DR_L_W DMA_READ 0 <--
+DR_L_W DMA_WRITE 0 <--
+
+NO_W GETX 0 <--
+NO_W GETS 0 <--
+NO_W Lockdown 0 <--
+NO_W Unlockdown 0 <--
+NO_W Own_Lock_or_Unlock 0 <--
+NO_W Data_Owner 0 <--
+NO_W Ack_Owner 0 <--
+NO_W Tokens 0 <--
+NO_W Ack_All_Tokens 0 <--
+NO_W Memory_Data 442
+NO_W DMA_READ 0 <--
+NO_W DMA_WRITE 0 <--
+
+O_DW_W GETX 0 <--
+O_DW_W GETS 0 <--
+O_DW_W Data_Owner 0 <--
+O_DW_W Ack_Owner 0 <--
+O_DW_W Tokens 0 <--
+O_DW_W Ack_All_Tokens 0 <--
+O_DW_W Memory_Ack 0 <--
+O_DW_W DMA_READ 0 <--
+O_DW_W DMA_WRITE 0 <--
+
+O_DR_W GETX 0 <--
+O_DR_W GETS 0 <--
+O_DR_W Lockdown 0 <--
+O_DR_W Unlockdown 0 <--
+O_DR_W Own_Lock_or_Unlock 0 <--
+O_DR_W Data_Owner 0 <--
+O_DR_W Ack_Owner 0 <--
+O_DR_W Tokens 0 <--
+O_DR_W Ack_All_Tokens 0 <--
+O_DR_W Memory_Data 0 <--
+O_DR_W DMA_READ 0 <--
+O_DR_W DMA_WRITE 0 <--
+
+O_DW GETX 0 <--
+O_DW GETS 0 <--
+O_DW Lockdown 0 <--
+O_DW Own_Lock_or_Unlock 0 <--
+O_DW Data_Owner 0 <--
+O_DW Data_All_Tokens 0 <--
+O_DW Ack_Owner 0 <--
+O_DW Ack_Owner_All_Tokens 0 <--
+O_DW Tokens 0 <--
+O_DW Ack_All_Tokens 0 <--
+O_DW DMA_READ 0 <--
+O_DW DMA_WRITE 0 <--
+
+NO_DW GETX 0 <--
+NO_DW GETS 0 <--
+NO_DW Lockdown 0 <--
+NO_DW Own_Lock_or_Unlock 0 <--
+NO_DW Data_Owner 0 <--
+NO_DW Data_All_Tokens 0 <--
+NO_DW Tokens 0 <--
+NO_DW Request_Timeout 0 <--
+NO_DW DMA_READ 0 <--
+NO_DW DMA_WRITE 0 <--
+
+NO_DR GETX 0 <--
+NO_DR GETS 0 <--
+NO_DR Lockdown 0 <--
+NO_DR Own_Lock_or_Unlock 0 <--
+NO_DR Data_Owner 0 <--
+NO_DR Data_All_Tokens 0 <--
+NO_DR Tokens 0 <--
+NO_DR Request_Timeout 0 <--
+NO_DR DMA_READ 0 <--
+NO_DR DMA_WRITE 0 <--
+
+DW_L GETX 0 <--
+DW_L GETS 0 <--
+DW_L Lockdown 0 <--
+DW_L Unlockdown 0 <--
+DW_L Own_Lock_or_Unlock 0 <--
+DW_L Data_Owner 0 <--
+DW_L Data_All_Tokens 0 <--
+DW_L Ack_Owner 0 <--
+DW_L Ack_Owner_All_Tokens 0 <--
+DW_L Tokens 0 <--
+DW_L Request_Timeout 0 <--
+DW_L DMA_READ 0 <--
+DW_L DMA_WRITE 0 <--
+
+DR_L GETX 0 <--
+DR_L GETS 0 <--
+DR_L Lockdown 0 <--
+DR_L Unlockdown 0 <--
+DR_L Own_Lock_or_Unlock 0 <--
+DR_L Data_Owner 0 <--
+DR_L Data_All_Tokens 0 <--
+DR_L Ack_Owner 0 <--
+DR_L Ack_Owner_All_Tokens 0 <--
+DR_L Tokens 0 <--
+DR_L Request_Timeout 0 <--
+DR_L DMA_READ 0 <--
+DR_L DMA_WRITE 0 <--
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 15:54:34
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 15:55:46
+M5 executing on svvint04
+command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 90308 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 18406 # Simulator instruction rate (inst/s)
+host_mem_usage 214900 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
+host_tick_rate 602029 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_insts 2577 # Number of instructions simulated
+sim_seconds 0.000090 # Number of seconds simulated
+sim_ticks 90308 # Number of ticks simulated
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 419 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 415 # DTB read hits
+system.cpu.dtb.read_misses 4 # DTB read misses
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 294 # DTB write hits
+system.cpu.dtb.write_misses 4 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 2586 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 90308 # number of cpu cycles simulated
+system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.num_refs 717 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=1
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
+buffer_size=0
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+memory_controller_latency=12
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: active, unordered
+virtual_net_4: active, ordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 11:48:25
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.33
+Virtual_time_in_minutes: 0.0055
+Virtual_time_in_hours: 9.16667e-05
+Virtual_time_in_days: 3.81944e-06
+
+Ruby_current_time: 81672
+Ruby_start_time: 0
+Ruby_cycles: 81672
+
+mbytes_resident: 31.8555
+mbytes_total: 31.8633
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 81673 [ 81673 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 2 max: 333 count: 3294 average: 23.7942 | standard deviation: 53.6415 | 0 2853 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87 74 46 111 83 4 0 4 2 0 2 2 0 0 1 1 2 0 0 0 2 2 2 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 243 count: 2585 average: 17.6507 | standard deviation: 45.0947 | 0 2337 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 47 26 56 63 2 0 2 1 0 1 2 0 0 0 1 1 0 0 0 1 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 333 count: 415 average: 57.9108 | standard deviation: 76.4181 | 0 269 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 16 18 39 18 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 333 count: 294 average: 29.6531 | standard deviation: 64.3241 | 0 247 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 11 2 16 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 6878
+page_faults: 2029
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.106447
+ links_utilized_percent_switch_0_link_0: 0.0672507 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.145644 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.152707
+ links_utilized_percent_switch_1_link_0: 0.0364109 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.269003 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.207323
+ links_utilized_percent_switch_2_link_0: 0.269003 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.145644 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 248
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 248
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 248 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 248 average: 4 | standard deviation: 0 | 0 0 0 0 248 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 193
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 193
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 75.6477%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 24.3523%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 193 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 193 average: 7.25389 | standard deviation: 1.56292 | 0 0 0 0 36 0 0 0 157 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 437
+Ifetch 2603
+Store 306
+L2_Replacement 425
+L1_to_L2 502
+L2_to_L1D 47
+L2_to_L1I 22
+Other_GETX 0
+Other_GETS 0
+Ack 0
+Shared_Ack 0
+Data 0
+Shared_Data 0
+Exclusive_Data 441
+Writeback_Ack 425
+Writeback_Nack 0
+All_acks 0
+All_acks_no_sharers 441
+
+ - Transitions -
+I Load 146
+I Ifetch 248
+I Store 47
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 0 <--
+S Other_GETS 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 0 <--
+O Other_GETS 0 <--
+
+M Load 131
+M Ifetch 2337
+M Store 36
+M L2_Replacement 344
+M L1_to_L2 397
+M L2_to_L1D 23
+M L2_to_L1I 22
+M Other_GETX 0 <--
+M Other_GETS 0 <--
+
+MM Load 138
+MM Ifetch 0 <--
+MM Store 211
+MM L2_Replacement 81
+MM L1_to_L2 105
+MM L2_to_L1D 24
+MM L2_to_L1I 0 <--
+MM Other_GETX 0 <--
+MM Other_GETS 0 <--
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 0 <--
+IM Other_GETS 0 <--
+IM Ack 0 <--
+IM Data 0 <--
+IM Exclusive_Data 47
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 0 <--
+SM Other_GETS 0 <--
+SM Ack 0 <--
+SM Data 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 0 <--
+OM Other_GETS 0 <--
+OM Ack 0 <--
+OM All_acks 0 <--
+OM All_acks_no_sharers 0 <--
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 0 <--
+ISM All_acks_no_sharers 0 <--
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 0 <--
+M_W All_acks_no_sharers 394
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 0 <--
+MM_W All_acks_no_sharers 47
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 0 <--
+IS Other_GETS 0 <--
+IS Ack 0 <--
+IS Shared_Ack 0 <--
+IS Data 0 <--
+IS Shared_Data 0 <--
+IS Exclusive_Data 394
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 0 <--
+SS Shared_Ack 0 <--
+SS All_acks 0 <--
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 22
+MI Ifetch 18
+MI Store 12
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 425
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+ memory_total_requests: 522
+ memory_reads: 441
+ memory_writes: 81
+ memory_refreshes: 171
+ memory_total_request_delays: 124
+ memory_delays_per_request: 0.237548
+ memory_delays_in_input_queue: 2
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 122
+ memory_stalls_for_bank_busy: 45
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 8
+ memory_stalls_for_bus: 23
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 46
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 106
+GETS 464
+PUT 425
+Unblock 440
+Writeback_Clean 0
+Writeback_Dirty 0
+Writeback_Exclusive_Clean 344
+Writeback_Exclusive_Dirty 81
+DMA_READ 0
+DMA_WRITE 0
+Memory_Data 441
+Memory_Ack 81
+Ack 0
+Shared_Ack 0
+Shared_Data 0
+Exclusive_Data 0
+All_acks_and_data 0
+All_acks_and_data_no_sharers 0
+
+ - Transitions -
+NO GETX 0 <--
+NO GETS 0 <--
+NO PUT 425
+NO DMA_READ 0 <--
+NO DMA_WRITE 0 <--
+
+O GETX 0 <--
+O GETS 0 <--
+O PUT 0 <--
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+
+E GETX 47
+E GETS 394
+E PUT 0 <--
+E DMA_READ 0 <--
+E DMA_WRITE 0 <--
+
+NO_B GETX 0 <--
+NO_B GETS 0 <--
+NO_B PUT 0 <--
+NO_B Unblock 440
+NO_B DMA_READ 0 <--
+NO_B DMA_WRITE 0 <--
+
+O_B GETX 0 <--
+O_B GETS 0 <--
+O_B PUT 0 <--
+O_B Unblock 0 <--
+O_B DMA_READ 0 <--
+O_B DMA_WRITE 0 <--
+
+NO_B_W GETX 0 <--
+NO_B_W GETS 0 <--
+NO_B_W PUT 0 <--
+NO_B_W Unblock 0 <--
+NO_B_W DMA_READ 0 <--
+NO_B_W DMA_WRITE 0 <--
+NO_B_W Memory_Data 441
+
+O_B_W GETX 0 <--
+O_B_W GETS 0 <--
+O_B_W PUT 0 <--
+O_B_W Unblock 0 <--
+O_B_W DMA_READ 0 <--
+O_B_W DMA_WRITE 0 <--
+O_B_W Memory_Data 0 <--
+
+NO_W GETX 0 <--
+NO_W GETS 0 <--
+NO_W PUT 0 <--
+NO_W DMA_READ 0 <--
+NO_W DMA_WRITE 0 <--
+NO_W Memory_Data 0 <--
+
+O_W GETX 0 <--
+O_W GETS 0 <--
+O_W PUT 0 <--
+O_W DMA_READ 0 <--
+O_W DMA_WRITE 0 <--
+O_W Memory_Data 0 <--
+
+NO_DW_B_W GETX 0 <--
+NO_DW_B_W GETS 0 <--
+NO_DW_B_W PUT 0 <--
+NO_DW_B_W DMA_READ 0 <--
+NO_DW_B_W DMA_WRITE 0 <--
+NO_DW_B_W Ack 0 <--
+NO_DW_B_W Exclusive_Data 0 <--
+NO_DW_B_W All_acks_and_data_no_sharers 0 <--
+
+NO_DR_B_W GETX 0 <--
+NO_DR_B_W GETS 0 <--
+NO_DR_B_W PUT 0 <--
+NO_DR_B_W DMA_READ 0 <--
+NO_DR_B_W DMA_WRITE 0 <--
+NO_DR_B_W Memory_Data 0 <--
+NO_DR_B_W Ack 0 <--
+NO_DR_B_W Shared_Ack 0 <--
+NO_DR_B_W Shared_Data 0 <--
+NO_DR_B_W Exclusive_Data 0 <--
+
+NO_DR_B_D GETX 0 <--
+NO_DR_B_D GETS 0 <--
+NO_DR_B_D PUT 0 <--
+NO_DR_B_D DMA_READ 0 <--
+NO_DR_B_D DMA_WRITE 0 <--
+NO_DR_B_D Ack 0 <--
+NO_DR_B_D Shared_Ack 0 <--
+NO_DR_B_D Shared_Data 0 <--
+NO_DR_B_D Exclusive_Data 0 <--
+NO_DR_B_D All_acks_and_data 0 <--
+NO_DR_B_D All_acks_and_data_no_sharers 0 <--
+
+NO_DR_B GETX 0 <--
+NO_DR_B GETS 0 <--
+NO_DR_B PUT 0 <--
+NO_DR_B DMA_READ 0 <--
+NO_DR_B DMA_WRITE 0 <--
+NO_DR_B Ack 0 <--
+NO_DR_B Shared_Ack 0 <--
+NO_DR_B Shared_Data 0 <--
+NO_DR_B Exclusive_Data 0 <--
+NO_DR_B All_acks_and_data 0 <--
+NO_DR_B All_acks_and_data_no_sharers 0 <--
+
+NO_DW_W GETX 0 <--
+NO_DW_W GETS 0 <--
+NO_DW_W PUT 0 <--
+NO_DW_W DMA_READ 0 <--
+NO_DW_W DMA_WRITE 0 <--
+NO_DW_W Memory_Ack 0 <--
+
+O_DR_B_W GETX 0 <--
+O_DR_B_W GETS 0 <--
+O_DR_B_W PUT 0 <--
+O_DR_B_W DMA_READ 0 <--
+O_DR_B_W DMA_WRITE 0 <--
+O_DR_B_W Memory_Data 0 <--
+
+O_DR_B GETX 0 <--
+O_DR_B GETS 0 <--
+O_DR_B PUT 0 <--
+O_DR_B DMA_READ 0 <--
+O_DR_B DMA_WRITE 0 <--
+O_DR_B Ack 0 <--
+O_DR_B All_acks_and_data_no_sharers 0 <--
+
+WB GETX 4
+WB GETS 15
+WB PUT 0 <--
+WB Unblock 0 <--
+WB Writeback_Clean 0 <--
+WB Writeback_Dirty 0 <--
+WB Writeback_Exclusive_Clean 344
+WB Writeback_Exclusive_Dirty 81
+WB DMA_READ 0 <--
+WB DMA_WRITE 0 <--
+
+WB_O_W GETX 0 <--
+WB_O_W GETS 0 <--
+WB_O_W PUT 0 <--
+WB_O_W DMA_READ 0 <--
+WB_O_W DMA_WRITE 0 <--
+WB_O_W Memory_Ack 0 <--
+
+WB_E_W GETX 55
+WB_E_W GETS 55
+WB_E_W PUT 0 <--
+WB_E_W DMA_READ 0 <--
+WB_E_W DMA_WRITE 0 <--
+WB_E_W Memory_Ack 81
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 11:30:01
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 11:48:25
+M5 executing on svvint06
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 81672 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 32212 # Simulator instruction rate (inst/s)
+host_mem_usage 212236 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 1020887 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_insts 2577 # Number of instructions simulated
+sim_seconds 0.000082 # Number of seconds simulated
+sim_ticks 81672 # Number of ticks simulated
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 419 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 415 # DTB read hits
+system.cpu.dtb.read_misses 4 # DTB read misses
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 294 # DTB write hits
+system.cpu.dtb.write_misses 4 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 2586 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 81672 # number of cpu cycles simulated
+system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.num_refs 717 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
[system]
type=System
-children=cpu membus physmem
-mem_mode=atomic
+children=cpu physmem ruby
+mem_mode=timing
physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dtb itb tracer workload
checker=Null
-clock=500
+clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
system=system
uid=100
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
+type=PhysicalMemory
file=
-latency=30000
+latency=30
latency_var=0
null=false
-num_cpus=1
-phase=0
range=0:134217727
-stats_file=ruby.stats
zero=false
-port=system.membus.port[0]
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
================ Begin RubySystem Configuration Print ================
RubySystem config:
- random_seed: 752800
+ random_seed: 1234
randomization: 0
- tech_nm: 45
- freq_mhz: 3000
+ cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
- memory_size_bytes: 1073741824
- memory_size_bits: 30
-DMA_Controller config: DMAController_0
- version: 0
- buffer_size: 32
- dma_sequencer: DMASequencer_0
- number_of_TBEs: 128
- transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
- version: 0
- buffer_size: 32
- directory_latency: 6
- directory_name: DirectoryMemory_0
- memory_controller_name: MemoryControl_0
- memory_latency: 158
- number_of_TBEs: 128
- recycle_latency: 10
- to_mem_ctrl_latency: 1
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
- version: 0
- buffer_size: 32
- cache: l1u_0
- cache_response_latency: 12
- issue_latency: 2
- number_of_TBEs: 128
- sequencer: Sequencer_0
- transitions_per_cycle: 32
-Cache config: l1u_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 2
- num_cache_sets: 4
- cache_set_size_bytes: 256
- cache_set_size_Kbytes: 0.25
- cache_set_size_Mbytes: 0.000244141
- cache_size_bytes: 2048
- cache_size_Kbytes: 2
- cache_size_Mbytes: 0.00195312
-DirectoryMemory Global Config:
- number of directory memories: 1
- total memory size bytes: 1073741824
- total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
- controller: DirectoryController_0
- version: 0
- memory_bits: 30
- memory_size_bytes: 1073741824
- memory_size_Kbytes: 1.04858e+06
- memory_size_Mbytes: 1024
- memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
- controller: L1CacheController_0
- version: 0
- max_outstanding_requests: 16
- deadlock_threshold: 500000
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: theTopology
+topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
- L1Cache-0 -> Directory-0 net_lat: 7
- L1Cache-0 -> DMA-0 net_lat: 7
-
-Directory-0 Network Latencies
- Directory-0 -> L1Cache-0 net_lat: 7
- Directory-0 -> DMA-0 net_lat: 7
-
-DMA-0 Network Latencies
- DMA-0 -> L1Cache-0 net_lat: 7
- DMA-0 -> Directory-0 net_lat: 7
-
---- End Topology Print ---
Profiler Configuration
----------------------
================ End RubySystem Configuration Print ================
-Real time: Jul/06/2009 11:11:07
+Real time: Jan/28/2010 10:26:06
Profiler Stats
--------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.44
-Virtual_time_in_minutes: 0.00733333
-Virtual_time_in_hours: 0.000122222
-Virtual_time_in_days: 0.000122222
+Virtual_time_in_seconds: 0.25
+Virtual_time_in_minutes: 0.00416667
+Virtual_time_in_hours: 6.94444e-05
+Virtual_time_in_days: 2.89352e-06
-Ruby_current_time: 9880001
-Ruby_start_time: 1
-Ruby_cycles: 9880000
+Ruby_current_time: 123378
+Ruby_start_time: 0
+Ruby_cycles: 123378
-mbytes_resident: 143.812
-mbytes_total: 1328.75
-resident_ratio: 0.108234
+mbytes_resident: 32.8828
+mbytes_total: 32.8906
+resident_ratio: 1
Total_misses: 0
total_misses: 0 [ 0 ]
user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
-instruction_executed: 1 [ 1 ]
-ruby_cycles_executed: 9880001 [ 9880001 ]
-cycles_per_instruction: 9.88e+06 [ 9.88e+06 ]
-misses_per_thousand_instructions: 0 [ 0 ]
+ruby_cycles_executed: 123379 [ 123379 ]
transactions_started: 0 [ 0 ]
transactions_ended: 0 [ 0 ]
-instructions_per_transaction: 0 [ 0 ]
cycles_per_transaction: 0 [ 0 ]
misses_per_transaction: 0 [ 0 ]
-L1D_cache cache stats:
- L1D_cache_total_misses: 0
- L1D_cache_total_demand_misses: 0
- L1D_cache_total_prefetches: 0
- L1D_cache_total_sw_prefetches: 0
- L1D_cache_total_hw_prefetches: 0
- L1D_cache_misses_per_transaction: 0
- L1D_cache_misses_per_instruction: 0
- L1D_cache_instructions_per_misses: NaN
-
- L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats:
- L1I_cache_total_misses: 0
- L1I_cache_total_demand_misses: 0
- L1I_cache_total_prefetches: 0
- L1I_cache_total_sw_prefetches: 0
- L1I_cache_total_hw_prefetches: 0
- L1I_cache_misses_per_transaction: 0
- L1I_cache_misses_per_instruction: 0
- L1I_cache_instructions_per_misses: NaN
-
- L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats:
- L2_cache_total_misses: 0
- L2_cache_total_demand_misses: 0
- L2_cache_total_prefetches: 0
- L2_cache_total_sw_prefetches: 0
- L2_cache_total_hw_prefetches: 0
- L2_cache_misses_per_transaction: 0
- L2_cache_misses_per_instruction: 0
- L2_cache_instructions_per_misses: NaN
-
- L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Memory control:
- memory_total_requests: 658
- memory_reads: 345
- memory_writes: 313
- memory_refreshes: 6486
- memory_total_request_delays: 795
- memory_delays_per_request: 1.20821
- memory_delays_in_input_queue: 313
- memory_delays_behind_head_of_bank_queue: 1
- memory_delays_stalled_at_head_of_bank_queue: 481
- memory_stalls_for_bank_busy: 108
- memory_stalls_for_random_busy: 0
- memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 30
- memory_stalls_for_bus: 335
- memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 8
- memory_stalls_for_read_read_turnaround: 0
- accesses_per_bank: 29 14 0 38 34 30 44 23 10 6 5 8 28 46 21 6 8 7 10 16 20 17 20 51 22 10 10 22 18 28 15 42
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
-DMA-0:0
+
Busy Bank Count:0
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 1 count: 658 average: 0.475684 | standard deviation: 0.50114 | 345 313 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3294 average: 1 | standard deviation: 0 | 0 3294 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 280 count: 3294 average: 19.8021 | standard deviation: 52.3549 | 0 2949 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 0 0 0 0 4 0 0 0 0 283 0 0 0 0 7 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 7 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 280 count: 2585 average: 15.4932 | standard deviation: 46.2081 | 0 2380 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 3 0 0 0 0 169 0 0 0 0 6 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 270 count: 415 average: 44.4916 | standard deviation: 74.7872 | 0 312 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 86 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 1 max: 190 count: 294 average: 22.8367 | standard deviation: 55.1047 | 0 0 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_2: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
Request vs. RubySystem State Profile
--------------------------------
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 658 average: 0 | standard deviation: 0 | 658 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 658 average: 0 | standard deviation: 0 | 658 ]
+Total_delay_cycles: [binsize: 1 max: 0 count: 1248 average: 0 | standard deviation: 0 | 1248 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1248 average: 0 | standard deviation: 0 | 1248 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 345 average: 0 | standard deviation: 0 | 345 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 313 average: 0 | standard deviation: 0 | 313 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 626 average: 0 | standard deviation: 0 | 626 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 622 average: 0 | standard deviation: 0 | 622 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 37575
-page_faults: 0
+page_reclaims: 7118
+page_faults: 2103
swaps: 0
-block_inputs: 8
-block_outputs: 48
+block_inputs: 0
+block_outputs: 0
Network Stats
-------------
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.000208122
- links_utilized_percent_switch_0_link_0: 8.3249e-05 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.000332996 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.157808
+ links_utilized_percent_switch_0_link_0: 0.0633825 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.252233 bw: 160000 base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 345 2760 [ 0 345 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Writeback_Control: 313 2504 [ 0 0 313 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Control: 345 2760 [ 345 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Data: 313 2504 [ 313 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.000208122
- links_utilized_percent_switch_1_link_0: 8.3249e-05 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.000332996 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.158294
+ links_utilized_percent_switch_1_link_0: 0.0630582 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.25353 bw: 160000 base_latency: 1
- outgoing_messages_switch_1_link_0_Control: 345 2760 [ 345 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Data: 313 2504 [ 313 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Data: 345 2760 [ 0 345 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 313 2504 [ 0 0 313 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_3_inlinks: 3
-switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0.000221997
- links_utilized_percent_switch_3_link_0: 0.000332996 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0.000332996 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_3_link_0_Response_Data: 345 2760 [ 0 345 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Writeback_Control: 313 2504 [ 0 0 313 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Control: 345 2760 [ 345 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Data: 313 2504 [ 313 0 0 0 0 0 ] base_latency: 1
-
- --- DMA ---
+links_utilized_percent_switch_2: 0.252881
+ links_utilized_percent_switch_2_link_0: 0.25353 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.252233 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 626
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 626
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 39.1374%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.4185%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 47.4441%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 626 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 626 average: 5.71885 | standard deviation: 1.98192 | 0 0 0 0 357 0 0 0 269 ]
+
+ --- L1Cache 0 ---
- Event Counts -
-ReadRequest 0
-WriteRequest 0
-Data 0
-Ack 0
+Load 415
+Ifetch 2585
+Store 294
+Data 626
+Fwd_GETX 0
+Inv 0
+Replacement 622
+Writeback_Ack 622
+Writeback_Nack 0
- Transitions -
-READY ReadRequest 0 <--
-READY WriteRequest 0 <--
+I Load 245
+I Ifetch 297
+I Store 84
+I Inv 0 <--
+I Replacement 0 <--
-BUSY_RD Data 0 <--
+II Writeback_Nack 0 <--
-BUSY_WR Ack 0 <--
+M Load 170
+M Ifetch 2288
+M Store 210
+M Fwd_GETX 0 <--
+M Inv 0 <--
+M Replacement 622
+
+MI Fwd_GETX 0 <--
+MI Inv 0 <--
+MI Writeback_Ack 622
+MI Writeback_Nack 0 <--
+
+MII Fwd_GETX 0 <--
+
+IS Data 542
+
+IM Data 84
+
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+ memory_total_requests: 1248
+ memory_reads: 626
+ memory_writes: 622
+ memory_refreshes: 258
+ memory_total_request_delays: 1710
+ memory_delays_per_request: 1.37019
+ memory_delays_in_input_queue: 622
+ memory_delays_behind_head_of_bank_queue: 3
+ memory_delays_stalled_at_head_of_bank_queue: 1085
+ memory_stalls_for_bank_busy: 404
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 39
+ memory_stalls_for_bus: 620
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 22
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138
- --- Directory ---
+ --- Directory 0 ---
- Event Counts -
-GETX 345
+GETX 626
GETS 0
-PUTX 313
+PUTX 622
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
-Memory_Data 345
-Memory_Ack 313
+Memory_Data 626
+Memory_Ack 622
- Transitions -
-I GETX 345
+I GETX 626
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
M GETX 0 <--
-M PUTX 313
+M PUTX 622
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
+M_DWRI GETX 0 <--
M_DWRI Memory_Ack 0 <--
+M_DRDI GETX 0 <--
+M_DRDI Memory_Ack 0 <--
+
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
-IM Memory_Data 345
+IM Memory_Data 626
MI GETX 0 <--
MI GETS 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
-MI Memory_Ack 313
+MI Memory_Ack 622
ID GETX 0 <--
ID GETS 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
- --- L1Cache ---
- - Event Counts -
-Load 415
-Ifetch 2585
-Store 294
-Data 345
-Fwd_GETX 0
-Inv 0
-Replacement 313
-Writeback_Ack 313
-Writeback_Nack 0
-
- - Transitions -
-I Load 103
-I Ifetch 205
-I Store 37
-I Inv 0 <--
-I Replacement 0 <--
-
-II Writeback_Nack 0 <--
-
-M Load 312
-M Ifetch 2380
-M Store 257
-M Fwd_GETX 0 <--
-M Inv 0 <--
-M Replacement 313
-
-MI Fwd_GETX 0 <--
-MI Inv 0 <--
-MI Writeback_Ack 313
-
-IS Data 308
-
-IM Data 37
-
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
-print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:06
-M5 executing on maize
+M5 compiled Jan 27 2010 22:23:20
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 10:26:06
+M5 executing on svvint07
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
-Global frequency set at 1000000000000 ticks per second
- Debug: Adding to filter: 'q' (Queue)
+Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 9880000 because target called exit()
+Exiting @ tick 123378 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 7760 # Simulator instruction rate (inst/s)
-host_mem_usage 1360644 # Number of bytes of host memory used
-host_seconds 0.33 # Real time elapsed on the host
-host_tick_rate 29737002 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 51538 # Simulator instruction rate (inst/s)
+host_mem_usage 214632 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
+host_tick_rate 2467461 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
-sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 9880000 # Number of ticks simulated
+sim_seconds 0.000123 # Number of seconds simulated
+sim_ticks 123378 # Number of ticks simulated
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 19760 # number of cpu cycles simulated
+system.cpu.numCycles 123378 # number of cpu cycles simulated
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+++ /dev/null
-[root]
-type=Root
-children=system
-dummy=0
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-CP0_Config=0
-CP0_Config1=0
-CP0_Config1_C2=false
-CP0_Config1_CA=false
-CP0_Config1_DA=0
-CP0_Config1_DL=0
-CP0_Config1_DS=0
-CP0_Config1_EP=false
-CP0_Config1_FP=false
-CP0_Config1_IA=0
-CP0_Config1_IL=0
-CP0_Config1_IS=0
-CP0_Config1_M=0
-CP0_Config1_MD=false
-CP0_Config1_MMU=0
-CP0_Config1_PC=false
-CP0_Config1_WR=false
-CP0_Config2=0
-CP0_Config2_M=false
-CP0_Config2_SA=0
-CP0_Config2_SL=0
-CP0_Config2_SS=0
-CP0_Config2_SU=0
-CP0_Config2_TA=0
-CP0_Config2_TL=0
-CP0_Config2_TS=0
-CP0_Config2_TU=0
-CP0_Config3=0
-CP0_Config3_DSPP=false
-CP0_Config3_LPA=false
-CP0_Config3_M=false
-CP0_Config3_MT=false
-CP0_Config3_SM=false
-CP0_Config3_SP=false
-CP0_Config3_TL=false
-CP0_Config3_VEIC=false
-CP0_Config3_VInt=false
-CP0_Config_AR=0
-CP0_Config_AT=0
-CP0_Config_BE=0
-CP0_Config_MT=0
-CP0_Config_VI=0
-CP0_EBase_CPUNum=0
-CP0_IntCtl_IPPCI=0
-CP0_IntCtl_IPTI=0
-CP0_PRId=0
-CP0_PRId_CompanyID=0
-CP0_PRId_CompanyOptions=0
-CP0_PRId_ProcessorID=1
-CP0_PRId_Revision=0
-CP0_PerfCtr_M=false
-CP0_PerfCtr_W=false
-CP0_SrsCtl_HSS=0
-CP0_WatchHi_M=false
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.dtb]
-type=MipsTLB
-size=64
-
-[system.cpu.itb]
-type=MipsTLB
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
-file=
-latency=30000
-latency_var=0
-null=false
-num_cpus=1
-num_dmas=1
-phase=0
-ports_per_core=2
-range=0:1073741823
-stats_file=ruby.stats
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024", "-C", "32768", "-A", "8", "-D", "1"]
-print config: 1
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-hack: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jan 2 2010 07:01:31
-M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch
-M5 started Jan 2 2010 07:03:09
-M5 executing on fajita
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic-ruby
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Hello World!
-Exiting @ tick 2913500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 57498 # Simulator instruction rate (inst/s)
-host_mem_usage 2303472 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
-host_tick_rate 28699061 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5827 # Number of instructions simulated
-sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 2913500 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5828 # number of cpu cycles simulated
-system.cpu.num_insts 5827 # Number of instructions executed
-system.cpu.num_refs 2090 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
-
----------- End Simulation Statistics ----------
[system]
type=System
-children=cpu membus physmem
+children=cpu physmem ruby
mem_mode=atomic
physmem=system.physmem
CP0_SrsCtl_HSS=0
CP0_WatchHi_M=false
checker=Null
-clock=500
+clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
[system.cpu.dtb]
type=MipsTLB
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
system=system
uid=100
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
+type=PhysicalMemory
file=
-latency=30000
+latency=30
latency_var=0
null=false
-num_cpus=1
-num_dmas=1
-phase=0
-ports_per_core=2
-range=0:1073741823
-stats_file=ruby.stats
+range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tech_nm=45
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024", "-C", "32768", "-A", "8", "-D", "1"]
-print config: 1
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Jan 2 2010 07:01:31
-M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch
-M5 started Jan 2 2010 07:03:09
-M5 executing on fajita
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby
-Global frequency set at 1000000000000 ticks per second
+M5 compiled Jan 21 2010 11:12:15
+M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
+M5 started Jan 21 2010 11:12:51
+M5 executing on svvint07
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
+Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 23749000 because target called exit()
+Exiting @ tick 292960 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 6560 # Simulator instruction rate (inst/s)
-host_mem_usage 2303716 # Number of bytes of host memory used
-host_seconds 0.89 # Real time elapsed on the host
-host_tick_rate 26729951 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 24278 # Simulator instruction rate (inst/s)
+host_mem_usage 347460 # Number of bytes of host memory used
+host_seconds 0.24 # Real time elapsed on the host
+host_tick_rate 1220626 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
-sim_seconds 0.000024 # Number of seconds simulated
-sim_ticks 23749000 # Number of ticks simulated
+sim_seconds 0.000293 # Number of seconds simulated
+sim_ticks 292960 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 47498 # number of cpu cycles simulated
+system.cpu.numCycles 292960 # number of cpu cycles simulated
system.cpu.num_insts 5827 # Number of instructions executed
system.cpu.num_refs 2090 # Number of memory references
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
+++ /dev/null
-[root]
-type=Root
-children=system
-dummy=0
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu.itb]
-type=SparcTLB
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
-file=
-latency=30000
-latency_var=0
-null=false
-num_cpus=1
-phase=0
-range=0:134217727
-stats_file=ruby.stats
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-
-================ Begin RubySystem Configuration Print ================
-
-RubySystem config:
- random_seed: 539659
- randomization: 0
- tech_nm: 45
- freq_mhz: 3000
- block_size_bytes: 64
- block_size_bits: 6
- memory_size_bytes: 1073741824
- memory_size_bits: 30
-DMA_Controller config: DMAController_0
- version: 0
- buffer_size: 32
- dma_sequencer: DMASequencer_0
- number_of_TBEs: 128
- transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
- version: 0
- buffer_size: 32
- directory_latency: 6
- directory_name: DirectoryMemory_0
- memory_controller_name: MemoryControl_0
- memory_latency: 158
- number_of_TBEs: 128
- recycle_latency: 10
- to_mem_ctrl_latency: 1
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
- version: 0
- buffer_size: 32
- cache: l1u_0
- cache_response_latency: 12
- issue_latency: 2
- number_of_TBEs: 128
- sequencer: Sequencer_0
- transitions_per_cycle: 32
-Cache config: l1u_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 2
- num_cache_sets: 4
- cache_set_size_bytes: 256
- cache_set_size_Kbytes: 0.25
- cache_set_size_Mbytes: 0.000244141
- cache_size_bytes: 2048
- cache_size_Kbytes: 2
- cache_size_Mbytes: 0.00195312
-DirectoryMemory Global Config:
- number of directory memories: 1
- total memory size bytes: 1073741824
- total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
- controller: DirectoryController_0
- version: 0
- memory_bits: 30
- memory_size_bytes: 1073741824
- memory_size_Kbytes: 1.04858e+06
- memory_size_Mbytes: 1024
- memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
- controller: L1CacheController_0
- version: 0
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-
-Network Configuration
----------------------
-network: SIMPLE_NETWORK
-topology: theTopology
-
-virtual_net_0: active, ordered
-virtual_net_1: active, ordered
-virtual_net_2: active, ordered
-virtual_net_3: inactive
-virtual_net_4: active, ordered
-virtual_net_5: active, ordered
-
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
- L1Cache-0 -> Directory-0 net_lat: 7
- L1Cache-0 -> DMA-0 net_lat: 7
-
-Directory-0 Network Latencies
- Directory-0 -> L1Cache-0 net_lat: 7
- Directory-0 -> DMA-0 net_lat: 7
-
-DMA-0 Network Latencies
- DMA-0 -> L1Cache-0 net_lat: 7
- DMA-0 -> Directory-0 net_lat: 7
-
---- End Topology Print ---
-
-Profiler Configuration
-----------------------
-periodic_stats_period: 1000000
-
-================ End RubySystem Configuration Print ================
-
-
-Real time: Jul/06/2009 11:11:24
-
-Profiler Stats
---------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
-
-Virtual_time_in_seconds: 0.23
-Virtual_time_in_minutes: 0.00383333
-Virtual_time_in_hours: 6.38889e-05
-Virtual_time_in_days: 6.38889e-05
-
-Ruby_current_time: 2701001
-Ruby_start_time: 1
-Ruby_cycles: 2701000
-
-mbytes_resident: 144.91
-mbytes_total: 1330.19
-resident_ratio: 0.108942
-
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-instruction_executed: 1 [ 1 ]
-ruby_cycles_executed: 2701001 [ 2701001 ]
-cycles_per_instruction: 2.701e+06 [ 2.701e+06 ]
-misses_per_thousand_instructions: 0 [ 0 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-instructions_per_transaction: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
-L1D_cache cache stats:
- L1D_cache_total_misses: 0
- L1D_cache_total_demand_misses: 0
- L1D_cache_total_prefetches: 0
- L1D_cache_total_sw_prefetches: 0
- L1D_cache_total_hw_prefetches: 0
- L1D_cache_misses_per_transaction: 0
- L1D_cache_misses_per_instruction: 0
- L1D_cache_instructions_per_misses: NaN
-
- L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats:
- L1I_cache_total_misses: 0
- L1I_cache_total_demand_misses: 0
- L1I_cache_total_prefetches: 0
- L1I_cache_total_sw_prefetches: 0
- L1I_cache_total_hw_prefetches: 0
- L1I_cache_misses_per_transaction: 0
- L1I_cache_misses_per_instruction: 0
- L1I_cache_instructions_per_misses: NaN
-
- L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats:
- L2_cache_total_misses: 0
- L2_cache_total_demand_misses: 0
- L2_cache_total_prefetches: 0
- L2_cache_total_sw_prefetches: 0
- L2_cache_total_hw_prefetches: 0
- L2_cache_misses_per_transaction: 0
- L2_cache_misses_per_instruction: 0
- L2_cache_instructions_per_misses: NaN
-
- L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Busy Controller Counts:
-L1Cache-0:0
-Directory-0:0
-DMA-0:0
-
-Busy Bank Count:0
-
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle SW Prefetch Requests
-------------------------------------
-prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Resource Usage
---------------
-page_size: 4096
-user_time: 0
-system_time: 0
-page_reclaims: 37843
-page_faults: 0
-swaps: 0
-block_inputs: 0
-block_outputs: 40
-
-Network Stats
--------------
-
-switch_0_inlinks: 2
-switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0
- links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_1_inlinks: 2
-switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0
- links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_2_inlinks: 2
-switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_3_inlinks: 3
-switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0
- links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
-
-
- --- DMA ---
- - Event Counts -
-ReadRequest 0
-WriteRequest 0
-Data 0
-Ack 0
-
- - Transitions -
-READY ReadRequest 0 <--
-READY WriteRequest 0 <--
-
-BUSY_RD Data 0 <--
-
-BUSY_WR Ack 0 <--
-
- --- Directory ---
- - Event Counts -
-GETX 0
-GETS 0
-PUTX 0
-PUTX_NotOwner 0
-DMA_READ 0
-DMA_WRITE 0
-Memory_Data 0
-Memory_Ack 0
-
- - Transitions -
-I GETX 0 <--
-I PUTX_NotOwner 0 <--
-I DMA_READ 0 <--
-I DMA_WRITE 0 <--
-
-M GETX 0 <--
-M PUTX 0 <--
-M PUTX_NotOwner 0 <--
-M DMA_READ 0 <--
-M DMA_WRITE 0 <--
-
-M_DRD GETX 0 <--
-M_DRD PUTX 0 <--
-
-M_DWR GETX 0 <--
-M_DWR PUTX 0 <--
-
-M_DWRI Memory_Ack 0 <--
-
-IM GETX 0 <--
-IM GETS 0 <--
-IM PUTX 0 <--
-IM PUTX_NotOwner 0 <--
-IM DMA_READ 0 <--
-IM DMA_WRITE 0 <--
-IM Memory_Data 0 <--
-
-MI GETX 0 <--
-MI GETS 0 <--
-MI PUTX 0 <--
-MI PUTX_NotOwner 0 <--
-MI DMA_READ 0 <--
-MI DMA_WRITE 0 <--
-MI Memory_Ack 0 <--
-
-ID GETX 0 <--
-ID GETS 0 <--
-ID PUTX 0 <--
-ID PUTX_NotOwner 0 <--
-ID DMA_READ 0 <--
-ID DMA_WRITE 0 <--
-ID Memory_Data 0 <--
-
-ID_W GETX 0 <--
-ID_W GETS 0 <--
-ID_W PUTX 0 <--
-ID_W PUTX_NotOwner 0 <--
-ID_W DMA_READ 0 <--
-ID_W DMA_WRITE 0 <--
-ID_W Memory_Ack 0 <--
-
- --- L1Cache ---
- - Event Counts -
-Load 0
-Ifetch 0
-Store 0
-Data 0
-Fwd_GETX 0
-Inv 0
-Replacement 0
-Writeback_Ack 0
-Writeback_Nack 0
-
- - Transitions -
-I Load 0 <--
-I Ifetch 0 <--
-I Store 0 <--
-I Inv 0 <--
-I Replacement 0 <--
-
-II Writeback_Nack 0 <--
-
-M Load 0 <--
-M Ifetch 0 <--
-M Store 0 <--
-M Fwd_GETX 0 <--
-M Inv 0 <--
-M Replacement 0 <--
-
-MI Fwd_GETX 0 <--
-MI Inv 0 <--
-MI Writeback_Ack 0 <--
-
-IS Data 0 <--
-
-IM Data 0 <--
-
+++ /dev/null
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
-print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-hack: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jul 6 2009 11:07:18
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:24
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby
-Global frequency set at 1000000000000 ticks per second
- Debug: Adding to filter: 'q' (Queue)
-info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 2701000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 49084 # Simulator instruction rate (inst/s)
-host_mem_usage 201040 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
-host_tick_rate 24773225 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5340 # Number of instructions simulated
-sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 2701000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5403 # number of cpu cycles simulated
-system.cpu.num_insts 5340 # Number of instructions executed
-system.cpu.num_refs 1402 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
-
----------- End Simulation Statistics ----------
[system]
type=System
-children=cpu membus physmem
+children=cpu physmem ruby
mem_mode=atomic
physmem=system.physmem
type=TimingSimpleCPU
children=dtb itb tracer workload
checker=Null
-clock=500
+clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
[system.cpu.dtb]
type=SparcTLB
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
system=system
uid=100
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
+type=PhysicalMemory
file=
-latency=30000
+latency=30
latency_var=0
null=false
-num_cpus=1
-phase=0
range=0:134217727
-stats_file=ruby.stats
zero=false
-port=system.membus.port[0]
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tech_nm=45
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
================ Begin RubySystem Configuration Print ================
RubySystem config:
- random_seed: 229628
+ random_seed: 1234
randomization: 0
tech_nm: 45
- freq_mhz: 3000
+ cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
- memory_size_bytes: 1073741824
- memory_size_bits: 30
-DMA_Controller config: DMAController_0
- version: 0
- buffer_size: 32
- dma_sequencer: DMASequencer_0
- number_of_TBEs: 128
- transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
- version: 0
- buffer_size: 32
- directory_latency: 6
- directory_name: DirectoryMemory_0
- memory_controller_name: MemoryControl_0
- memory_latency: 158
- number_of_TBEs: 128
- recycle_latency: 10
- to_mem_ctrl_latency: 1
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
- version: 0
- buffer_size: 32
- cache: l1u_0
- cache_response_latency: 12
- issue_latency: 2
- number_of_TBEs: 128
- sequencer: Sequencer_0
- transitions_per_cycle: 32
-Cache config: l1u_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 2
- num_cache_sets: 4
- cache_set_size_bytes: 256
- cache_set_size_Kbytes: 0.25
- cache_set_size_Mbytes: 0.000244141
- cache_size_bytes: 2048
- cache_size_Kbytes: 2
- cache_size_Mbytes: 0.00195312
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
DirectoryMemory Global Config:
number of directory memories: 1
- total memory size bytes: 1073741824
- total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
- controller: DirectoryController_0
- version: 0
- memory_bits: 30
- memory_size_bytes: 1073741824
- memory_size_Kbytes: 1.04858e+06
- memory_size_Mbytes: 1024
- memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
- controller: L1CacheController_0
- version: 0
- max_outstanding_requests: 16
- deadlock_threshold: 500000
+ total memory size bytes: 134217728
+ total memory size bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: theTopology
+topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
- L1Cache-0 -> Directory-0 net_lat: 7
- L1Cache-0 -> DMA-0 net_lat: 7
-
-Directory-0 Network Latencies
- Directory-0 -> L1Cache-0 net_lat: 7
- Directory-0 -> DMA-0 net_lat: 7
-
-DMA-0 Network Latencies
- DMA-0 -> L1Cache-0 net_lat: 7
- DMA-0 -> Directory-0 net_lat: 7
-
---- End Topology Print ---
Profiler Configuration
----------------------
================ End RubySystem Configuration Print ================
-Real time: Jul/06/2009 11:11:36
+Real time: Jan/21/2010 11:30:49
Profiler Stats
--------------
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.71
-Virtual_time_in_minutes: 0.0118333
-Virtual_time_in_hours: 0.000197222
-Virtual_time_in_days: 0.000197222
+Virtual_time_in_seconds: 0.28
+Virtual_time_in_minutes: 0.00466667
+Virtual_time_in_hours: 7.77778e-05
+Virtual_time_in_days: 3.24074e-06
-Ruby_current_time: 20314001
-Ruby_start_time: 1
-Ruby_cycles: 20314000
+Ruby_current_time: 253364
+Ruby_start_time: 0
+Ruby_cycles: 253364
-mbytes_resident: 145.32
-mbytes_total: 1330.48
-resident_ratio: 0.109227
+mbytes_resident: 34.3555
+mbytes_total: 34.5312
+resident_ratio: 0.995136
Total_misses: 0
total_misses: 0 [ 0 ]
user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
-instruction_executed: 1 [ 1 ]
-ruby_cycles_executed: 20314001 [ 20314001 ]
-cycles_per_instruction: 2.0314e+07 [ 2.0314e+07 ]
-misses_per_thousand_instructions: 0 [ 0 ]
+ruby_cycles_executed: 253365 [ 253365 ]
transactions_started: 0 [ 0 ]
transactions_ended: 0 [ 0 ]
-instructions_per_transaction: 0 [ 0 ]
cycles_per_transaction: 0 [ 0 ]
misses_per_transaction: 0 [ 0 ]
-L1D_cache cache stats:
- L1D_cache_total_misses: 0
- L1D_cache_total_demand_misses: 0
- L1D_cache_total_prefetches: 0
- L1D_cache_total_sw_prefetches: 0
- L1D_cache_total_hw_prefetches: 0
- L1D_cache_misses_per_transaction: 0
- L1D_cache_misses_per_instruction: 0
- L1D_cache_instructions_per_misses: NaN
-
- L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats:
- L1I_cache_total_misses: 0
- L1I_cache_total_demand_misses: 0
- L1I_cache_total_prefetches: 0
- L1I_cache_total_sw_prefetches: 0
- L1I_cache_total_hw_prefetches: 0
- L1I_cache_misses_per_transaction: 0
- L1I_cache_misses_per_instruction: 0
- L1I_cache_instructions_per_misses: NaN
-
- L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats:
- L2_cache_total_misses: 0
- L2_cache_total_demand_misses: 0
- L2_cache_total_prefetches: 0
- L2_cache_total_sw_prefetches: 0
- L2_cache_total_hw_prefetches: 0
- L2_cache_misses_per_transaction: 0
- L2_cache_misses_per_instruction: 0
- L2_cache_instructions_per_misses: NaN
-
- L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Memory control:
- memory_total_requests: 1262
- memory_reads: 647
- memory_writes: 615
- memory_refreshes: 12114
- memory_total_request_delays: 1568
- memory_delays_per_request: 1.24247
- memory_delays_in_input_queue: 615
- memory_delays_behind_head_of_bank_queue: 1
- memory_delays_stalled_at_head_of_bank_queue: 952
- memory_stalls_for_bank_busy: 261
- memory_stalls_for_random_busy: 0
- memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 39
- memory_stalls_for_bus: 627
- memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 25
- memory_stalls_for_read_read_turnaround: 0
- accesses_per_bank: 90 30 28 38 62 36 45 47 17 28 13 18 28 22 6 14 12 27 39 28 18 42 13 12 41 72 76 92 62 79 86 41
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
-DMA-0:0
+
Busy Bank Count:0
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 1 count: 1262 average: 0.487322 | standard deviation: 0.500594 | 647 615 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6772 average: 1 | standard deviation: 0 | 0 6772 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average: 1 | standard deviation: 0 | 0 6773 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 270 count: 6772 average: 18.3048 | standard deviation: 50.462 | 0 6125 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 13 0 0 0 0 558 0 0 0 0 5 0 0 0 0 17 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 270 count: 5383 average: 13.4873 | standard deviation: 43.0215 | 0 5021 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 0 0 0 0 3 0 0 0 0 316 0 0 0 0 4 0 0 0 0 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 260 count: 716 average: 41.8128 | standard deviation: 72.7521 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 7 0 0 0 0 141 0 0 0 0 1 0 0 0 0 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 260 count: 673 average: 31.8276 | standard deviation: 65.1506 | 0 555 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 3 0 0 0 0 101 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_1: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
Request vs. RubySystem State Profile
--------------------------------
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 1262 average: 0 | standard deviation: 0 | 1262 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1262 average: 0 | standard deviation: 0 | 1262 ]
+Total_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 647 average: 0 | standard deviation: 0 | 647 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 615 average: 0 | standard deviation: 0 | 615 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1289 average: 0 | standard deviation: 0 | 1289 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1285 average: 0 | standard deviation: 0 | 1285 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 37948
-page_faults: 0
+page_reclaims: 7494
+page_faults: 2200
swaps: 0
block_inputs: 0
-block_outputs: 48
+block_outputs: 0
Network Stats
-------------
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.00019414
- links_utilized_percent_switch_0_link_0: 7.76558e-05 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.000310623 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.158621
+ links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 647 5176 [ 0 647 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Writeback_Control: 615 4920 [ 0 0 615 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Control: 647 5176 [ 647 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Data: 615 4920 [ 615 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.00019414
- links_utilized_percent_switch_1_link_0: 7.76558e-05 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.000310623 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.158857
+ links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1
- outgoing_messages_switch_1_link_0_Control: 647 5176 [ 647 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Data: 615 4920 [ 615 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Data: 647 5176 [ 0 647 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 615 4920 [ 0 0 615 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_3_inlinks: 3
-switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0.000207082
- links_utilized_percent_switch_3_link_0: 0.000310623 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0.000310623 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_3_link_0_Response_Data: 647 5176 [ 0 647 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Writeback_Control: 615 4920 [ 0 0 615 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Control: 647 5176 [ 647 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Data: 615 4920 [ 615 0 0 0 0 0 ] base_latency: 1
-
- --- DMA ---
+links_utilized_percent_switch_2: 0.253982
+ links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1289
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1289
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 30.6439%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.8867%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 55.4694%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1289 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1289 average: 5.1249 | standard deviation: 2.01759 | 0 50 2 0 836 0 0 0 401 ]
+
+ --- L1Cache 0 ---
- Event Counts -
-ReadRequest 0
-WriteRequest 0
-Data 0
-Ack 0
+Load 716
+Ifetch 5383
+Store 673
+Data 1289
+Fwd_GETX 0
+Inv 0
+Replacement 1285
+Writeback_Ack 1285
+Writeback_Nack 0
- Transitions -
-READY ReadRequest 0 <--
-READY WriteRequest 0 <--
+I Load 395
+I Ifetch 715
+I Store 179
+I Inv 0 <--
+I Replacement 0 <--
-BUSY_RD Data 0 <--
+II Writeback_Nack 0 <--
-BUSY_WR Ack 0 <--
+M Load 321
+M Ifetch 4668
+M Store 494
+M Fwd_GETX 0 <--
+M Inv 0 <--
+M Replacement 1285
+
+MI Fwd_GETX 0 <--
+MI Inv 0 <--
+MI Writeback_Ack 1285
+
+IS Data 1110
+
+IM Data 179
+
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+ memory_total_requests: 2574
+ memory_reads: 1289
+ memory_writes: 1285
+ memory_refreshes: 528
+ memory_total_request_delays: 3552
+ memory_delays_per_request: 1.37995
+ memory_delays_in_input_queue: 1284
+ memory_delays_behind_head_of_bank_queue: 3
+ memory_delays_stalled_at_head_of_bank_queue: 2265
+ memory_stalls_for_bank_busy: 847
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 88
+ memory_stalls_for_bus: 1292
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 38
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66
- --- Directory ---
+ --- Directory 0 ---
- Event Counts -
-GETX 647
+GETX 1289
GETS 0
-PUTX 615
+PUTX 1285
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
-Memory_Data 647
-Memory_Ack 615
+Memory_Data 1289
+Memory_Ack 1285
- Transitions -
-I GETX 647
+I GETX 1289
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
M GETX 0 <--
-M PUTX 615
+M PUTX 1285
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
+M_DWRI GETX 0 <--
M_DWRI Memory_Ack 0 <--
+M_DRDI GETX 0 <--
+M_DRDI Memory_Ack 0 <--
+
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
-IM Memory_Data 647
+IM Memory_Data 1289
MI GETX 0 <--
MI GETS 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
-MI Memory_Ack 615
+MI Memory_Ack 1285
ID GETX 0 <--
ID GETS 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
- --- L1Cache ---
- - Event Counts -
-Load 716
-Ifetch 5383
-Store 673
-Data 647
-Fwd_GETX 0
-Inv 0
-Replacement 615
-Writeback_Ack 615
-Writeback_Nack 0
-
- - Transitions -
-I Load 167
-I Ifetch 362
-I Store 118
-I Inv 0 <--
-I Replacement 0 <--
-
-II Writeback_Nack 0 <--
-
-M Load 549
-M Ifetch 5021
-M Store 555
-M Fwd_GETX 0 <--
-M Inv 0 <--
-M Replacement 615
-
-MI Fwd_GETX 0 <--
-MI Inv 0 <--
-MI Writeback_Ack 615
-
-IS Data 529
-
-IM Data 118
-
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
-print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Jul 6 2009 11:07:18
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:35
-M5 executing on maize
+M5 compiled Jan 21 2010 11:29:25
+M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
+M5 started Jan 21 2010 11:30:48
+M5 executing on svvint07
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
-Global frequency set at 1000000000000 ticks per second
- Debug: Adding to filter: 'q' (Queue)
+Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 20314000 because target called exit()
+Hello World!Exiting @ tick 253364 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 3344 # Simulator instruction rate (inst/s)
-host_mem_usage 1362412 # Number of bytes of host memory used
-host_seconds 1.60 # Real time elapsed on the host
-host_tick_rate 12720005 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 59331 # Simulator instruction rate (inst/s)
+host_mem_usage 347024 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 2815062 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
-sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 20314000 # Number of ticks simulated
+sim_seconds 0.000253 # Number of seconds simulated
+sim_ticks 253364 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 40628 # number of cpu cycles simulated
+system.cpu.numCycles 253364 # number of cpu cycles simulated
system.cpu.num_insts 5340 # Number of instructions executed
system.cpu.num_refs 1402 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+++ /dev/null
-[root]
-type=Root
-children=system
-dummy=0
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.dtb]
-type=X86TLB
-size=64
-
-[system.cpu.itb]
-type=X86TLB
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
-file=
-latency=30000
-latency_var=0
-null=false
-num_cpus=1
-phase=0
-range=0:134217727
-stats_file=ruby.stats
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-
-================ Begin RubySystem Configuration Print ================
-
-RubySystem config:
- random_seed: 1234
- randomization: 0
- tech_nm: 45
- freq_mhz: 3000
- block_size_bytes: 64
- block_size_bits: 6
- memory_size_bytes: 1073741824
- memory_size_bits: 30
-DMA_Controller config: DMAController_0
- version: 0
- buffer_size: 32
- dma_sequencer: DMASequencer_0
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 6
- transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
- version: 0
- buffer_size: 32
- directory_latency: 6
- directory_name: DirectoryMemory_0
- dma_select_low_bit: 6
- dma_select_num_bits: 0
- memory_controller_name: MemoryControl_0
- number_of_TBEs: 256
- recycle_latency: 10
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
- version: 0
- buffer_size: 32
- cache: l1u_0
- cache_response_latency: 12
- issue_latency: 2
- number_of_TBEs: 256
- recycle_latency: 10
- sequencer: Sequencer_0
- transitions_per_cycle: 32
-Cache config: l1u_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 2
- num_cache_sets: 4
- cache_set_size_bytes: 256
- cache_set_size_Kbytes: 0.25
- cache_set_size_Mbytes: 0.000244141
- cache_size_bytes: 2048
- cache_size_Kbytes: 2
- cache_size_Mbytes: 0.00195312
-DirectoryMemory Global Config:
- number of directory memories: 1
- total memory size bytes: 1073741824
- total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
- controller: DirectoryController_0
- version: 0
- memory_bits: 30
- memory_size_bytes: 1073741824
- memory_size_Kbytes: 1.04858e+06
- memory_size_Mbytes: 1024
- memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
- controller: L1CacheController_0
- version: 0
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-
-Network Configuration
----------------------
-network: SIMPLE_NETWORK
-topology: theTopology
-
-virtual_net_0: active, ordered
-virtual_net_1: active, ordered
-virtual_net_2: active, ordered
-virtual_net_3: inactive
-virtual_net_4: active, ordered
-virtual_net_5: active, ordered
-
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
- L1Cache-0 -> Directory-0 net_lat: 7
- L1Cache-0 -> DMA-0 net_lat: 7
-
-Directory-0 Network Latencies
- Directory-0 -> L1Cache-0 net_lat: 7
- Directory-0 -> DMA-0 net_lat: 7
-
-DMA-0 Network Latencies
- DMA-0 -> L1Cache-0 net_lat: 7
- DMA-0 -> Directory-0 net_lat: 7
-
---- End Topology Print ---
-
-Profiler Configuration
-----------------------
-periodic_stats_period: 1000000
-
-================ End RubySystem Configuration Print ================
-
-
-Real time: Aug/09/2009 03:58:51
-
-Profiler Stats
---------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
-
-Virtual_time_in_seconds: 0.34
-Virtual_time_in_minutes: 0.00566667
-Virtual_time_in_hours: 9.44444e-05
-Virtual_time_in_days: 3.93519e-06
-
-Ruby_current_time: 5504001
-Ruby_start_time: 1
-Ruby_cycles: 5504000
-
-mbytes_resident: 144.359
-mbytes_total: 1352.23
-resident_ratio: 0.106763
-
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 5504001 [ 5504001 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
-
-Busy Controller Counts:
-L1Cache-0:0
-Directory-0:0
-DMA-0:0
-
-Busy Bank Count:0
-
-sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle SW Prefetch Requests
-------------------------------------
-prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Request vs. RubySystem State Profile
---------------------------------
-
-
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Resource Usage
---------------
-page_size: 4096
-user_time: 0
-system_time: 0
-page_reclaims: 38267
-page_faults: 1
-swaps: 0
-block_inputs: 0
-block_outputs: 0
-
-Network Stats
--------------
-
-switch_0_inlinks: 2
-switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0
- links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_1_inlinks: 2
-switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0
- links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_2_inlinks: 2
-switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_3_inlinks: 3
-switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0
- links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
-
-
-l1u_0 cache stats:
- l1u_0_total_misses: 0
- l1u_0_total_demand_misses: 0
- l1u_0_total_prefetches: 0
- l1u_0_total_sw_prefetches: 0
- l1u_0_total_hw_prefetches: 0
- l1u_0_misses_per_transaction: nan
-
- l1u_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- DMA 0 ---
- - Event Counts -
-ReadRequest 0
-WriteRequest 0
-Data 0
-Ack 0
-
- - Transitions -
-READY ReadRequest 0 <--
-READY WriteRequest 0 <--
-
-BUSY_RD Data 0 <--
-
-BUSY_WR Ack 0 <--
-
- --- Directory 0 ---
- - Event Counts -
-GETX 0
-GETS 0
-PUTX 0
-PUTX_NotOwner 0
-DMA_READ 0
-DMA_WRITE 0
-Memory_Data 0
-Memory_Ack 0
-
- - Transitions -
-I GETX 0 <--
-I PUTX_NotOwner 0 <--
-I DMA_READ 0 <--
-I DMA_WRITE 0 <--
-
-M GETX 0 <--
-M PUTX 0 <--
-M PUTX_NotOwner 0 <--
-M DMA_READ 0 <--
-M DMA_WRITE 0 <--
-
-M_DRD GETX 0 <--
-M_DRD PUTX 0 <--
-
-M_DWR GETX 0 <--
-M_DWR PUTX 0 <--
-
-M_DWRI Memory_Ack 0 <--
-
-IM GETX 0 <--
-IM GETS 0 <--
-IM PUTX 0 <--
-IM PUTX_NotOwner 0 <--
-IM DMA_READ 0 <--
-IM DMA_WRITE 0 <--
-IM Memory_Data 0 <--
-
-MI GETX 0 <--
-MI GETS 0 <--
-MI PUTX 0 <--
-MI PUTX_NotOwner 0 <--
-MI DMA_READ 0 <--
-MI DMA_WRITE 0 <--
-MI Memory_Ack 0 <--
-
-ID GETX 0 <--
-ID GETS 0 <--
-ID PUTX 0 <--
-ID PUTX_NotOwner 0 <--
-ID DMA_READ 0 <--
-ID DMA_WRITE 0 <--
-ID Memory_Data 0 <--
-
-ID_W GETX 0 <--
-ID_W GETS 0 <--
-ID_W PUTX 0 <--
-ID_W PUTX_NotOwner 0 <--
-ID_W DMA_READ 0 <--
-ID_W DMA_WRITE 0 <--
-ID_W Memory_Ack 0 <--
-
- --- L1Cache 0 ---
- - Event Counts -
-Load 0
-Ifetch 0
-Store 0
-Data 0
-Fwd_GETX 0
-Inv 0
-Replacement 0
-Writeback_Ack 0
-Writeback_Nack 0
-
- - Transitions -
-I Load 0 <--
-I Ifetch 0 <--
-I Store 0 <--
-I Inv 0 <--
-I Replacement 0 <--
-
-II Writeback_Nack 0 <--
-
-M Load 0 <--
-M Ifetch 0 <--
-M Store 0 <--
-M Fwd_GETX 0 <--
-M Inv 0 <--
-M Replacement 0 <--
-
-MI Fwd_GETX 0 <--
-MI Inv 0 <--
-MI Writeback_Ack 0 <--
-
-IS Data 0 <--
-
-IM Data 0 <--
-
+++ /dev/null
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
-Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false.
-Solution: Re-compile with RUBY_DEBUG set to true.
-print config: 1
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
-warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
-hack: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Aug 9 2009 03:58:47
-M5 revision 33faa9915d16 6486 default tip
-M5 started Aug 9 2009 03:58:49
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 5504000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 7886 # Simulator instruction rate (inst/s)
-host_mem_usage 1384684 # Number of bytes of host memory used
-host_seconds 1.21 # Real time elapsed on the host
-host_tick_rate 4559114 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 9519 # Number of instructions simulated
-sim_seconds 0.000006 # Number of seconds simulated
-sim_ticks 5504000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 11009 # number of cpu cycles simulated
-system.cpu.num_insts 9519 # Number of instructions executed
-system.cpu.num_refs 1987 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
-
----------- End Simulation Statistics ----------
[system]
type=System
-children=cpu membus physmem
+children=cpu physmem ruby
mem_mode=atomic
physmem=system.physmem
type=TimingSimpleCPU
children=dtb itb tracer workload
checker=Null
-clock=500
+clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
[system.cpu.dtb]
type=X86TLB
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
system=system
uid=100
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
+type=PhysicalMemory
file=
-latency=30000
+latency=30
latency_var=0
null=false
-num_cpus=1
-phase=0
range=0:134217727
-stats_file=ruby.stats
zero=false
-port=system.membus.port[0]
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tech_nm=45
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
random_seed: 1234
randomization: 0
tech_nm: 45
- freq_mhz: 3000
+ cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
- memory_size_bytes: 1073741824
- memory_size_bits: 30
-DMA_Controller config: DMAController_0
- version: 0
- buffer_size: 32
- dma_sequencer: DMASequencer_0
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 6
- transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
- version: 0
- buffer_size: 32
- directory_latency: 6
- directory_name: DirectoryMemory_0
- dma_select_low_bit: 6
- dma_select_num_bits: 0
- memory_controller_name: MemoryControl_0
- number_of_TBEs: 256
- recycle_latency: 10
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
- version: 0
- buffer_size: 32
- cache: l1u_0
- cache_response_latency: 12
- issue_latency: 2
- number_of_TBEs: 256
- recycle_latency: 10
- sequencer: Sequencer_0
- transitions_per_cycle: 32
-Cache config: l1u_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 2
- num_cache_sets: 4
- cache_set_size_bytes: 256
- cache_set_size_Kbytes: 0.25
- cache_set_size_Mbytes: 0.000244141
- cache_size_bytes: 2048
- cache_size_Kbytes: 2
- cache_size_Mbytes: 0.00195312
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
DirectoryMemory Global Config:
number of directory memories: 1
- total memory size bytes: 1073741824
- total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
- controller: DirectoryController_0
- version: 0
- memory_bits: 30
- memory_size_bytes: 1073741824
- memory_size_Kbytes: 1.04858e+06
- memory_size_Mbytes: 1024
- memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
- controller: L1CacheController_0
- version: 0
- max_outstanding_requests: 16
- deadlock_threshold: 500000
+ total memory size bytes: 134217728
+ total memory size bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: theTopology
+topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
- L1Cache-0 -> Directory-0 net_lat: 7
- L1Cache-0 -> DMA-0 net_lat: 7
-
-Directory-0 Network Latencies
- Directory-0 -> L1Cache-0 net_lat: 7
- Directory-0 -> DMA-0 net_lat: 7
-
-DMA-0 Network Latencies
- DMA-0 -> L1Cache-0 net_lat: 7
- DMA-0 -> Directory-0 net_lat: 7
-
---- End Topology Print ---
Profiler Configuration
----------------------
================ End RubySystem Configuration Print ================
-Real time: Aug/09/2009 04:00:22
+Real time: Jan/21/2010 12:14:46
Profiler Stats
--------------
-Elapsed_time_in_seconds: 4
-Elapsed_time_in_minutes: 0.0666667
-Elapsed_time_in_hours: 0.00111111
-Elapsed_time_in_days: 4.62963e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 1.19
-Virtual_time_in_minutes: 0.0198333
-Virtual_time_in_hours: 0.000330556
-Virtual_time_in_days: 1.37731e-05
+Virtual_time_in_seconds: 0.32
+Virtual_time_in_minutes: 0.00533333
+Virtual_time_in_hours: 8.88889e-05
+Virtual_time_in_days: 3.7037e-06
-Ruby_current_time: 26617001
-Ruby_start_time: 1
-Ruby_cycles: 26617000
+Ruby_current_time: 287334
+Ruby_start_time: 0
+Ruby_cycles: 287334
-mbytes_resident: 144.777
-mbytes_total: 1352.41
-resident_ratio: 0.107057
+mbytes_resident: 34.1406
+mbytes_total: 34.3242
+resident_ratio: 0.994879
Total_misses: 0
total_misses: 0 [ 0 ]
user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
-ruby_cycles_executed: 26617001 [ 26617001 ]
+ruby_cycles_executed: 287335 [ 287335 ]
transactions_started: 0 [ 0 ]
transactions_ended: 0 [ 0 ]
misses_per_transaction: 0 [ 0 ]
-Memory control MemoryControl_0:
- memory_total_requests: 1082
- memory_reads: 557
- memory_writes: 525
- memory_refreshes: 10431
- memory_total_request_delays: 1311
- memory_delays_per_request: 1.21165
- memory_delays_in_input_queue: 525
- memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 786
- memory_stalls_for_bank_busy: 180
- memory_stalls_for_random_busy: 0
- memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 38
- memory_stalls_for_bus: 546
- memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 22
- memory_stalls_for_read_read_turnaround: 0
- accesses_per_bank: 58 43 53 51 67 43 40 32 18 19 34 51 41 46 28 10 31 8 8 12 42 34 9 20 10 25 44 26 25 58 55 41
-
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
-DMA-0:0
+
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8873 average: 1 | standard deviation: 0 | 0 8873 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8874 average: 1 | standard deviation: 0 | 0 8874 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 277 count: 8873 average: 11.531 | standard deviation: 40.8912 | 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 277 count: 6886 average: 8.82021 | standard deviation: 35.5704 | 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 277 count: 1053 average: 23.3457 | standard deviation: 57.517 | 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 257 count: 934 average: 18.197 | standard deviation: 50.763 | 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 373 count: 8873 average: 31.383 | standard deviation: 65.1247 | 0 7435 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 6 5 6 6 3 335 255 166 323 190 5 5 4 3 1 12 13 5 9 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 13 16 13 8 0 3 3 2 2 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 287 count: 6886 average: 19.1856 | standard deviation: 51.0326 | 0 6248 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 4 1 3 2 158 129 57 116 103 3 1 2 2 1 4 7 1 5 4 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 6 4 3 5 5 0 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 373 count: 1053 average: 91.7255 | standard deviation: 89.279 | 0 521 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 5 2 1 109 51 79 167 65 1 3 0 1 0 4 5 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 11 8 2 0 0 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 281 count: 934 average: 53.2784 | standard deviation: 80.2311 | 0 666 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 68 75 30 40 22 1 1 2 0 0 4 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 8 2 0 1 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standard deviation: 0 | 1082 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standard deviation: 0 | 1082 ]
+Total_delay_cycles: [binsize: 1 max: 0 count: 2872 average: 0 | standard deviation: 0 | 2872 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2872 average: 0 | standard deviation: 0 | 2872 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 557 average: 0 | standard deviation: 0 | 557 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 525 average: 0 | standard deviation: 0 | 525 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1438 average: 0 | standard deviation: 0 | 1438 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1434 average: 0 | standard deviation: 0 | 1434 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
-user_time: 1
+user_time: 0
system_time: 0
-page_reclaims: 38363
-page_faults: 0
+page_reclaims: 7403
+page_faults: 2289
swaps: 0
block_inputs: 0
block_outputs: 0
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.000127033
- links_utilized_percent_switch_0_link_0: 5.08134e-05 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.000203254 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.156073
+ links_utilized_percent_switch_0_link_0: 0.0625405 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.249605 bw: 160000 base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 1438 103536 [ 0 1438 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 1434 11472 [ 0 0 1434 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 1438 11504 [ 1438 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Data: 1434 103248 [ 1434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.000127033
- links_utilized_percent_switch_1_link_0: 5.08134e-05 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.000203254 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.156282
+ links_utilized_percent_switch_1_link_0: 0.0624012 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.250162 bw: 160000 base_latency: 1
- outgoing_messages_switch_1_link_0_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Control: 1438 11504 [ 1438 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Data: 1434 103248 [ 1434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 1438 103536 [ 0 1438 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 1434 11472 [ 0 0 1434 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_3_inlinks: 3
-switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0.000135502
- links_utilized_percent_switch_3_link_0: 0.000203254 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0.000203254 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_3_link_0_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
-
-l1u_0 cache stats:
- l1u_0_total_misses: 557
- l1u_0_total_demand_misses: 557
- l1u_0_total_prefetches: 0
- l1u_0_total_sw_prefetches: 0
- l1u_0_total_hw_prefetches: 0
- l1u_0_misses_per_transaction: inf
-
- l1u_0_request_type_LD: 25.1346%
- l1u_0_request_type_ST: 17.4147%
- l1u_0_request_type_IFETCH: 57.4506%
-
- l1u_0_access_mode_type_SupervisorMode: 557 100%
- l1u_0_request_size: [binsize: log2 max: 8 count: 557 average: 7.5368 | standard deviation: 1.45496 | 0 12 1 42 502 ]
-
- --- DMA 0 ---
+links_utilized_percent_switch_2: 0.249883
+ links_utilized_percent_switch_2_link_0: 0.250162 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.249605 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 1438 103536 [ 0 1438 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 1434 11472 [ 0 0 1434 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 1438 11504 [ 1438 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Data: 1434 103248 [ 1434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1438
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1438
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 36.9958%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 18.637%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 44.3672%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1438 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1438 average: 7.26912 | standard deviation: 1.85842 | 0 71 3 0 134 0 0 0 1230 ]
+
+ --- L1Cache 0 ---
- Event Counts -
-ReadRequest 0
-WriteRequest 0
-Data 0
-Ack 0
+Load 1053
+Ifetch 6886
+Store 934
+Data 1438
+Fwd_GETX 0
+Inv 0
+Replacement 1434
+Writeback_Ack 1434
+Writeback_Nack 0
- Transitions -
-READY ReadRequest 0 <--
-READY WriteRequest 0 <--
+I Load 532
+I Ifetch 638
+I Store 268
+I Inv 0 <--
+I Replacement 0 <--
-BUSY_RD Data 0 <--
+II Writeback_Nack 0 <--
-BUSY_WR Ack 0 <--
+M Load 521
+M Ifetch 6248
+M Store 666
+M Fwd_GETX 0 <--
+M Inv 0 <--
+M Replacement 1434
+
+MI Fwd_GETX 0 <--
+MI Inv 0 <--
+MI Writeback_Ack 1434
+
+IS Data 1170
+
+IM Data 268
+
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+ memory_total_requests: 2872
+ memory_reads: 1438
+ memory_writes: 1434
+ memory_refreshes: 599
+ memory_total_request_delays: 3924
+ memory_delays_per_request: 1.3663
+ memory_delays_in_input_queue: 1431
+ memory_delays_behind_head_of_bank_queue: 7
+ memory_delays_stalled_at_head_of_bank_queue: 2486
+ memory_stalls_for_bank_busy: 841
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 109
+ memory_stalls_for_bus: 1466
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 70
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 162 142 210 172 216 84 102 44 22 20 146 276 148 116 62 30 84 8 8 14 116 56 12 60 34 58 82 64 44 122 104 54
--- Directory 0 ---
- Event Counts -
-GETX 557
+GETX 1438
GETS 0
-PUTX 525
+PUTX 1434
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
-Memory_Data 557
-Memory_Ack 525
+Memory_Data 1438
+Memory_Ack 1434
- Transitions -
-I GETX 557
+I GETX 1438
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
M GETX 0 <--
-M PUTX 525
+M PUTX 1434
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
+M_DWRI GETX 0 <--
M_DWRI Memory_Ack 0 <--
+M_DRDI GETX 0 <--
+M_DRDI Memory_Ack 0 <--
+
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
-IM Memory_Data 557
+IM Memory_Data 1438
MI GETX 0 <--
MI GETS 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
-MI Memory_Ack 525
+MI Memory_Ack 1434
ID GETX 0 <--
ID GETS 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
- --- L1Cache 0 ---
- - Event Counts -
-Load 1053
-Ifetch 6886
-Store 934
-Data 557
-Fwd_GETX 0
-Inv 0
-Replacement 525
-Writeback_Ack 525
-Writeback_Nack 0
-
- - Transitions -
-I Load 140
-I Ifetch 320
-I Store 97
-I Inv 0 <--
-I Replacement 0 <--
-
-II Writeback_Nack 0 <--
-
-M Load 913
-M Ifetch 6566
-M Store 837
-M Fwd_GETX 0 <--
-M Inv 0 <--
-M Replacement 525
-
-MI Fwd_GETX 0 <--
-MI Inv 0 <--
-MI Writeback_Ack 525
-
-IS Data 460
-
-IM Data 97
-
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
-Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false.
-Solution: Re-compile with RUBY_DEBUG set to true.
-print config: 1
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
All Rights Reserved
-M5 compiled Aug 9 2009 04:00:16
-M5 revision 33faa9915d16+ 6486+ default tip
-M5 started Aug 9 2009 04:00:18
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
-Global frequency set at 1000000000000 ticks per second
+M5 compiled Jan 21 2010 12:13:38
+M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
+M5 started Jan 21 2010 12:14:46
+M5 executing on svvint07
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
+Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 26617000 because target called exit()
+Exiting @ tick 287334 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 2962 # Simulator instruction rate (inst/s)
-host_mem_usage 1384872 # Number of bytes of host memory used
-host_seconds 3.21 # Real time elapsed on the host
-host_tick_rate 8282962 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 52882 # Simulator instruction rate (inst/s)
+host_mem_usage 349184 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
+host_tick_rate 1596256 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 9519 # Number of instructions simulated
-sim_seconds 0.000027 # Number of seconds simulated
-sim_ticks 26617000 # Number of ticks simulated
+sim_seconds 0.000287 # Number of seconds simulated
+sim_ticks 287334 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 53234 # number of cpu cycles simulated
+system.cpu.numCycles 287334 # number of cpu cycles simulated
system.cpu.num_insts 9519 # Number of instructions executed
system.cpu.num_refs 1987 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+++ /dev/null
-[root]
-type=Root
-children=system
-dummy=0
-
-[system]
-type=System
-children=cpu0 cpu1 cpu2 cpu3 membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=system.cpu0.workload
-dcache_port=system.membus.port[1]
-icache_port=system.membus.port[0]
-
-[system.cpu0.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu0.itb]
-type=SparcTLB
-size=64
-
-[system.cpu0.tracer]
-type=ExeTracer
-
-[system.cpu0.workload]
-type=LiveProcess
-cmd=test_atomic 4
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dtb itb tracer
-checker=Null
-clock=500
-cpu_id=1
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu1.tracer
-width=1
-workload=system.cpu0.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
-
-[system.cpu1.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu1.itb]
-type=SparcTLB
-size=64
-
-[system.cpu1.tracer]
-type=ExeTracer
-
-[system.cpu2]
-type=AtomicSimpleCPU
-children=dtb itb tracer
-checker=Null
-clock=500
-cpu_id=2
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu2.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu2.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu2.tracer
-width=1
-workload=system.cpu0.workload
-dcache_port=system.membus.port[5]
-icache_port=system.membus.port[4]
-
-[system.cpu2.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu2.itb]
-type=SparcTLB
-size=64
-
-[system.cpu2.tracer]
-type=ExeTracer
-
-[system.cpu3]
-type=AtomicSimpleCPU
-children=dtb itb tracer
-checker=Null
-clock=500
-cpu_id=3
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu3.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu3.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu3.tracer
-width=1
-workload=system.cpu0.workload
-dcache_port=system.membus.port[7]
-icache_port=system.membus.port[6]
-
-[system.cpu3.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu3.itb]
-type=SparcTLB
-size=64
-
-[system.cpu3.tracer]
-type=ExeTracer
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port system.cpu2.icache_port system.cpu2.dcache_port system.cpu3.icache_port system.cpu3.dcache_port system.physmem.port[0]
-
-[system.physmem]
-type=RubyMemory
-clock=1
-config_file=
-config_options=
-debug=false
-debug_file=
-file=
-latency=30000
-latency_var=0
-null=false
-num_cpus=4
-phase=0
-range=0:134217727
-stats_file=ruby.stats
-zero=false
-port=system.membus.port[8]
-
+++ /dev/null
-
-================ Begin RubySystem Configuration Print ================
-
-Ruby Configuration
-------------------
-protocol: MOSI_SMP_bcast
-compiled_at: 22:54:24, May 4 2009
-RUBY_DEBUG: false
-hostname: piton
-g_RANDOM_SEED: 1
-g_DEADLOCK_THRESHOLD: 500000
-RANDOMIZATION: false
-g_SYNTHETIC_DRIVER: false
-g_DETERMINISTIC_DRIVER: false
-g_FILTERING_ENABLED: false
-g_DISTRIBUTED_PERSISTENT_ENABLED: true
-g_DYNAMIC_TIMEOUT_ENABLED: true
-g_RETRY_THRESHOLD: 1
-g_FIXED_TIMEOUT_LATENCY: 300
-g_trace_warmup_length: 1000000
-g_bash_bandwidth_adaptive_threshold: 0.75
-g_tester_length: 0
-g_synthetic_locks: 2048
-g_deterministic_addrs: 1
-g_SpecifiedGenerator: DetermInvGenerator
-g_callback_counter: 0
-g_NUM_COMPLETIONS_BEFORE_PASS: 0
-g_NUM_SMT_THREADS: 1
-g_think_time: 5
-g_hold_time: 5
-g_wait_time: 5
-PROTOCOL_DEBUG_TRACE: true
-DEBUG_FILTER_STRING: none
-DEBUG_VERBOSITY_STRING: none
-DEBUG_START_TIME: 0
-DEBUG_OUTPUT_FILENAME: none
-SIMICS_RUBY_MULTIPLIER: 4
-OPAL_RUBY_MULTIPLIER: 1
-TRANSACTION_TRACE_ENABLED: false
-USER_MODE_DATA_ONLY: false
-PROFILE_HOT_LINES: false
-PROFILE_ALL_INSTRUCTIONS: false
-PRINT_INSTRUCTION_TRACE: false
-g_DEBUG_CYCLE: 0
-BLOCK_STC: false
-PERFECT_MEMORY_SYSTEM: false
-PERFECT_MEMORY_SYSTEM_LATENCY: 0
-DATA_BLOCK: false
-REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
-L1_CACHE_ASSOC: 4
-L1_CACHE_NUM_SETS_BITS: 8
-L2_CACHE_ASSOC: 4
-L2_CACHE_NUM_SETS_BITS: 16
-g_MEMORY_SIZE_BYTES: 4294967296
-g_DATA_BLOCK_BYTES: 64
-g_PAGE_SIZE_BYTES: 4096
-g_REPLACEMENT_POLICY: PSEDUO_LRU
-g_NUM_PROCESSORS: 4
-g_NUM_L2_BANKS: 4
-g_NUM_MEMORIES: 4
-g_PROCS_PER_CHIP: 1
-g_NUM_CHIPS: 4
-g_NUM_CHIP_BITS: 2
-g_MEMORY_SIZE_BITS: 32
-g_DATA_BLOCK_BITS: 6
-g_PAGE_SIZE_BITS: 12
-g_NUM_PROCESSORS_BITS: 2
-g_PROCS_PER_CHIP_BITS: 0
-g_NUM_L2_BANKS_BITS: 2
-g_NUM_L2_BANKS_PER_CHIP_BITS: 0
-g_NUM_L2_BANKS_PER_CHIP: 1
-g_NUM_MEMORIES_BITS: 2
-g_NUM_MEMORIES_PER_CHIP: 1
-g_MEMORY_MODULE_BITS: 24
-g_MEMORY_MODULE_BLOCKS: 16777216
-MAP_L2BANKS_TO_LOWEST_BITS: false
-DIRECTORY_CACHE_LATENCY: 6
-NULL_LATENCY: 1
-ISSUE_LATENCY: 2
-CACHE_RESPONSE_LATENCY: 12
-L2_RESPONSE_LATENCY: 6
-L2_TAG_LATENCY: 6
-L1_RESPONSE_LATENCY: 3
-MEMORY_RESPONSE_LATENCY_MINUS_2: 158
-DIRECTORY_LATENCY: 80
-NETWORK_LINK_LATENCY: 1
-COPY_HEAD_LATENCY: 4
-ON_CHIP_LINK_LATENCY: 1
-RECYCLE_LATENCY: 10
-L2_RECYCLE_LATENCY: 5
-TIMER_LATENCY: 10000
-TBE_RESPONSE_LATENCY: 1
-PERIODIC_TIMER_WAKEUPS: true
-PROFILE_EXCEPTIONS: false
-PROFILE_XACT: true
-PROFILE_NONXACT: false
-XACT_DEBUG: true
-XACT_DEBUG_LEVEL: 1
-XACT_MEMORY: false
-XACT_ENABLE_TOURMALINE: false
-XACT_NUM_CURRENT: 0
-XACT_LAST_UPDATE: 0
-XACT_ISOLATION_CHECK: false
-PERFECT_FILTER: true
-READ_WRITE_FILTER: Perfect_
-PERFECT_VIRTUAL_FILTER: true
-VIRTUAL_READ_WRITE_FILTER: Perfect_
-PERFECT_SUMMARY_FILTER: true
-SUMMARY_READ_WRITE_FILTER: Perfect_
-XACT_EAGER_CD: true
-XACT_LAZY_VM: false
-XACT_CONFLICT_RES: BASE
-XACT_VISUALIZER: false
-XACT_COMMIT_TOKEN_LATENCY: 0
-XACT_NO_BACKOFF: false
-XACT_LOG_BUFFER_SIZE: 0
-XACT_STORE_PREDICTOR_HISTORY: 256
-XACT_STORE_PREDICTOR_ENTRIES: 256
-XACT_STORE_PREDICTOR_THRESHOLD: 4
-XACT_FIRST_ACCESS_COST: 0
-XACT_FIRST_PAGE_ACCESS_COST: 0
-ENABLE_MAGIC_WAITING: false
-ENABLE_WATCHPOINT: false
-XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
-ATMTP_ENABLED: false
-ATMTP_ABORT_ON_NON_XACT_INST: false
-ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
-ATMTP_XACT_MAX_STORES: 32
-ATMTP_DEBUG_LEVEL: 0
-L1_REQUEST_LATENCY: 2
-L2_REQUEST_LATENCY: 4
-SINGLE_ACCESS_L2_BANKS: true
-SEQUENCER_TO_CONTROLLER_LATENCY: 4
-L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
-L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
-DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
-g_SEQUENCER_OUTSTANDING_REQUESTS: 16
-NUMBER_OF_TBES: 128
-NUMBER_OF_L1_TBES: 32
-NUMBER_OF_L2_TBES: 32
-FINITE_BUFFERING: false
-FINITE_BUFFER_SIZE: 3
-PROCESSOR_BUFFER_SIZE: 10
-PROTOCOL_BUFFER_SIZE: 32
-TSO: false
-g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
-g_CACHE_DESIGN: NUCA
-g_endpoint_bandwidth: 10000
-g_adaptive_routing: true
-NUMBER_OF_VIRTUAL_NETWORKS: 4
-FAN_OUT_DEGREE: 4
-g_PRINT_TOPOLOGY: true
-XACT_LENGTH: 0
-XACT_SIZE: 0
-ABORT_RETRY_TIME: 0
-g_GARNET_NETWORK: false
-g_DETAIL_NETWORK: false
-g_NETWORK_TESTING: false
-g_FLIT_SIZE: 16
-g_NUM_PIPE_STAGES: 4
-g_VCS_PER_CLASS: 4
-g_BUFFER_SIZE: 4
-MEM_BUS_CYCLE_MULTIPLIER: 10
-BANKS_PER_RANK: 8
-RANKS_PER_DIMM: 2
-DIMMS_PER_CHANNEL: 2
-BANK_BIT_0: 8
-RANK_BIT_0: 11
-DIMM_BIT_0: 12
-BANK_QUEUE_SIZE: 12
-BANK_BUSY_TIME: 11
-RANK_RANK_DELAY: 1
-READ_WRITE_DELAY: 2
-BASIC_BUS_BUSY_TIME: 2
-MEM_CTL_LATENCY: 12
-REFRESH_PERIOD: 1560
-TFAW: 0
-MEM_RANDOM_ARBITRATE: 0
-MEM_FIXED_DELAY: 0
-
-Chip Config
------------
-Total_Chips: 4
-
-L1Cache_TBEs numberPerChip: 1
-TBEs_per_TBETable: 128
-
-L1Cache_L1IcacheMemory numberPerChip: 1
-Cache config: L1Cache_0_L1I
- cache_associativity: 4
- num_cache_sets_bits: 8
- num_cache_sets: 256
- cache_set_size_bytes: 16384
- cache_set_size_Kbytes: 16
- cache_set_size_Mbytes: 0.015625
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-
-L1Cache_L1DcacheMemory numberPerChip: 1
-Cache config: L1Cache_0_L1D
- cache_associativity: 4
- num_cache_sets_bits: 8
- num_cache_sets: 256
- cache_set_size_bytes: 16384
- cache_set_size_Kbytes: 16
- cache_set_size_Mbytes: 0.015625
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-
-L1Cache_L2cacheMemory numberPerChip: 1
-Cache config: L1Cache_0_L2
- cache_associativity: 4
- num_cache_sets_bits: 16
- num_cache_sets: 65536
- cache_set_size_bytes: 4194304
- cache_set_size_Kbytes: 4096
- cache_set_size_Mbytes: 4
- cache_size_bytes: 16777216
- cache_size_Kbytes: 16384
- cache_size_Mbytes: 16
-
-L1Cache_mandatoryQueue numberPerChip: 1
-
-L1Cache_sequencer numberPerChip: 1
-sequencer: Sequencer - SC
- max_outstanding_requests: 16
-
-L1Cache_storeBuffer numberPerChip: 1
-Store buffer entries: 128 (Only valid if TSO is enabled)
-
-Directory_directory numberPerChip: 1
-Memory config:
- memory_bits: 32
- memory_size_bytes: 4294967296
- memory_size_Kbytes: 4.1943e+06
- memory_size_Mbytes: 4096
- memory_size_Gbytes: 4
- module_bits: 24
- module_size_lines: 16777216
- module_size_bytes: 1073741824
- module_size_Kbytes: 1.04858e+06
- module_size_Mbytes: 1024
-
-
-Network Configuration
----------------------
-network: SIMPLE_NETWORK
-topology: HIERARCHICAL_SWITCH
-
-virtual_net_0: active, ordered
-virtual_net_1: active, unordered
-virtual_net_2: inactive
-virtual_net_3: inactive
-
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
- L1Cache-0 -> L1Cache-1 net_lat: 9
- L1Cache-0 -> L1Cache-2 net_lat: 9
- L1Cache-0 -> L1Cache-3 net_lat: 9
- L1Cache-0 -> Directory-0 net_lat: 9
- L1Cache-0 -> Directory-1 net_lat: 9
- L1Cache-0 -> Directory-2 net_lat: 9
- L1Cache-0 -> Directory-3 net_lat: 9
-
-L1Cache-1 Network Latencies
- L1Cache-1 -> L1Cache-0 net_lat: 9
- L1Cache-1 -> L1Cache-2 net_lat: 9
- L1Cache-1 -> L1Cache-3 net_lat: 9
- L1Cache-1 -> Directory-0 net_lat: 9
- L1Cache-1 -> Directory-1 net_lat: 9
- L1Cache-1 -> Directory-2 net_lat: 9
- L1Cache-1 -> Directory-3 net_lat: 9
-
-L1Cache-2 Network Latencies
- L1Cache-2 -> L1Cache-0 net_lat: 9
- L1Cache-2 -> L1Cache-1 net_lat: 9
- L1Cache-2 -> L1Cache-3 net_lat: 9
- L1Cache-2 -> Directory-0 net_lat: 9
- L1Cache-2 -> Directory-1 net_lat: 9
- L1Cache-2 -> Directory-2 net_lat: 9
- L1Cache-2 -> Directory-3 net_lat: 9
-
-L1Cache-3 Network Latencies
- L1Cache-3 -> L1Cache-0 net_lat: 9
- L1Cache-3 -> L1Cache-1 net_lat: 9
- L1Cache-3 -> L1Cache-2 net_lat: 9
- L1Cache-3 -> Directory-0 net_lat: 9
- L1Cache-3 -> Directory-1 net_lat: 9
- L1Cache-3 -> Directory-2 net_lat: 9
- L1Cache-3 -> Directory-3 net_lat: 9
-
-Directory-0 Network Latencies
- Directory-0 -> L1Cache-0 net_lat: 9
- Directory-0 -> L1Cache-1 net_lat: 9
- Directory-0 -> L1Cache-2 net_lat: 9
- Directory-0 -> L1Cache-3 net_lat: 9
- Directory-0 -> Directory-1 net_lat: 9
- Directory-0 -> Directory-2 net_lat: 9
- Directory-0 -> Directory-3 net_lat: 9
-
-Directory-1 Network Latencies
- Directory-1 -> L1Cache-0 net_lat: 9
- Directory-1 -> L1Cache-1 net_lat: 9
- Directory-1 -> L1Cache-2 net_lat: 9
- Directory-1 -> L1Cache-3 net_lat: 9
- Directory-1 -> Directory-0 net_lat: 9
- Directory-1 -> Directory-2 net_lat: 9
- Directory-1 -> Directory-3 net_lat: 9
-
-Directory-2 Network Latencies
- Directory-2 -> L1Cache-0 net_lat: 9
- Directory-2 -> L1Cache-1 net_lat: 9
- Directory-2 -> L1Cache-2 net_lat: 9
- Directory-2 -> L1Cache-3 net_lat: 9
- Directory-2 -> Directory-0 net_lat: 9
- Directory-2 -> Directory-1 net_lat: 9
- Directory-2 -> Directory-3 net_lat: 9
-
-Directory-3 Network Latencies
- Directory-3 -> L1Cache-0 net_lat: 9
- Directory-3 -> L1Cache-1 net_lat: 9
- Directory-3 -> L1Cache-2 net_lat: 9
- Directory-3 -> L1Cache-3 net_lat: 9
- Directory-3 -> Directory-0 net_lat: 9
- Directory-3 -> Directory-1 net_lat: 9
- Directory-3 -> Directory-2 net_lat: 9
-
---- End Topology Print ---
-
-Profiler Configuration
-----------------------
-periodic_stats_period: 1000000
-
-================ End RubySystem Configuration Print ================
-
-
-Real time: May/05/2009 07:34:05
-
-Profiler Stats
---------------
-Elapsed_time_in_seconds: 3
-Elapsed_time_in_minutes: 0.05
-Elapsed_time_in_hours: 0.000833333
-Elapsed_time_in_days: 3.47222e-05
-
-Virtual_time_in_seconds: 1.88
-Virtual_time_in_minutes: 0.0313333
-Virtual_time_in_hours: 0.000522222
-Virtual_time_in_days: 0.000522222
-
-Ruby_current_time: 87713501
-Ruby_start_time: 1
-Ruby_cycles: 87713500
-
-mbytes_resident: 90.4062
-mbytes_total: 251.832
-resident_ratio: 0.35901
-
-Total_misses: 0
-total_misses: 0 [ 0 0 0 0 ]
-user_misses: 0 [ 0 0 0 0 ]
-supervisor_misses: 0 [ 0 0 0 0 ]
-
-instruction_executed: 4 [ 1 1 1 1 ]
-cycles_executed: 4 [ 1 1 1 1 ]
-cycles_per_instruction: 8.77135e+07 [ 8.77135e+07 8.77135e+07 8.77135e+07 8.77135e+07 ]
-misses_per_thousand_instructions: 0 [ 0 0 0 0 ]
-
-transactions_started: 0 [ 0 0 0 0 ]
-transactions_ended: 0 [ 0 0 0 0 ]
-instructions_per_transaction: 0 [ 0 0 0 0 ]
-cycles_per_transaction: 0 [ 0 0 0 0 ]
-misses_per_transaction: 0 [ 0 0 0 0 ]
-
-L1D_cache cache stats:
- L1D_cache_total_misses: 0
- L1D_cache_total_demand_misses: 0
- L1D_cache_total_prefetches: 0
- L1D_cache_total_sw_prefetches: 0
- L1D_cache_total_hw_prefetches: 0
- L1D_cache_misses_per_transaction: 0
- L1D_cache_misses_per_instruction: 0
- L1D_cache_instructions_per_misses: NaN
-
- L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats:
- L1I_cache_total_misses: 0
- L1I_cache_total_demand_misses: 0
- L1I_cache_total_prefetches: 0
- L1I_cache_total_sw_prefetches: 0
- L1I_cache_total_hw_prefetches: 0
- L1I_cache_misses_per_transaction: 0
- L1I_cache_misses_per_instruction: 0
- L1I_cache_instructions_per_misses: NaN
-
- L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats:
- L2_cache_total_misses: 0
- L2_cache_total_demand_misses: 0
- L2_cache_total_prefetches: 0
- L2_cache_total_sw_prefetches: 0
- L2_cache_total_hw_prefetches: 0
- L2_cache_misses_per_transaction: 0
- L2_cache_misses_per_instruction: 0
- L2_cache_instructions_per_misses: NaN
-
- L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Busy Controller Counts:
-L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0
-Directory-0:0 Directory-1:0 Directory-2:0 Directory-3:0
-
-Busy Bank Count:0
-
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle SW Prefetch Requests
-------------------------------------
-prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Resource Usage
---------------
-page_size: 4096
-user_time: 1
-system_time: 0
-page_reclaims: 23338
-page_faults: 0
-swaps: 0
-block_inputs: 0
-block_outputs: 640
-MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
-MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
-MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
-MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
-
-Network Stats
--------------
-
-switch_0_inlinks: 1
-switch_0_outlinks: 1
-links_utilized_percent_switch_0: 0
- links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_1_inlinks: 1
-switch_1_outlinks: 1
-links_utilized_percent_switch_1: 0
- links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_2_inlinks: 1
-switch_2_outlinks: 1
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_3_inlinks: 1
-switch_3_outlinks: 1
-links_utilized_percent_switch_3: 0
- links_utilized_percent_switch_3_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_4_inlinks: 1
-switch_4_outlinks: 1
-links_utilized_percent_switch_4: 0
- links_utilized_percent_switch_4_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_5_inlinks: 1
-switch_5_outlinks: 1
-links_utilized_percent_switch_5: 0
- links_utilized_percent_switch_5_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_6_inlinks: 1
-switch_6_outlinks: 1
-links_utilized_percent_switch_6: 0
- links_utilized_percent_switch_6_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_7_inlinks: 1
-switch_7_outlinks: 1
-links_utilized_percent_switch_7: 0
- links_utilized_percent_switch_7_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_8_inlinks: 4
-switch_8_outlinks: 1
-links_utilized_percent_switch_8: 0
- links_utilized_percent_switch_8_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_9_inlinks: 4
-switch_9_outlinks: 1
-links_utilized_percent_switch_9: 0
- links_utilized_percent_switch_9_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_10_inlinks: 2
-switch_10_outlinks: 2
-links_utilized_percent_switch_10: 0
- links_utilized_percent_switch_10_link_0: 0 bw: 10000 base_latency: 1
- links_utilized_percent_switch_10_link_1: 0 bw: 10000 base_latency: 1
-
-
-switch_11_inlinks: 1
-switch_11_outlinks: 4
-links_utilized_percent_switch_11: 0
- links_utilized_percent_switch_11_link_0: 0 bw: 10000 base_latency: 1
- links_utilized_percent_switch_11_link_1: 0 bw: 10000 base_latency: 1
- links_utilized_percent_switch_11_link_2: 0 bw: 10000 base_latency: 1
- links_utilized_percent_switch_11_link_3: 0 bw: 10000 base_latency: 1
-
-
-switch_12_inlinks: 1
-switch_12_outlinks: 4
-links_utilized_percent_switch_12: 0
- links_utilized_percent_switch_12_link_0: 0 bw: 10000 base_latency: 1
- links_utilized_percent_switch_12_link_1: 0 bw: 10000 base_latency: 1
- links_utilized_percent_switch_12_link_2: 0 bw: 10000 base_latency: 1
- links_utilized_percent_switch_12_link_3: 0 bw: 10000 base_latency: 1
-
-
-
-Chip Stats
-----------
-
- --- L1Cache ---
- - Event Counts -
-Load 0
-Ifetch 0
-Store 0
-L1_to_L2 0
-L2_to_L1D 0
-L2_to_L1I 0
-L2_Replacement 0
-Own_GETS 0
-Own_GET_INSTR 0
-Own_GETX 0
-Own_PUTX 0
-Other_GETS 0
-Other_GET_INSTR 0
-Other_GETX 0
-Other_PUTX 0
-Data 0
-
- - Transitions -
-NP Load 0 <--
-NP Ifetch 0 <--
-NP Store 0 <--
-NP Other_GETS 0 <--
-NP Other_GET_INSTR 0 <--
-NP Other_GETX 0 <--
-NP Other_PUTX 0 <--
-
-I Load 0 <--
-I Ifetch 0 <--
-I Store 0 <--
-I L1_to_L2 0 <--
-I L2_to_L1D 0 <--
-I L2_to_L1I 0 <--
-I L2_Replacement 0 <--
-I Other_GETS 0 <--
-I Other_GET_INSTR 0 <--
-I Other_GETX 0 <--
-I Other_PUTX 0 <--
-
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_to_L2 0 <--
-S L2_to_L1D 0 <--
-S L2_to_L1I 0 <--
-S L2_Replacement 0 <--
-S Other_GETS 0 <--
-S Other_GET_INSTR 0 <--
-S Other_GETX 0 <--
-S Other_PUTX 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_to_L2 0 <--
-O L2_to_L1D 0 <--
-O L2_to_L1I 0 <--
-O L2_Replacement 0 <--
-O Other_GETS 0 <--
-O Other_GET_INSTR 0 <--
-O Other_GETX 0 <--
-O Other_PUTX 0 <--
-
-M Load 0 <--
-M Ifetch 0 <--
-M Store 0 <--
-M L1_to_L2 0 <--
-M L2_to_L1D 0 <--
-M L2_to_L1I 0 <--
-M L2_Replacement 0 <--
-M Other_GETS 0 <--
-M Other_GET_INSTR 0 <--
-M Other_GETX 0 <--
-M Other_PUTX 0 <--
-
-IS_AD Load 0 <--
-IS_AD Ifetch 0 <--
-IS_AD Store 0 <--
-IS_AD L1_to_L2 0 <--
-IS_AD L2_to_L1D 0 <--
-IS_AD L2_to_L1I 0 <--
-IS_AD L2_Replacement 0 <--
-IS_AD Own_GETS 0 <--
-IS_AD Own_GET_INSTR 0 <--
-IS_AD Other_GETS 0 <--
-IS_AD Other_GET_INSTR 0 <--
-IS_AD Other_GETX 0 <--
-IS_AD Other_PUTX 0 <--
-IS_AD Data 0 <--
-
-IM_AD Load 0 <--
-IM_AD Ifetch 0 <--
-IM_AD Store 0 <--
-IM_AD L1_to_L2 0 <--
-IM_AD L2_to_L1D 0 <--
-IM_AD L2_to_L1I 0 <--
-IM_AD L2_Replacement 0 <--
-IM_AD Own_GETX 0 <--
-IM_AD Other_GETS 0 <--
-IM_AD Other_GET_INSTR 0 <--
-IM_AD Other_GETX 0 <--
-IM_AD Other_PUTX 0 <--
-IM_AD Data 0 <--
-
-SM_AD Load 0 <--
-SM_AD Ifetch 0 <--
-SM_AD Store 0 <--
-SM_AD L1_to_L2 0 <--
-SM_AD L2_to_L1D 0 <--
-SM_AD L2_to_L1I 0 <--
-SM_AD L2_Replacement 0 <--
-SM_AD Own_GETX 0 <--
-SM_AD Other_GETS 0 <--
-SM_AD Other_GET_INSTR 0 <--
-SM_AD Other_GETX 0 <--
-SM_AD Other_PUTX 0 <--
-SM_AD Data 0 <--
-
-OM_A Load 0 <--
-OM_A Ifetch 0 <--
-OM_A Store 0 <--
-OM_A L1_to_L2 0 <--
-OM_A L2_to_L1D 0 <--
-OM_A L2_to_L1I 0 <--
-OM_A L2_Replacement 0 <--
-OM_A Own_GETX 0 <--
-OM_A Other_GETS 0 <--
-OM_A Other_GET_INSTR 0 <--
-OM_A Other_GETX 0 <--
-OM_A Other_PUTX 0 <--
-OM_A Data 0 <--
-
-IS_A Load 0 <--
-IS_A Ifetch 0 <--
-IS_A Store 0 <--
-IS_A L1_to_L2 0 <--
-IS_A L2_to_L1D 0 <--
-IS_A L2_to_L1I 0 <--
-IS_A L2_Replacement 0 <--
-IS_A Own_GETS 0 <--
-IS_A Own_GET_INSTR 0 <--
-IS_A Other_GETS 0 <--
-IS_A Other_GET_INSTR 0 <--
-IS_A Other_GETX 0 <--
-IS_A Other_PUTX 0 <--
-
-IM_A Load 0 <--
-IM_A Ifetch 0 <--
-IM_A Store 0 <--
-IM_A L1_to_L2 0 <--
-IM_A L2_to_L1D 0 <--
-IM_A L2_to_L1I 0 <--
-IM_A L2_Replacement 0 <--
-IM_A Own_GETX 0 <--
-IM_A Other_GETS 0 <--
-IM_A Other_GET_INSTR 0 <--
-IM_A Other_GETX 0 <--
-IM_A Other_PUTX 0 <--
-
-SM_A Load 0 <--
-SM_A Ifetch 0 <--
-SM_A Store 0 <--
-SM_A L1_to_L2 0 <--
-SM_A L2_to_L1D 0 <--
-SM_A L2_to_L1I 0 <--
-SM_A L2_Replacement 0 <--
-SM_A Own_GETX 0 <--
-SM_A Other_GETS 0 <--
-SM_A Other_GET_INSTR 0 <--
-SM_A Other_GETX 0 <--
-SM_A Other_PUTX 0 <--
-
-MI_A Load 0 <--
-MI_A Ifetch 0 <--
-MI_A Store 0 <--
-MI_A L1_to_L2 0 <--
-MI_A L2_to_L1D 0 <--
-MI_A L2_to_L1I 0 <--
-MI_A L2_Replacement 0 <--
-MI_A Own_PUTX 0 <--
-MI_A Other_GETS 0 <--
-MI_A Other_GET_INSTR 0 <--
-MI_A Other_GETX 0 <--
-MI_A Other_PUTX 0 <--
-
-OI_A Load 0 <--
-OI_A Ifetch 0 <--
-OI_A Store 0 <--
-OI_A L1_to_L2 0 <--
-OI_A L2_to_L1D 0 <--
-OI_A L2_to_L1I 0 <--
-OI_A L2_Replacement 0 <--
-OI_A Own_PUTX 0 <--
-OI_A Other_GETS 0 <--
-OI_A Other_GET_INSTR 0 <--
-OI_A Other_GETX 0 <--
-OI_A Other_PUTX 0 <--
-
-II_A Load 0 <--
-II_A Ifetch 0 <--
-II_A Store 0 <--
-II_A L1_to_L2 0 <--
-II_A L2_to_L1D 0 <--
-II_A L2_to_L1I 0 <--
-II_A L2_Replacement 0 <--
-II_A Own_PUTX 0 <--
-II_A Other_GETS 0 <--
-II_A Other_GET_INSTR 0 <--
-II_A Other_GETX 0 <--
-II_A Other_PUTX 0 <--
-
-IS_D Load 0 <--
-IS_D Ifetch 0 <--
-IS_D Store 0 <--
-IS_D L1_to_L2 0 <--
-IS_D L2_to_L1D 0 <--
-IS_D L2_to_L1I 0 <--
-IS_D L2_Replacement 0 <--
-IS_D Other_GETS 0 <--
-IS_D Other_GET_INSTR 0 <--
-IS_D Other_GETX 0 <--
-IS_D Other_PUTX 0 <--
-IS_D Data 0 <--
-
-IS_D_I Load 0 <--
-IS_D_I Ifetch 0 <--
-IS_D_I Store 0 <--
-IS_D_I L1_to_L2 0 <--
-IS_D_I L2_to_L1D 0 <--
-IS_D_I L2_to_L1I 0 <--
-IS_D_I L2_Replacement 0 <--
-IS_D_I Other_GETS 0 <--
-IS_D_I Other_GET_INSTR 0 <--
-IS_D_I Other_GETX 0 <--
-IS_D_I Other_PUTX 0 <--
-IS_D_I Data 0 <--
-
-IM_D Load 0 <--
-IM_D Ifetch 0 <--
-IM_D Store 0 <--
-IM_D L1_to_L2 0 <--
-IM_D L2_to_L1D 0 <--
-IM_D L2_to_L1I 0 <--
-IM_D L2_Replacement 0 <--
-IM_D Other_GETS 0 <--
-IM_D Other_GET_INSTR 0 <--
-IM_D Other_GETX 0 <--
-IM_D Other_PUTX 0 <--
-IM_D Data 0 <--
-
-IM_D_O Load 0 <--
-IM_D_O Ifetch 0 <--
-IM_D_O Store 0 <--
-IM_D_O L1_to_L2 0 <--
-IM_D_O L2_to_L1D 0 <--
-IM_D_O L2_to_L1I 0 <--
-IM_D_O L2_Replacement 0 <--
-IM_D_O Other_GETS 0 <--
-IM_D_O Other_GET_INSTR 0 <--
-IM_D_O Other_GETX 0 <--
-IM_D_O Other_PUTX 0 <--
-IM_D_O Data 0 <--
-
-IM_D_I Load 0 <--
-IM_D_I Ifetch 0 <--
-IM_D_I Store 0 <--
-IM_D_I L1_to_L2 0 <--
-IM_D_I L2_to_L1D 0 <--
-IM_D_I L2_to_L1I 0 <--
-IM_D_I L2_Replacement 0 <--
-IM_D_I Other_GETS 0 <--
-IM_D_I Other_GET_INSTR 0 <--
-IM_D_I Other_GETX 0 <--
-IM_D_I Other_PUTX 0 <--
-IM_D_I Data 0 <--
-
-IM_D_OI Load 0 <--
-IM_D_OI Ifetch 0 <--
-IM_D_OI Store 0 <--
-IM_D_OI L1_to_L2 0 <--
-IM_D_OI L2_to_L1D 0 <--
-IM_D_OI L2_to_L1I 0 <--
-IM_D_OI L2_Replacement 0 <--
-IM_D_OI Other_GETS 0 <--
-IM_D_OI Other_GET_INSTR 0 <--
-IM_D_OI Other_GETX 0 <--
-IM_D_OI Other_PUTX 0 <--
-IM_D_OI Data 0 <--
-
-SM_D Load 0 <--
-SM_D Ifetch 0 <--
-SM_D Store 0 <--
-SM_D L1_to_L2 0 <--
-SM_D L2_to_L1D 0 <--
-SM_D L2_to_L1I 0 <--
-SM_D L2_Replacement 0 <--
-SM_D Other_GETS 0 <--
-SM_D Other_GET_INSTR 0 <--
-SM_D Other_GETX 0 <--
-SM_D Other_PUTX 0 <--
-SM_D Data 0 <--
-
-SM_D_O Load 0 <--
-SM_D_O Ifetch 0 <--
-SM_D_O Store 0 <--
-SM_D_O L1_to_L2 0 <--
-SM_D_O L2_to_L1D 0 <--
-SM_D_O L2_to_L1I 0 <--
-SM_D_O L2_Replacement 0 <--
-SM_D_O Other_GETS 0 <--
-SM_D_O Other_GET_INSTR 0 <--
-SM_D_O Other_GETX 0 <--
-SM_D_O Other_PUTX 0 <--
-SM_D_O Data 0 <--
-
- --- Directory ---
- - Event Counts -
-OtherAddress 0
-GETS 0
-GET_INSTR 0
-GETX 0
-PUTX_Owner 0
-PUTX_NotOwner 0
-
- - Transitions -
-C OtherAddress 0 <--
-C GETS 0 <--
-C GET_INSTR 0 <--
-C GETX 0 <--
-
-I GETS 0 <--
-I GET_INSTR 0 <--
-I GETX 0 <--
-I PUTX_NotOwner 0 <--
-
-S GETS 0 <--
-S GET_INSTR 0 <--
-S GETX 0 <--
-S PUTX_NotOwner 0 <--
-
-SS GETS 0 <--
-SS GET_INSTR 0 <--
-SS GETX 0 <--
-SS PUTX_NotOwner 0 <--
-
-OS GETS 0 <--
-OS GET_INSTR 0 <--
-OS GETX 0 <--
-OS PUTX_Owner 0 <--
-OS PUTX_NotOwner 0 <--
-
-OSS GETS 0 <--
-OSS GET_INSTR 0 <--
-OSS GETX 0 <--
-OSS PUTX_Owner 0 <--
-OSS PUTX_NotOwner 0 <--
-
-M GETS 0 <--
-M GET_INSTR 0 <--
-M GETX 0 <--
-M PUTX_Owner 0 <--
-M PUTX_NotOwner 0 <--
-
+++ /dev/null
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "4", "-m", "1", "-s", "1024"]
-print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
-Creating new MessageBuffer for 3 0
-Creating new MessageBuffer for 3 1
-Creating new MessageBuffer for 3 2
-Creating new MessageBuffer for 3 3
-Creating new MessageBuffer for 3 4
-Creating new MessageBuffer for 3 5
-Creating new MessageBuffer for 4 0
-Creating new MessageBuffer for 4 1
-Creating new MessageBuffer for 4 2
-Creating new MessageBuffer for 4 3
-Creating new MessageBuffer for 4 4
-Creating new MessageBuffer for 4 5
-Creating new MessageBuffer for 5 0
-Creating new MessageBuffer for 5 1
-Creating new MessageBuffer for 5 2
-Creating new MessageBuffer for 5 3
-Creating new MessageBuffer for 5 4
-Creating new MessageBuffer for 5 5
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-hack: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jul 6 2009 11:07:18
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:11:25
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby
-Global frequency set at 1000000000000 ticks per second
- Debug: Adding to filter: 'q' (Queue)
-info: Entering event queue @ 0. Starting simulation...
-Init done
-[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 2 completed
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 3 completed
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
-Iteration 4 completed
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 5 completed
-[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 6 completed
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 10 completed
-PASSED :-)
-Exiting @ tick 87713500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 38506 # Simulator instruction rate (inst/s)
-host_mem_usage 1363292 # Number of bytes of host memory used
-host_seconds 17.59 # Real time elapsed on the host
-host_tick_rate 4986293 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 677340 # Number of instructions simulated
-sim_seconds 0.000088 # Number of seconds simulated
-sim_ticks 87713500 # Number of ticks simulated
-system.cpu0.idle_fraction 0.045871 # Percentage of idle cycles
-system.cpu0.not_idle_fraction 0.954129 # Percentage of non-idle cycles
-system.cpu0.numCycles 173308 # number of cpu cycles simulated
-system.cpu0.num_insts 167334 # Number of instructions executed
-system.cpu0.num_refs 58537 # Number of memory references
-system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
-system.cpu1.idle_fraction 0.046241 # Percentage of idle cycles
-system.cpu1.not_idle_fraction 0.953759 # Percentage of non-idle cycles
-system.cpu1.numCycles 173307 # number of cpu cycles simulated
-system.cpu1.num_insts 167269 # Number of instructions executed
-system.cpu1.num_refs 55900 # Number of memory references
-system.cpu2.idle_fraction 0 # Percentage of idle cycles
-system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu2.numCycles 175428 # number of cpu cycles simulated
-system.cpu2.num_insts 175339 # Number of instructions executed
-system.cpu2.num_refs 82398 # Number of memory references
-system.cpu3.idle_fraction 0.045506 # Percentage of idle cycles
-system.cpu3.not_idle_fraction 0.954494 # Percentage of non-idle cycles
-system.cpu3.numCycles 173308 # number of cpu cycles simulated
-system.cpu3.num_insts 167398 # Number of instructions executed
-system.cpu3.num_refs 53394 # Number of memory references
-
----------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu0]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu1]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
+
+[system.cpu2]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
+
+[system.cpu3]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
+num_int_nodes=11
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=1
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=2
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[2]
+port=system.cpu2.test
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links3]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links3.ext_node
+int_node=3
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links3.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=3
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links4]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links4.ext_node
+int_node=4
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links4.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=4
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links5]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links5.ext_node
+int_node=5
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links5.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=5
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links6]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links6.ext_node
+int_node=6
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links6.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=6
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links7]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links7.ext_node
+int_node=7
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links7.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=7
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links8]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links8.ext_node
+int_node=8
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links8.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory
+buffer_size=0
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+recycle_latency=10
+to_l1_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links9]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links9.ext_node
+int_node=9
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links9.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links9.ext_node.directory
+directory_latency=6
+memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+to_mem_ctrl_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links9.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links9.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=3
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=4
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=5
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=6
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=7
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=8
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links9]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=9
+node_b=10
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 13:58:37
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 52
+Elapsed_time_in_minutes: 0.866667
+Elapsed_time_in_hours: 0.0144444
+Elapsed_time_in_days: 0.000601852
+
+Virtual_time_in_seconds: 49.18
+Virtual_time_in_minutes: 0.819667
+Virtual_time_in_hours: 0.0136611
+Virtual_time_in_days: 0.000569213
+
+Ruby_current_time: 3708588
+Ruby_start_time: 0
+Ruby_cycles: 3708588
+
+mbytes_resident: 31.5625
+mbytes_total: 31.5664
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+
+ruby_cycles_executed: 29668712 [ 3708589 3708589 3708589 3708589 3708589 3708589 3708589 3708589 ]
+
+transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
+transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
+cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
+
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1203078 average: 1.94854 | standard deviation: 0.220933 | 0 61909 1141169 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 8 max: 1079 count: 1203063 average: 47.3156 | standard deviation: 87.6351 | 816620 0 0 12702 11269 8948 17837 40884 24865 42456 9079 3638 16674 9433 11140 15717 156 11218 19344 8790 12626 977 6763 8017 7595 3835 2226 8755 5115 7788 3448 877 5397 4166 3570 4056 239 2902 3976 2469 2769 419 2332 2187 2031 1129 378 1933 1318 1530 965 174 1063 1034 801 835 85 664 764 547 416 83 462 404 397 258 47 346 268 218 158 23 172 139 135 115 15 89 94 98 71 16 71 46 49 29 9 40 40 27 28 5 29 20 17 11 2 8 12 17 8 1 5 9 7 1 0 3 2 3 0 0 1 3 1 2 0 2 3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 8 max: 1079 count: 782528 average: 30.8562 | standard deviation: 72.4141 | 623937 0 0 2804 2414 344 17837 15305 10251 19019 256 3637 7241 2137 5293 5719 150 5344 8353 3454 5061 973 1991 3604 2554 434 2225 3489 2021 3344 596 872 2369 1421 1525 1457 236 1143 1709 912 967 419 899 914 781 222 377 798 497 649 263 174 463 393 337 282 85 251 293 198 118 83 186 180 159 69 47 159 94 90 44 23 76 58 54 32 15 35 37 28 19 16 24 21 18 9 9 14 18 9 8 5 9 7 7 4 2 3 9 13 1 1 4 4 2 0 0 1 1 1 0 0 1 2 0 0 0 1 2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 8 max: 946 count: 420535 average: 77.943 | standard deviation: 103.783 | 192683 0 0 9898 8855 8604 0 25579 14614 23437 8823 1 9433 7296 5847 9998 6 5874 10991 5336 7565 4 4772 4413 5041 3401 1 5266 3094 4444 2852 5 3028 2745 2045 2599 3 1759 2267 1557 1802 0 1433 1273 1250 907 1 1135 821 881 702 0 600 641 464 553 0 413 471 349 298 0 276 224 238 189 0 187 174 128 114 0 96 81 81 83 0 54 57 70 52 0 47 25 31 20 0 26 22 18 20 0 20 13 10 7 0 5 3 4 7 0 1 5 5 1 0 2 1 2 0 0 0 1 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 32 max: 1060 count: 1895369 average: 23.6822 | standard deviation: 66.5463 | 1600516 76453 36521 50437 28498 31139 16664 13034 11860 7967 7774 4001 2906 2434 1530 1461 693 443 326 262 174 101 69 30 33 22 6 5 6 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1187979 average: 0.00268523 | standard deviation: 0.0585751 | 1185227 2323 420 9 ]
+ virtual_network_0_delay_cycles: [binsize: 32 max: 1060 count: 707390 average: 63.4492 | standard deviation: 96.6557 | 412537 76453 36521 50437 28498 31139 16664 13034 11860 7967 7774 4001 2906 2434 1530 1461 693 443 326 262 174 101 69 30 33 22 6 5 6 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 3 count: 468144 average: 0.00568415 | standard deviation: 0.0868848 | 465918 1800 417 9 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 719835 average: 0.000734891 | standard deviation: 0.0272622 | 719309 523 3 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 48
+system_time: 0
+page_reclaims: 6918
+page_faults: 1939
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.415271
+ links_utilized_percent_switch_0_link_0: 0.174951 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.65559 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Request_Control: 59248 473984 [ 59248 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 47528 3422016 [ 0 47528 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 32057 256456 [ 0 32057 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 49012 392096 [ 49012 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Data: 40688 2929536 [ 0 40688 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Control: 71059 568472 [ 0 30280 40779 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.417719
+ links_utilized_percent_switch_1_link_0: 0.17501 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.660428 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 59529 476232 [ 59529 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 47490 3419280 [ 0 47490 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Control: 32292 258336 [ 0 32292 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Control: 48960 391680 [ 48960 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 41045 2955240 [ 0 41045 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 71486 571888 [ 0 30524 40962 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.409969
+ links_utilized_percent_switch_2_link_0: 0.173149 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.646789 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Request_Control: 58671 469368 [ 58671 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Data: 47080 3389760 [ 0 47080 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Control: 31320 250560 [ 0 31320 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 48508 388064 [ 48508 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 40095 2886840 [ 0 40095 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Control: 70372 562976 [ 0 30167 40205 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 0.410979
+ links_utilized_percent_switch_3_link_0: 0.172611 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.649347 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Request_Control: 58622 468976 [ 58622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Data: 46898 3376656 [ 0 46898 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 31411 251288 [ 0 31411 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Control: 48355 386840 [ 48355 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 40341 2904552 [ 0 40341 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Control: 70208 561664 [ 0 30006 40202 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 0.410566
+ links_utilized_percent_switch_4_link_0: 0.172947 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_4_link_1: 0.648185 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_4_link_0_Request_Control: 58685 469480 [ 58685 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Response_Data: 46987 3383064 [ 0 46987 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Response_Control: 31543 252344 [ 0 31543 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Control: 48410 387280 [ 48410 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Response_Data: 40214 2895408 [ 0 40214 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Response_Control: 70434 563472 [ 0 30169 40265 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_5_inlinks: 2
+switch_5_outlinks: 2
+links_utilized_percent_switch_5: 0.406856
+ links_utilized_percent_switch_5_link_0: 0.171397 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_5_link_1: 0.642316 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_5_link_0_Request_Control: 58202 465616 [ 58202 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Data: 46584 3354048 [ 0 46584 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Control: 31054 248432 [ 0 31054 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Control: 48013 384104 [ 48013 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Data: 39847 2868984 [ 0 39847 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Control: 69781 558248 [ 0 29974 39807 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_6_inlinks: 2
+switch_6_outlinks: 2
+links_utilized_percent_switch_6: 0.403083
+ links_utilized_percent_switch_6_link_0: 0.170609 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_6_link_1: 0.635556 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_6_link_0_Request_Control: 57792 462336 [ 57792 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Response_Data: 46405 3341160 [ 0 46405 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Response_Control: 30739 245912 [ 0 30739 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Control: 47700 381600 [ 47700 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Response_Data: 39391 2836152 [ 0 39391 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Response_Control: 69184 553472 [ 0 29788 39396 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_7_inlinks: 2
+switch_7_outlinks: 2
+links_utilized_percent_switch_7: 0.401771
+ links_utilized_percent_switch_7_link_0: 0.169663 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_7_link_1: 0.63388 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_7_link_0_Request_Control: 57395 459160 [ 57395 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Response_Data: 46078 3317616 [ 0 46078 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Response_Control: 31270 250160 [ 0 31270 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Control: 47499 379992 [ 47499 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Response_Data: 39327 2831544 [ 0 39327 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Response_Control: 68718 549744 [ 0 29385 39333 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_8_inlinks: 2
+switch_8_outlinks: 2
+links_utilized_percent_switch_8: 1.37752
+ links_utilized_percent_switch_8_link_0: 0.52085 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_8_link_1: 2.23418 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_8_link_0_Control: 386457 3091656 [ 386457 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_0_Response_Data: 93099 6703128 [ 0 93099 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_0_Response_Control: 320947 2567576 [ 0 0 320947 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Request_Control: 320947 2567576 [ 320947 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Response_Data: 147199 10598328 [ 0 147199 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Response_Control: 11393 91144 [ 0 11393 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 2
+switch_9_outlinks: 2
+links_utilized_percent_switch_9: 1.24711e-05
+ links_utilized_percent_switch_9_link_0: 6.74111e-07 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_9_link_1: 2.4268e-05 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_9_link_0_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_10_inlinks: 10
+switch_10_outlinks: 10
+links_utilized_percent_switch_10: 0.760475
+ links_utilized_percent_switch_10_link_0: 0.699804 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_1: 0.700039 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_2: 0.692596 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_3: 0.690445 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_4: 0.691788 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_5: 0.685587 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_6: 0.682438 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_7: 0.67865 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_8: 2.0834 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_9: 2.69644e-06 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_10_link_0_Request_Control: 59248 473984 [ 59248 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_Response_Data: 47528 3422016 [ 0 47528 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_Response_Control: 32057 256456 [ 0 32057 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Request_Control: 59529 476232 [ 59529 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Response_Data: 47490 3419280 [ 0 47490 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Response_Control: 32292 258336 [ 0 32292 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Request_Control: 58671 469368 [ 58671 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Response_Data: 47080 3389760 [ 0 47080 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Response_Control: 31320 250560 [ 0 31320 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Request_Control: 58622 468976 [ 58622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Response_Data: 46898 3376656 [ 0 46898 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Response_Control: 31411 251288 [ 0 31411 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Request_Control: 58685 469480 [ 58685 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Response_Data: 46987 3383064 [ 0 46987 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Response_Control: 31543 252344 [ 0 31543 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Request_Control: 58202 465616 [ 58202 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Response_Data: 46584 3354048 [ 0 46584 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Response_Control: 31054 248432 [ 0 31054 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Request_Control: 57792 462336 [ 57792 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Response_Data: 46405 3341160 [ 0 46405 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Response_Control: 30739 245912 [ 0 30739 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Request_Control: 57395 459160 [ 57395 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Response_Data: 46078 3317616 [ 0 46078 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Response_Control: 31270 250160 [ 0 31270 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_8_Control: 386457 3091656 [ 386457 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_8_Response_Data: 93099 6703128 [ 0 93099 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_8_Response_Control: 320948 2567584 [ 0 0 320948 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_9_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 98992
+Ifetch 0
+Store 53492
+Inv 30280
+L1_Replacement 0
+Fwd_GETX 17248
+Fwd_GETS 11720
+Fwd_GET_INSTR 0
+Data 10425
+Data_Exclusive 0
+DataS_fromL1 11811
+Data_all_Acks 25292
+Ack 20150
+Ack_all 11907
+WB_Ack 0
+
+ - Transitions -
+NP Load 1
+NP Ifetch 0 <--
+NP Store 1
+NP Inv 0 <--
+NP L1_Replacement 0 <--
+
+I Load 20042
+I Ifetch 0 <--
+I Store 10889
+I Inv 0 <--
+I L1_Replacement 0 <--
+
+S Load 33193
+S Ifetch 0 <--
+S Store 18079
+S Inv 11462
+S L1_Replacement 0 <--
+
+E Load 0 <--
+E Ifetch 0 <--
+E Store 0 <--
+E Inv 0 <--
+E L1_Replacement 0 <--
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 45756
+M Ifetch 0 <--
+M Store 24523
+M Inv 0 <--
+M L1_Replacement 0 <--
+M Fwd_GETX 17248
+M Fwd_GETS 11720
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 2221
+IS L1_Replacement 0 <--
+IS Data_Exclusive 0 <--
+IS DataS_fromL1 11811
+IS Data_all_Acks 6010
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 10425
+IM Data_all_Acks 17061
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 16597
+SM L1_Replacement 0 <--
+SM Ack 20150
+SM Ack_all 11907
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 2221
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 0 <--
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 1 ---
+ - Event Counts -
+Load 100000
+Ifetch 0
+Store 53369
+Inv 30524
+L1_Replacement 0
+Fwd_GETX 16965
+Fwd_GETS 12040
+Fwd_GET_INSTR 0
+Data 10436
+Data_Exclusive 0
+DataS_fromL1 11957
+Data_all_Acks 25097
+Ack 20387
+Ack_all 11905
+WB_Ack 0
+
+ - Transitions -
+NP Load 0 <--
+NP Ifetch 0 <--
+NP Store 2
+NP Inv 0 <--
+NP L1_Replacement 0 <--
+
+I Load 19954
+I Ifetch 0 <--
+I Store 10627
+I Inv 0 <--
+I L1_Replacement 0 <--
+
+S Load 34113
+S Ifetch 0 <--
+S Store 18377
+S Inv 11476
+S L1_Replacement 0 <--
+
+E Load 0 <--
+E Ifetch 0 <--
+E Store 0 <--
+E Inv 0 <--
+E L1_Replacement 0 <--
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 45933
+M Ifetch 0 <--
+M Store 24363
+M Inv 0 <--
+M L1_Replacement 0 <--
+M Fwd_GETX 16965
+M Fwd_GETS 12040
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 2140
+IS L1_Replacement 0 <--
+IS Data_Exclusive 0 <--
+IS DataS_fromL1 11957
+IS Data_all_Acks 5857
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 10436
+IM Data_all_Acks 17100
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 16908
+SM L1_Replacement 0 <--
+SM Ack 20387
+SM Ack_all 11905
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 2140
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 0 <--
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 2 ---
+ - Event Counts -
+Load 98060
+Ifetch 0
+Store 52567
+Inv 30167
+L1_Replacement 0
+Fwd_GETX 16913
+Fwd_GETS 11591
+Fwd_GET_INSTR 0
+Data 10258
+Data_Exclusive 0
+DataS_fromL1 11701
+Data_all_Acks 25121
+Ack 19636
+Ack_all 11684
+WB_Ack 0
+
+ - Transitions -
+NP Load 1
+NP Ifetch 0 <--
+NP Store 1
+NP Inv 0 <--
+NP L1_Replacement 0 <--
+
+I Load 20002
+I Ifetch 0 <--
+I Store 10728
+I Inv 0 <--
+I L1_Replacement 0 <--
+
+S Load 32916
+S Ifetch 0 <--
+S Store 17776
+S Inv 11648
+S L1_Replacement 0 <--
+
+E Load 0 <--
+E Ifetch 0 <--
+E Store 0 <--
+E Inv 0 <--
+E L1_Replacement 0 <--
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 45141
+M Ifetch 0 <--
+M Store 24062
+M Inv 0 <--
+M L1_Replacement 0 <--
+M Fwd_GETX 16913
+M Fwd_GETS 11591
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 2169
+IS L1_Replacement 0 <--
+IS Data_Exclusive 0 <--
+IS DataS_fromL1 11701
+IS Data_all_Acks 6132
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 10258
+IM Data_all_Acks 16820
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 16350
+SM L1_Replacement 0 <--
+SM Ack 19636
+SM Ack_all 11684
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 2169
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 0 <--
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 3 ---
+ - Event Counts -
+Load 97980
+Ifetch 0
+Store 52707
+Inv 30006
+L1_Replacement 0
+Fwd_GETX 16891
+Fwd_GETS 11725
+Fwd_GET_INSTR 0
+Data 10169
+Data_Exclusive 0
+DataS_fromL1 11586
+Data_all_Acks 25143
+Ack 19787
+Ack_all 11624
+WB_Ack 0
+
+ - Transitions -
+NP Load 2
+NP Ifetch 0 <--
+NP Store 0 <--
+NP Inv 0 <--
+NP L1_Replacement 0 <--
+
+I Load 19735
+I Ifetch 0 <--
+I Store 10745
+I Inv 0 <--
+I L1_Replacement 0 <--
+
+S Load 33032
+S Ifetch 0 <--
+S Store 17873
+S Inv 11501
+S L1_Replacement 0 <--
+
+E Load 0 <--
+E Ifetch 0 <--
+E Store 0 <--
+E Inv 0 <--
+E L1_Replacement 0 <--
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 45211
+M Ifetch 0 <--
+M Store 24089
+M Inv 0 <--
+M L1_Replacement 0 <--
+M Fwd_GETX 16891
+M Fwd_GETS 11725
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 2088
+IS L1_Replacement 0 <--
+IS Data_Exclusive 0 <--
+IS DataS_fromL1 11586
+IS Data_all_Acks 6063
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 10169
+IM Data_all_Acks 16992
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 16417
+SM L1_Replacement 0 <--
+SM Ack 19787
+SM Ack_all 11624
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 2088
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 0 <--
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 4 ---
+ - Event Counts -
+Load 98002
+Ifetch 0
+Store 52774
+Inv 30169
+L1_Replacement 0
+Fwd_GETX 16818
+Fwd_GETS 11698
+Fwd_GET_INSTR 0
+Data 10198
+Data_Exclusive 0
+DataS_fromL1 11749
+Data_all_Acks 25040
+Ack 19924
+Ack_all 11619
+WB_Ack 0
+
+ - Transitions -
+NP Load 0 <--
+NP Ifetch 0 <--
+NP Store 2
+NP Inv 0 <--
+NP L1_Replacement 0 <--
+
+I Load 19894
+I Ifetch 0 <--
+I Store 10660
+I Inv 0 <--
+I L1_Replacement 0 <--
+
+S Load 33230
+S Ifetch 0 <--
+S Store 17854
+S Inv 11630
+S L1_Replacement 0 <--
+
+E Load 0 <--
+E Ifetch 0 <--
+E Store 0 <--
+E Inv 0 <--
+E L1_Replacement 0 <--
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 44878
+M Ifetch 0 <--
+M Store 24258
+M Inv 0 <--
+M L1_Replacement 0 <--
+M Fwd_GETX 16818
+M Fwd_GETS 11698
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 2106
+IS L1_Replacement 0 <--
+IS Data_Exclusive 0 <--
+IS DataS_fromL1 11749
+IS Data_all_Acks 6037
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 10198
+IM Data_all_Acks 16897
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 16433
+SM L1_Replacement 0 <--
+SM Ack 19924
+SM Ack_all 11619
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 2106
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 0 <--
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 5 ---
+ - Event Counts -
+Load 97409
+Ifetch 0
+Store 52454
+Inv 29974
+L1_Replacement 0
+Fwd_GETX 16609
+Fwd_GETS 11619
+Fwd_GET_INSTR 0
+Data 10002
+Data_Exclusive 0
+DataS_fromL1 11578
+Data_all_Acks 25004
+Ack 19624
+Ack_all 11430
+WB_Ack 0
+
+ - Transitions -
+NP Load 1
+NP Ifetch 0 <--
+NP Store 1
+NP Inv 0 <--
+NP L1_Replacement 0 <--
+
+I Load 19782
+I Ifetch 0 <--
+I Store 10572
+I Inv 0 <--
+I L1_Replacement 0 <--
+
+S Load 33224
+S Ifetch 0 <--
+S Store 17657
+S Inv 11591
+S L1_Replacement 0 <--
+
+E Load 0 <--
+E Ifetch 0 <--
+E Store 0 <--
+E Inv 0 <--
+E L1_Replacement 0 <--
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 44402
+M Ifetch 0 <--
+M Store 24224
+M Inv 0 <--
+M L1_Replacement 0 <--
+M Fwd_GETX 16609
+M Fwd_GETS 11619
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 2154
+IS L1_Replacement 0 <--
+IS Data_Exclusive 0 <--
+IS DataS_fromL1 11578
+IS Data_all_Acks 6051
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 10002
+IM Data_all_Acks 16799
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 16229
+SM L1_Replacement 0 <--
+SM Ack 19624
+SM Ack_all 11430
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 2154
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 0 <--
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 6 ---
+ - Event Counts -
+Load 96359
+Ifetch 0
+Store 51489
+Inv 29788
+L1_Replacement 0
+Fwd_GETX 16617
+Fwd_GETS 11387
+Fwd_GET_INSTR 0
+Data 10074
+Data_Exclusive 0
+DataS_fromL1 11392
+Data_all_Acks 24939
+Ack 19372
+Ack_all 11367
+WB_Ack 0
+
+ - Transitions -
+NP Load 2
+NP Ifetch 0 <--
+NP Store 0 <--
+NP Inv 0 <--
+NP L1_Replacement 0 <--
+
+I Load 19693
+I Ifetch 0 <--
+I Store 10572
+I Inv 0 <--
+I L1_Replacement 0 <--
+
+S Load 32214
+S Ifetch 0 <--
+S Store 17433
+S Inv 11564
+S L1_Replacement 0 <--
+
+E Load 0 <--
+E Ifetch 0 <--
+E Store 0 <--
+E Inv 0 <--
+E L1_Replacement 0 <--
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 44450
+M Ifetch 0 <--
+M Store 23484
+M Inv 0 <--
+M L1_Replacement 0 <--
+M Fwd_GETX 16617
+M Fwd_GETS 11387
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 2084
+IS L1_Replacement 0 <--
+IS Data_Exclusive 0 <--
+IS DataS_fromL1 11392
+IS Data_all_Acks 6218
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 10074
+IM Data_all_Acks 16637
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 16140
+SM L1_Replacement 0 <--
+SM Ack 19372
+SM Ack_all 11367
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 2084
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 0 <--
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 7 ---
+ - Event Counts -
+Load 95733
+Ifetch 0
+Store 51690
+Inv 29385
+L1_Replacement 0
+Fwd_GETX 16693
+Fwd_GETS 11317
+Fwd_GET_INSTR 0
+Data 10141
+Data_Exclusive 0
+DataS_fromL1 11323
+Data_all_Acks 24614
+Ack 19710
+Ack_all 11560
+WB_Ack 0
+
+ - Transitions -
+NP Load 1
+NP Ifetch 0 <--
+NP Store 1
+NP Inv 0 <--
+NP L1_Replacement 0 <--
+
+I Load 19488
+I Ifetch 0 <--
+I Store 10620
+I Inv 0 <--
+I L1_Replacement 0 <--
+
+S Load 32018
+S Ifetch 0 <--
+S Store 17389
+S Inv 11338
+S L1_Replacement 0 <--
+
+E Load 0 <--
+E Ifetch 0 <--
+E Store 0 <--
+E Inv 0 <--
+E L1_Replacement 0 <--
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 44226
+M Ifetch 0 <--
+M Store 23680
+M Inv 0 <--
+M L1_Replacement 0 <--
+M Fwd_GETX 16693
+M Fwd_GETS 11317
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 2077
+IS L1_Replacement 0 <--
+IS Data_Exclusive 0 <--
+IS DataS_fromL1 11323
+IS Data_all_Acks 6087
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 0 <--
+IM Data 10141
+IM Data_all_Acks 16450
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 15970
+SM L1_Replacement 0 <--
+SM Ack 19710
+SM Ack_all 11560
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 2077
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 0 <--
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 0 <--
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GET_INSTR 0
+L1_GETS 2019575
+L1_GETX 2540990
+L1_UPGRADE 314372
+L1_PUTX 0
+L1_PUTX_old 0
+Fwd_L1_GETX 0
+Fwd_L1_GETS 0
+Fwd_L1_GET_INSTR 0
+L2_Replacement 0
+L2_Replacement_clean 0
+Mem_Data 2
+Mem_Ack 0
+WB_Data 93097
+WB_Data_clean 0
+Ack 0
+Ack_all 0
+Unblock 93096
+Unblock_Cancel 0
+Exclusive_Unblock 227851
+MEM_Inv 0
+
+ - Transitions -
+NP L1_GET_INSTR 0 <--
+NP L1_GETS 0 <--
+NP L1_GETX 2
+NP L1_PUTX 0 <--
+NP L1_PUTX_old 0 <--
+
+SS L1_GET_INSTR 0 <--
+SS L1_GETS 65494
+SS L1_GETX 81703
+SS L1_UPGRADE 11393
+SS L1_PUTX 0 <--
+SS L1_PUTX_old 0 <--
+SS L2_Replacement 0 <--
+SS L2_Replacement_clean 0 <--
+SS MEM_Inv 0 <--
+
+M L1_GET_INSTR 0 <--
+M L1_GETS 0 <--
+M L1_GETX 0 <--
+M L1_PUTX 0 <--
+M L1_PUTX_old 0 <--
+M L2_Replacement 0 <--
+M L2_Replacement_clean 0 <--
+M MEM_Inv 0 <--
+
+MT L1_GET_INSTR 0 <--
+MT L1_GETS 93097
+MT L1_GETX 134754
+MT L1_PUTX 0 <--
+MT L1_PUTX_old 0 <--
+MT L2_Replacement 0 <--
+MT L2_Replacement_clean 0 <--
+MT MEM_Inv 0 <--
+
+M_I L1_GET_INSTR 0 <--
+M_I L1_GETS 0 <--
+M_I L1_GETX 0 <--
+M_I L1_UPGRADE 0 <--
+M_I L1_PUTX 0 <--
+M_I L1_PUTX_old 0 <--
+M_I Mem_Ack 0 <--
+M_I MEM_Inv 0 <--
+
+MT_I L1_GET_INSTR 0 <--
+MT_I L1_GETS 0 <--
+MT_I L1_GETX 0 <--
+MT_I L1_UPGRADE 0 <--
+MT_I L1_PUTX 0 <--
+MT_I L1_PUTX_old 0 <--
+MT_I WB_Data 0 <--
+MT_I WB_Data_clean 0 <--
+MT_I Ack_all 0 <--
+MT_I MEM_Inv 0 <--
+
+MCT_I L1_GET_INSTR 0 <--
+MCT_I L1_GETS 0 <--
+MCT_I L1_GETX 0 <--
+MCT_I L1_UPGRADE 0 <--
+MCT_I L1_PUTX 0 <--
+MCT_I L1_PUTX_old 0 <--
+MCT_I WB_Data 0 <--
+MCT_I WB_Data_clean 0 <--
+MCT_I Ack_all 0 <--
+
+I_I L1_GET_INSTR 0 <--
+I_I L1_GETS 0 <--
+I_I L1_GETX 0 <--
+I_I L1_UPGRADE 0 <--
+I_I L1_PUTX 0 <--
+I_I L1_PUTX_old 0 <--
+I_I Ack 0 <--
+I_I Ack_all 0 <--
+
+S_I L1_GET_INSTR 0 <--
+S_I L1_GETS 0 <--
+S_I L1_GETX 0 <--
+S_I L1_UPGRADE 0 <--
+S_I L1_PUTX 0 <--
+S_I L1_PUTX_old 0 <--
+S_I Ack 0 <--
+S_I Ack_all 0 <--
+S_I MEM_Inv 0 <--
+
+ISS L1_GET_INSTR 0 <--
+ISS L1_GETS 0 <--
+ISS L1_GETX 0 <--
+ISS L1_PUTX 0 <--
+ISS L1_PUTX_old 0 <--
+ISS L2_Replacement 0 <--
+ISS L2_Replacement_clean 0 <--
+ISS Mem_Data 0 <--
+ISS MEM_Inv 0 <--
+
+IS L1_GET_INSTR 0 <--
+IS L1_GETS 0 <--
+IS L1_GETX 0 <--
+IS L1_PUTX 0 <--
+IS L1_PUTX_old 0 <--
+IS L2_Replacement 0 <--
+IS L2_Replacement_clean 0 <--
+IS Mem_Data 0 <--
+IS MEM_Inv 0 <--
+
+IM L1_GET_INSTR 0 <--
+IM L1_GETS 244
+IM L1_GETX 183
+IM L1_PUTX 0 <--
+IM L1_PUTX_old 0 <--
+IM L2_Replacement 0 <--
+IM L2_Replacement_clean 0 <--
+IM Mem_Data 2
+IM MEM_Inv 0 <--
+
+SS_MB L1_GET_INSTR 0 <--
+SS_MB L1_GETS 467835
+SS_MB L1_GETX 561825
+SS_MB L1_UPGRADE 262405
+SS_MB L1_PUTX 0 <--
+SS_MB L1_PUTX_old 0 <--
+SS_MB L2_Replacement 0 <--
+SS_MB L2_Replacement_clean 0 <--
+SS_MB Unblock_Cancel 0 <--
+SS_MB Exclusive_Unblock 93096
+SS_MB MEM_Inv 0 <--
+
+MT_MB L1_GET_INSTR 0 <--
+MT_MB L1_GETS 856021
+MT_MB L1_GETX 1061989
+MT_MB L1_UPGRADE 0 <--
+MT_MB L1_PUTX 0 <--
+MT_MB L1_PUTX_old 0 <--
+MT_MB L2_Replacement 0 <--
+MT_MB L2_Replacement_clean 0 <--
+MT_MB Unblock_Cancel 0 <--
+MT_MB Exclusive_Unblock 134755
+MT_MB MEM_Inv 0 <--
+
+M_MB L1_GET_INSTR 0 <--
+M_MB L1_GETS 0 <--
+M_MB L1_GETX 0 <--
+M_MB L1_UPGRADE 0 <--
+M_MB L1_PUTX 0 <--
+M_MB L1_PUTX_old 0 <--
+M_MB L2_Replacement 0 <--
+M_MB L2_Replacement_clean 0 <--
+M_MB Exclusive_Unblock 0 <--
+M_MB MEM_Inv 0 <--
+
+MT_IIB L1_GET_INSTR 0 <--
+MT_IIB L1_GETS 382910
+MT_IIB L1_GETX 496747
+MT_IIB L1_UPGRADE 0 <--
+MT_IIB L1_PUTX 0 <--
+MT_IIB L1_PUTX_old 0 <--
+MT_IIB L2_Replacement 0 <--
+MT_IIB L2_Replacement_clean 0 <--
+MT_IIB WB_Data 93097
+MT_IIB WB_Data_clean 0 <--
+MT_IIB Unblock 0 <--
+MT_IIB MEM_Inv 0 <--
+
+MT_IB L1_GET_INSTR 0 <--
+MT_IB L1_GETS 0 <--
+MT_IB L1_GETX 0 <--
+MT_IB L1_UPGRADE 0 <--
+MT_IB L1_PUTX 0 <--
+MT_IB L1_PUTX_old 0 <--
+MT_IB L2_Replacement 0 <--
+MT_IB L2_Replacement_clean 0 <--
+MT_IB WB_Data 0 <--
+MT_IB WB_Data_clean 0 <--
+MT_IB Unblock_Cancel 0 <--
+MT_IB MEM_Inv 0 <--
+
+MT_SB L1_GET_INSTR 0 <--
+MT_SB L1_GETS 153974
+MT_SB L1_GETX 203787
+MT_SB L1_UPGRADE 40574
+MT_SB L1_PUTX 0 <--
+MT_SB L1_PUTX_old 0 <--
+MT_SB L2_Replacement 0 <--
+MT_SB L2_Replacement_clean 0 <--
+MT_SB Unblock 93096
+MT_SB MEM_Inv 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer:
+ memory_total_requests: 2
+ memory_reads: 2
+ memory_writes: 0
+ memory_refreshes: 22
+ memory_total_request_delays: 31
+ memory_delays_per_request: 15.5
+ memory_delays_in_input_queue: 1
+ memory_delays_behind_head_of_bank_queue: 10
+ memory_delays_stalled_at_head_of_bank_queue: 20
+ memory_stalls_for_bank_busy: 20
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 0
+ memory_stalls_for_bus: 0
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 0
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+
+ --- Directory 0 ---
+ - Event Counts -
+Fetch 2
+Data 0
+Memory_Data 2
+Memory_Ack 0
+DMA_READ 0
+DMA_WRITE 0
+CleanReplacement 0
+
+ - Transitions -
+I Fetch 2
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+ID Fetch 0 <--
+ID Data 0 <--
+ID Memory_Data 0 <--
+ID DMA_READ 0 <--
+ID DMA_WRITE 0 <--
+
+ID_W Fetch 0 <--
+ID_W Data 0 <--
+ID_W Memory_Ack 0 <--
+ID_W DMA_READ 0 <--
+ID_W DMA_WRITE 0 <--
+
+M Data 0 <--
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+M CleanReplacement 0 <--
+
+IM Fetch 0 <--
+IM Data 0 <--
+IM Memory_Data 2
+IM DMA_READ 0 <--
+IM DMA_WRITE 0 <--
+
+MI Fetch 0 <--
+MI Data 0 <--
+MI Memory_Ack 0 <--
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+
+M_DRD Data 0 <--
+M_DRD DMA_READ 0 <--
+M_DRD DMA_WRITE 0 <--
+
+M_DRDI Fetch 0 <--
+M_DRDI Data 0 <--
+M_DRDI Memory_Ack 0 <--
+M_DRDI DMA_READ 0 <--
+M_DRDI DMA_WRITE 0 <--
+
+M_DWR Data 0 <--
+M_DWR DMA_READ 0 <--
+M_DWR DMA_WRITE 0 <--
+
+M_DWRI Fetch 0 <--
+M_DWRI Data 0 <--
+M_DWRI Memory_Ack 0 <--
+M_DWRI DMA_READ 0 <--
+M_DWRI DMA_WRITE 0 <--
+
--- /dev/null
+system.cpu1: completed 10000 read accesses @369045
+system.cpu3: completed 10000 read accesses @375134
+system.cpu0: completed 10000 read accesses @379333
+system.cpu4: completed 10000 read accesses @381010
+system.cpu2: completed 10000 read accesses @382842
+system.cpu6: completed 10000 read accesses @383698
+system.cpu7: completed 10000 read accesses @384995
+system.cpu5: completed 10000 read accesses @385374
+system.cpu1: completed 20000 read accesses @741171
+system.cpu4: completed 20000 read accesses @750155
+system.cpu0: completed 20000 read accesses @752751
+system.cpu3: completed 20000 read accesses @756635
+system.cpu2: completed 20000 read accesses @759675
+system.cpu6: completed 20000 read accesses @761608
+system.cpu7: completed 20000 read accesses @768000
+system.cpu5: completed 20000 read accesses @768371
+system.cpu1: completed 30000 read accesses @1110388
+system.cpu4: completed 30000 read accesses @1123036
+system.cpu0: completed 30000 read accesses @1128110
+system.cpu2: completed 30000 read accesses @1137867
+system.cpu3: completed 30000 read accesses @1139088
+system.cpu6: completed 30000 read accesses @1142556
+system.cpu7: completed 30000 read accesses @1150467
+system.cpu5: completed 30000 read accesses @1151106
+system.cpu1: completed 40000 read accesses @1490114
+system.cpu0: completed 40000 read accesses @1493155
+system.cpu4: completed 40000 read accesses @1497187
+system.cpu2: completed 40000 read accesses @1515309
+system.cpu3: completed 40000 read accesses @1515741
+system.cpu6: completed 40000 read accesses @1525379
+system.cpu5: completed 40000 read accesses @1530541
+system.cpu7: completed 40000 read accesses @1538741
+system.cpu1: completed 50000 read accesses @1860332
+system.cpu0: completed 50000 read accesses @1867591
+system.cpu4: completed 50000 read accesses @1873458
+system.cpu2: completed 50000 read accesses @1899397
+system.cpu3: completed 50000 read accesses @1900017
+system.cpu5: completed 50000 read accesses @1912488
+system.cpu6: completed 50000 read accesses @1915555
+system.cpu7: completed 50000 read accesses @1922782
+system.cpu1: completed 60000 read accesses @2238333
+system.cpu0: completed 60000 read accesses @2244218
+system.cpu4: completed 60000 read accesses @2255037
+system.cpu2: completed 60000 read accesses @2274576
+system.cpu3: completed 60000 read accesses @2274764
+system.cpu5: completed 60000 read accesses @2298934
+system.cpu6: completed 60000 read accesses @2309075
+system.cpu7: completed 60000 read accesses @2323339
+system.cpu1: completed 70000 read accesses @2600904
+system.cpu0: completed 70000 read accesses @2622809
+system.cpu4: completed 70000 read accesses @2633148
+system.cpu2: completed 70000 read accesses @2650372
+system.cpu3: completed 70000 read accesses @2661632
+system.cpu5: completed 70000 read accesses @2678675
+system.cpu6: completed 70000 read accesses @2697088
+system.cpu7: completed 70000 read accesses @2711986
+system.cpu1: completed 80000 read accesses @2969240
+system.cpu0: completed 80000 read accesses @2991652
+system.cpu4: completed 80000 read accesses @3015607
+system.cpu2: completed 80000 read accesses @3020165
+system.cpu3: completed 80000 read accesses @3040093
+system.cpu5: completed 80000 read accesses @3054431
+system.cpu6: completed 80000 read accesses @3090505
+system.cpu7: completed 80000 read accesses @3105496
+system.cpu1: completed 90000 read accesses @3338659
+system.cpu0: completed 90000 read accesses @3373927
+system.cpu2: completed 90000 read accesses @3397759
+system.cpu4: completed 90000 read accesses @3398901
+system.cpu3: completed 90000 read accesses @3408631
+system.cpu5: completed 90000 read accesses @3430133
+system.cpu6: completed 90000 read accesses @3467538
+system.cpu7: completed 90000 read accesses @3493036
+system.cpu1: completed 100000 read accesses @3708588
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 13:54:58
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 13:57:45
+M5 executing on svvint03
+command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 3708588 because maximum number of loads reached
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 344972 # Number of bytes of host memory used
+host_seconds 51.38 # Real time elapsed on the host
+host_tick_rate 72178 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.003709 # Number of seconds simulated
+sim_ticks 3708588 # Number of ticks simulated
+system.cpu0.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 98991 # number of read accesses completed
+system.cpu0.num_writes 53491 # number of write accesses completed
+system.cpu1.num_copies 0 # number of copy accesses completed
+system.cpu1.num_reads 100000 # number of read accesses completed
+system.cpu1.num_writes 53368 # number of write accesses completed
+system.cpu2.num_copies 0 # number of copy accesses completed
+system.cpu2.num_reads 98059 # number of read accesses completed
+system.cpu2.num_writes 52566 # number of write accesses completed
+system.cpu3.num_copies 0 # number of copy accesses completed
+system.cpu3.num_reads 97980 # number of read accesses completed
+system.cpu3.num_writes 52705 # number of write accesses completed
+system.cpu4.num_copies 0 # number of copy accesses completed
+system.cpu4.num_reads 98000 # number of read accesses completed
+system.cpu4.num_writes 52774 # number of write accesses completed
+system.cpu5.num_copies 0 # number of copy accesses completed
+system.cpu5.num_reads 97409 # number of read accesses completed
+system.cpu5.num_writes 52453 # number of write accesses completed
+system.cpu6.num_copies 0 # number of copy accesses completed
+system.cpu6.num_reads 96358 # number of read accesses completed
+system.cpu6.num_writes 51488 # number of write accesses completed
+system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu7.num_reads 95731 # number of read accesses completed
+system.cpu7.num_writes 51690 # number of write accesses completed
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu0]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu1]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
+
+[system.cpu2]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
+
+[system.cpu3]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
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+
+[system.ruby]
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+network=system.ruby.network
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+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
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+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
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+children=topology
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+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
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+
+[system.ruby.network.topology]
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+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
+num_int_nodes=11
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
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+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
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+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+buffer_size=0
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+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
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+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
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+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
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+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
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+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L1Cache_Controller
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+L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
+transitions_per_cycle=32
+version=1
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
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+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
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+request_latency=2
+sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer
+transitions_per_cycle=32
+version=2
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
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+deadlock_threshold=500000
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+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[2]
+port=system.cpu2.test
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache]
+type=RubyCache
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+size=256
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
+type=RubyCache
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+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links3]
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+int_node=3
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+
+[system.ruby.network.topology.ext_links3.ext_node]
+type=L1Cache_Controller
+children=sequencer
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+L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+buffer_size=0
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+number_of_TBEs=256
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+sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer
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+version=3
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
+deadlock_threshold=500000
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+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache]
+type=RubyCache
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+size=256
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
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+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links4]
+type=ExtLink
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+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links4.ext_node
+int_node=4
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links4.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
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+sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer
+transitions_per_cycle=32
+version=4
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
+deadlock_threshold=500000
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+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links5]
+type=ExtLink
+children=ext_node
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+ext_node=system.ruby.network.topology.ext_links5.ext_node
+int_node=5
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links5.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer
+transitions_per_cycle=32
+version=5
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links6]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links6.ext_node
+int_node=6
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links6.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
+transitions_per_cycle=32
+version=6
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links7]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links7.ext_node
+int_node=7
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links7.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
+transitions_per_cycle=32
+version=7
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links8]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links8.ext_node
+int_node=8
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links8.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory
+buffer_size=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+response_latency=2
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links9]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links9.ext_node
+int_node=9
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links9.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links9.ext_node.directory
+directory_latency=6
+memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links9.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links9.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=3
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=4
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=5
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=6
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=7
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=8
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links9]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=9
+node_b=10
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 15:08:53
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 37
+Elapsed_time_in_minutes: 0.616667
+Elapsed_time_in_hours: 0.0102778
+Elapsed_time_in_days: 0.000428241
+
+Virtual_time_in_seconds: 35.3
+Virtual_time_in_minutes: 0.588333
+Virtual_time_in_hours: 0.00980556
+Virtual_time_in_days: 0.000408565
+
+Ruby_current_time: 3340930
+Ruby_start_time: 0
+Ruby_cycles: 3340930
+
+mbytes_resident: 31.6562
+mbytes_total: 31.6602
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+
+ruby_cycles_executed: 26727448 [ 3340931 3340931 3340931 3340931 3340931 3340931 3340931 3340931 ]
+
+transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
+transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
+cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+
+
+Busy Controller Counts:
+L2Cache-0:0
+L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
+
+
+Directory-0:0
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1209372 average: 1.94335 | standard deviation: 0.231168 | 0 68507 1140865 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 32 max: 4298 count: 1209357 average: 42.1968 | standard deviation: 176.791 | 1106640 85 18037 216 3595 192 19765 106 4791 343 9697 145 6094 246 4395 177 5289 130 2755 493 3644 182 1723 1274 2161 279 1230 1187 1214 683 921 916 558 978 682 652 451 708 490 526 332 565 216 523 271 401 195 361 168 295 137 255 107 233 97 185 83 130 77 140 51 93 52 81 48 66 36 58 43 46 28 38 20 30 16 24 17 27 11 18 9 8 10 13 14 8 6 8 4 8 4 4 4 5 4 1 1 3 0 3 2 3 1 1 0 1 0 0 0 0 0 3 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 32 max: 3807 count: 785687 average: 41.6957 | standard deviation: 175.435 | 719594 3 11712 167 2248 90 12821 47 3129 162 6289 73 3953 181 2740 100 3449 65 1950 107 2369 108 1103 808 1394 175 818 770 951 249 577 570 369 659 408 414 289 478 380 302 198 354 139 341 162 256 121 216 124 177 82 180 70 165 58 126 57 82 50 84 24 53 37 59 22 37 25 33 29 24 18 31 15 20 8 12 10 15 8 15 5 3 5 7 9 4 5 7 2 3 3 3 2 2 2 1 1 2 0 1 2 2 1 1 0 1 0 0 0 0 0 2 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 32 max: 4298 count: 423670 average: 43.126 | standard deviation: 179.276 | 387046 82 6325 49 1347 102 6944 59 1662 181 3408 72 2141 65 1655 77 1840 65 805 386 1275 74 620 466 767 104 412 417 263 434 344 346 189 319 274 238 162 230 110 224 134 211 77 182 109 145 74 145 44 118 55 75 37 68 39 59 26 48 27 56 27 40 15 22 26 29 11 25 14 22 10 7 5 10 8 12 7 12 3 3 4 5 5 6 5 4 1 1 2 5 1 1 2 3 2 0 0 1 0 2 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 34
+system_time: 0
+page_reclaims: 6907
+page_faults: 1977
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.131151
+ links_utilized_percent_switch_0_link_0: 0.0499779 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.212324 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseLocal_Data: 12884 927648 [ 0 0 12884 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 4640 37120 [ 0 0 4640 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Forwarded_Control: 12897 103176 [ 12897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Invalidate_Control: 76 608 [ 76 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 12894 103152 [ 12894 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_ResponseLocal_Data: 12890 928080 [ 0 0 12890 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Control: 76 608 [ 0 0 76 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 12892 103136 [ 0 0 12892 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.132697
+ links_utilized_percent_switch_1_link_0: 0.0505836 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.21481 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_ResponseLocal_Data: 13033 938376 [ 0 0 13033 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Control: 4750 38000 [ 0 0 4750 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Forwarded_Control: 13052 104416 [ 13052 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Invalidate_Control: 89 712 [ 89 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 13047 104376 [ 13047 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseLocal_Data: 13039 938808 [ 0 0 13039 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 89 712 [ 0 0 89 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Unblock_Control: 13046 104368 [ 0 0 13046 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.130515
+ links_utilized_percent_switch_2_link_0: 0.0496984 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.211332 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_ResponseLocal_Data: 12804 921888 [ 0 0 12804 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Control: 4672 37376 [ 0 0 4672 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Forwarded_Control: 12845 102760 [ 12845 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Invalidate_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 12818 102544 [ 12818 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_ResponseLocal_Data: 12833 923976 [ 0 0 12833 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Control: 78 624 [ 0 0 78 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Unblock_Control: 12816 102528 [ 0 0 12816 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 0.130077
+ links_utilized_percent_switch_3_link_0: 0.0496456 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.210509 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_ResponseLocal_Data: 12789 920808 [ 0 0 12789 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 4707 37656 [ 0 0 4707 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Forwarded_Control: 12786 102288 [ 12786 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Invalidate_Control: 96 768 [ 96 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 12804 102432 [ 12804 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_ResponseLocal_Data: 12773 919656 [ 0 0 12773 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Control: 96 768 [ 0 0 96 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Unblock_Control: 12802 102416 [ 0 0 12802 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 0.130969
+ links_utilized_percent_switch_4_link_0: 0.0499771 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_4_link_1: 0.21196 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_4_link_0_ResponseLocal_Data: 12875 927000 [ 0 0 12875 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Response_Control: 4744 37952 [ 0 0 4744 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Forwarded_Control: 12872 102976 [ 12872 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Invalidate_Control: 85 680 [ 85 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Request_Control: 12885 103080 [ 12885 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_ResponseLocal_Data: 12864 926208 [ 0 0 12864 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Response_Control: 85 680 [ 0 0 85 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Unblock_Control: 12883 103064 [ 0 0 12883 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_5_inlinks: 2
+switch_5_outlinks: 2
+links_utilized_percent_switch_5: 0.129933
+ links_utilized_percent_switch_5_link_0: 0.0494742 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_5_link_1: 0.210392 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_5_link_0_ResponseLocal_Data: 12748 917856 [ 0 0 12748 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Control: 4628 37024 [ 0 0 4628 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Forwarded_Control: 12786 102288 [ 12786 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Invalidate_Control: 86 688 [ 86 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Request_Control: 12761 102088 [ 12761 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_ResponseLocal_Data: 12775 919800 [ 0 0 12775 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Control: 86 688 [ 0 0 86 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Unblock_Control: 12759 102072 [ 0 0 12759 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_6_inlinks: 2
+switch_6_outlinks: 2
+links_utilized_percent_switch_6: 0.129171
+ links_utilized_percent_switch_6_link_0: 0.0492928 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_6_link_1: 0.20905 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_6_link_0_ResponseLocal_Data: 12711 915192 [ 0 0 12711 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Response_Control: 4565 36520 [ 0 0 4565 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Forwarded_Control: 12692 101536 [ 12692 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Request_Control: 12719 101752 [ 12719 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_ResponseLocal_Data: 12684 913248 [ 0 0 12684 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Response_Control: 91 728 [ 0 0 91 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Unblock_Control: 12718 101744 [ 0 0 12718 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_7_inlinks: 2
+switch_7_outlinks: 2
+links_utilized_percent_switch_7: 0.130628
+ links_utilized_percent_switch_7_link_0: 0.0498364 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_7_link_1: 0.21142 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_7_link_0_ResponseLocal_Data: 12842 924624 [ 0 0 12842 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Response_Control: 4677 37416 [ 0 0 4677 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Forwarded_Control: 12841 102728 [ 12841 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Request_Control: 12857 102856 [ 12857 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_ResponseLocal_Data: 12828 923616 [ 0 0 12828 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Response_Control: 104 832 [ 0 0 104 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Unblock_Control: 12855 102840 [ 0 0 12855 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_8_inlinks: 2
+switch_8_outlinks: 2
+links_utilized_percent_switch_8: 0.143125
+ links_utilized_percent_switch_8_link_0: 0.076915 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_8_link_1: 0.209335 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_8_link_0_Request_Control: 102785 822280 [ 102785 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_0_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_0_Unblock_Control: 102771 822168 [ 0 0 102771 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Response_Control: 36678 293424 [ 0 0 36678 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Forwarded_Control: 102771 822168 [ 102771 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Invalidate_Control: 404 3232 [ 404 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 2
+switch_9_outlinks: 2
+links_utilized_percent_switch_9: 1.42176e-05
+ links_utilized_percent_switch_9_link_0: 1.49659e-06 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_9_link_1: 2.69386e-05 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_9_link_0_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_0_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_10_inlinks: 10
+switch_10_outlinks: 10
+links_utilized_percent_switch_10: 0.190161
+ links_utilized_percent_switch_10_link_0: 0.199911 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_1: 0.202334 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_2: 0.198793 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_3: 0.198582 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_4: 0.199908 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_5: 0.197897 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_6: 0.197171 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_7: 0.199346 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_8: 0.30766 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_9: 5.98636e-06 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_10_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_ResponseLocal_Data: 12884 927648 [ 0 0 12884 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_Response_Control: 4640 37120 [ 0 0 4640 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_Forwarded_Control: 12897 103176 [ 12897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_Invalidate_Control: 76 608 [ 76 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_ResponseLocal_Data: 13033 938376 [ 0 0 13033 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Response_Control: 4750 38000 [ 0 0 4750 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Forwarded_Control: 13052 104416 [ 13052 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Invalidate_Control: 89 712 [ 89 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_ResponseLocal_Data: 12804 921888 [ 0 0 12804 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Response_Control: 4672 37376 [ 0 0 4672 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Forwarded_Control: 12845 102760 [ 12845 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Invalidate_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_ResponseLocal_Data: 12789 920808 [ 0 0 12789 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Response_Control: 4707 37656 [ 0 0 4707 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Forwarded_Control: 12786 102288 [ 12786 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Invalidate_Control: 96 768 [ 96 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_ResponseLocal_Data: 12875 927000 [ 0 0 12875 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Response_Control: 4744 37952 [ 0 0 4744 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Forwarded_Control: 12872 102976 [ 12872 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Invalidate_Control: 85 680 [ 85 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_ResponseLocal_Data: 12748 917856 [ 0 0 12748 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Response_Control: 4628 37024 [ 0 0 4628 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Forwarded_Control: 12786 102288 [ 12786 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Invalidate_Control: 86 688 [ 86 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_ResponseLocal_Data: 12711 915192 [ 0 0 12711 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Response_Control: 4565 36520 [ 0 0 4565 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Forwarded_Control: 12692 101536 [ 12692 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_ResponseLocal_Data: 12842 924624 [ 0 0 12842 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Response_Control: 4677 37416 [ 0 0 4677 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Forwarded_Control: 12841 102728 [ 12841 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_8_Request_Control: 102785 822280 [ 102785 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_8_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_8_Unblock_Control: 102771 822168 [ 0 0 102771 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_9_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_9_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 99075
+Ifetch 0
+Store 53011
+L1_Replacement 0
+Own_GETX 7
+Fwd_GETX 22924
+Fwd_GETS 40027
+Fwd_DMA 0
+Inv 76
+Ack 4640
+Data 91
+Exclusive_Data 12794
+Writeback_Ack 0
+Writeback_Ack_Data 0
+Writeback_Nack 0
+All_acks 4530
+Use_Timeout 12801
+
+ - Transitions -
+I Load 8363
+I Ifetch 0 <--
+I Store 4412
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 132
+S Ifetch 0 <--
+S Store 71
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 20
+
+O Load 88
+O Ifetch 0 <--
+O Store 48
+O L1_Replacement 0 <--
+O Fwd_GETX 2
+O Fwd_GETS 4
+O Fwd_DMA 0 <--
+
+M Load 119
+M Ifetch 0 <--
+M Store 70
+M L1_Replacement 0 <--
+M Fwd_GETX 29
+M Fwd_GETS 50
+M Fwd_DMA 0 <--
+
+M_W Load 14991
+M_W Ifetch 0 <--
+M_W Store 8122
+M_W L1_Replacement 0 <--
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 1371
+M_W Fwd_GETS 2561
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 149
+
+MM Load 11539
+MM Ifetch 0 <--
+MM Store 6194
+MM L1_Replacement 0 <--
+MM Fwd_GETX 4633
+MM Fwd_GETS 8089
+MM Fwd_DMA 0 <--
+
+MM_W Load 63843
+MM_W Ifetch 0 <--
+MM_W Store 34094
+MM_W L1_Replacement 0 <--
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 16848
+MM_W Fwd_GETS 29281
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 12652
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 4544
+IM Data 0 <--
+IM Exclusive_Data 4508
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 56
+SM Ack 33
+SM Data 0 <--
+SM Exclusive_Data 15
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 7
+OM Fwd_GETX 41
+OM Fwd_GETS 42
+OM Fwd_DMA 0 <--
+OM Ack 63
+OM All_acks 4530
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 91
+IS Exclusive_Data 8271
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 0 <--
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 1 ---
+ - Event Counts -
+Load 100000
+Ifetch 0
+Store 53539
+L1_Replacement 0
+Own_GETX 12
+Fwd_GETX 22634
+Fwd_GETS 40980
+Fwd_DMA 0
+Inv 89
+Ack 4750
+Data 99
+Exclusive_Data 12935
+Writeback_Ack 0
+Writeback_Ack_Data 0
+Writeback_Nack 0
+All_acks 4656
+Use_Timeout 12946
+
+ - Transitions -
+I Load 8390
+I Ifetch 0 <--
+I Store 4524
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 180
+S Ifetch 0 <--
+S Store 84
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 15
+
+O Load 94
+O Ifetch 0 <--
+O Store 49
+O L1_Replacement 0 <--
+O Fwd_GETX 1
+O Fwd_GETS 7
+O Fwd_DMA 0 <--
+
+M Load 111
+M Ifetch 0 <--
+M Store 78
+M L1_Replacement 0 <--
+M Fwd_GETX 28
+M Fwd_GETS 50
+M Fwd_DMA 0 <--
+
+M_W Load 15239
+M_W Ifetch 0 <--
+M_W Store 8135
+M_W L1_Replacement 0 <--
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 1404
+M_W Fwd_GETS 2650
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 156
+
+MM Load 11589
+MM Ifetch 0 <--
+MM Store 6188
+MM L1_Replacement 0 <--
+MM Fwd_GETX 4575
+MM Fwd_GETS 8293
+MM Fwd_DMA 0 <--
+
+MM_W Load 64397
+MM_W Ifetch 0 <--
+MM_W Store 34481
+MM_W L1_Replacement 0 <--
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 16589
+MM_W Fwd_GETS 29932
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 12790
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 4648
+IM Data 0 <--
+IM Exclusive_Data 4634
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 74
+SM Ack 22
+SM Data 0 <--
+SM Exclusive_Data 10
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 12
+OM Fwd_GETX 37
+OM Fwd_GETS 48
+OM Fwd_DMA 0 <--
+OM Ack 80
+OM All_acks 4656
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 99
+IS Exclusive_Data 8291
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 0 <--
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 2 ---
+ - Event Counts -
+Load 98065
+Ifetch 0
+Store 52760
+L1_Replacement 0
+Own_GETX 12
+Fwd_GETX 21639
+Fwd_GETS 40937
+Fwd_DMA 0
+Inv 78
+Ack 4672
+Data 88
+Exclusive_Data 12716
+Writeback_Ack 0
+Writeback_Ack_Data 0
+Writeback_Nack 0
+All_acks 4586
+Use_Timeout 12728
+
+ - Transitions -
+I Load 8231
+I Ifetch 0 <--
+I Store 4456
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 149
+S Ifetch 0 <--
+S Store 74
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 14
+
+O Load 105
+O Ifetch 0 <--
+O Store 57
+O L1_Replacement 0 <--
+O Fwd_GETX 2
+O Fwd_GETS 4
+O Fwd_DMA 0 <--
+
+M Load 126
+M Ifetch 0 <--
+M Store 75
+M L1_Replacement 0 <--
+M Fwd_GETX 27
+M Fwd_GETS 59
+M Fwd_DMA 0 <--
+
+M_W Load 14458
+M_W Ifetch 0 <--
+M_W Store 7981
+M_W L1_Replacement 0 <--
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 1353
+M_W Fwd_GETS 2411
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 161
+
+MM Load 11324
+MM Ifetch 0 <--
+MM Store 6093
+MM L1_Replacement 0 <--
+MM Fwd_GETX 4374
+MM Fwd_GETS 8268
+MM Fwd_DMA 0 <--
+
+MM_W Load 63672
+MM_W Ifetch 0 <--
+MM_W Store 34024
+MM_W L1_Replacement 0 <--
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 15838
+MM_W Fwd_GETS 30141
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 12567
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 4586
+IM Data 0 <--
+IM Exclusive_Data 4564
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 64
+SM Ack 18
+SM Data 0 <--
+SM Exclusive_Data 10
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 12
+OM Fwd_GETX 45
+OM Fwd_GETS 54
+OM Fwd_DMA 0 <--
+OM Ack 68
+OM All_acks 4586
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 88
+IS Exclusive_Data 8142
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 0 <--
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 3 ---
+ - Event Counts -
+Load 97747
+Ifetch 0
+Store 52715
+L1_Replacement 0
+Own_GETX 13
+Fwd_GETX 22282
+Fwd_GETS 40107
+Fwd_DMA 0
+Inv 96
+Ack 4707
+Data 110
+Exclusive_Data 12679
+Writeback_Ack 0
+Writeback_Ack_Data 0
+Writeback_Nack 0
+All_acks 4623
+Use_Timeout 12692
+
+ - Transitions -
+I Load 8180
+I Ifetch 0 <--
+I Store 4481
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 213
+S Ifetch 0 <--
+S Store 94
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 16
+
+O Load 75
+O Ifetch 0 <--
+O Store 49
+O L1_Replacement 0 <--
+O Fwd_GETX 4
+O Fwd_GETS 2
+O Fwd_DMA 0 <--
+
+M Load 116
+M Ifetch 0 <--
+M Store 55
+M L1_Replacement 0 <--
+M Fwd_GETX 38
+M Fwd_GETS 53
+M Fwd_DMA 0 <--
+
+M_W Load 14537
+M_W Ifetch 0 <--
+M_W Store 7923
+M_W L1_Replacement 0 <--
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 1362
+M_W Fwd_GETS 2413
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 146
+
+MM Load 11271
+MM Ifetch 0 <--
+MM Store 6128
+MM L1_Replacement 0 <--
+MM Fwd_GETX 4489
+MM Fwd_GETS 8112
+MM Fwd_DMA 0 <--
+
+MM_W Load 63355
+MM_W Ifetch 0 <--
+MM_W Store 33985
+MM_W L1_Replacement 0 <--
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 16353
+MM_W Fwd_GETS 29488
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 12546
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 4613
+IM Data 0 <--
+IM Exclusive_Data 4596
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 80
+SM Ack 22
+SM Data 0 <--
+SM Exclusive_Data 14
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 13
+OM Fwd_GETX 36
+OM Fwd_GETS 39
+OM Fwd_DMA 0 <--
+OM Ack 72
+OM All_acks 4623
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 110
+IS Exclusive_Data 8069
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 0 <--
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 4 ---
+ - Event Counts -
+Load 98342
+Ifetch 0
+Store 53559
+L1_Replacement 0
+Own_GETX 8
+Fwd_GETX 22914
+Fwd_GETS 39984
+Fwd_DMA 0
+Inv 85
+Ack 4744
+Data 100
+Exclusive_Data 12775
+Writeback_Ack 0
+Writeback_Ack_Data 0
+Writeback_Nack 0
+All_acks 4643
+Use_Timeout 12783
+
+ - Transitions -
+I Load 8241
+I Ifetch 0 <--
+I Store 4510
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 153
+S Ifetch 0 <--
+S Store 89
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 11
+
+O Load 64
+O Ifetch 0 <--
+O Store 45
+O L1_Replacement 0 <--
+O Fwd_GETX 0 <--
+O Fwd_GETS 2
+O Fwd_DMA 0 <--
+
+M Load 94
+M Ifetch 0 <--
+M Store 52
+M L1_Replacement 0 <--
+M Fwd_GETX 24
+M Fwd_GETS 45
+M Fwd_DMA 0 <--
+
+M_W Load 14777
+M_W Ifetch 0 <--
+M_W Store 8019
+M_W L1_Replacement 0 <--
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 1398
+M_W Fwd_GETS 2437
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 121
+
+MM Load 11595
+MM Ifetch 0 <--
+MM Store 6249
+MM L1_Replacement 0 <--
+MM Fwd_GETX 4628
+MM Fwd_GETS 8086
+MM Fwd_DMA 0 <--
+
+MM_W Load 63418
+MM_W Ifetch 0 <--
+MM_W Store 34595
+MM_W L1_Replacement 0 <--
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 16827
+MM_W Fwd_GETS 29372
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 12662
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 4651
+IM Data 0 <--
+IM Exclusive_Data 4620
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 74
+SM Ack 24
+SM Data 0 <--
+SM Exclusive_Data 15
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 8
+OM Fwd_GETX 37
+OM Fwd_GETS 42
+OM Fwd_DMA 0 <--
+OM Ack 69
+OM All_acks 4643
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 100
+IS Exclusive_Data 8140
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 0 <--
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 5 ---
+ - Event Counts -
+Load 97458
+Ifetch 0
+Store 52785
+L1_Replacement 0
+Own_GETX 11
+Fwd_GETX 21979
+Fwd_GETS 40331
+Fwd_DMA 0
+Inv 86
+Ack 4628
+Data 95
+Exclusive_Data 12653
+Writeback_Ack 0
+Writeback_Ack_Data 0
+Writeback_Nack 0
+All_acks 4548
+Use_Timeout 12664
+
+ - Transitions -
+I Load 8213
+I Ifetch 0 <--
+I Store 4409
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 136
+S Ifetch 0 <--
+S Store 82
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 13
+
+O Load 128
+O Ifetch 0 <--
+O Store 57
+O L1_Replacement 0 <--
+O Fwd_GETX 4
+O Fwd_GETS 7
+O Fwd_DMA 0 <--
+
+M Load 137
+M Ifetch 0 <--
+M Store 64
+M L1_Replacement 0 <--
+M Fwd_GETX 27
+M Fwd_GETS 61
+M Fwd_DMA 0 <--
+
+M_W Load 14759
+M_W Ifetch 0 <--
+M_W Store 7964
+M_W L1_Replacement 0 <--
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 1343
+M_W Fwd_GETS 2516
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 152
+
+MM Load 11252
+MM Ifetch 0 <--
+MM Store 6100
+MM L1_Replacement 0 <--
+MM Fwd_GETX 4435
+MM Fwd_GETS 8141
+MM Fwd_DMA 0 <--
+
+MM_W Load 62833
+MM_W Ifetch 0 <--
+MM_W Store 34109
+MM_W L1_Replacement 0 <--
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 16124
+MM_W Fwd_GETS 29552
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 12512
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 4547
+IM Data 0 <--
+IM Exclusive_Data 4528
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 73
+SM Ack 15
+SM Data 0 <--
+SM Exclusive_Data 9
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 11
+OM Fwd_GETX 46
+OM Fwd_GETS 54
+OM Fwd_DMA 0 <--
+OM Ack 66
+OM All_acks 4548
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 95
+IS Exclusive_Data 8116
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 0 <--
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 6 ---
+ - Event Counts -
+Load 97174
+Ifetch 0
+Store 52208
+L1_Replacement 0
+Own_GETX 7
+Fwd_GETX 21652
+Fwd_GETS 40353
+Fwd_DMA 0
+Inv 91
+Ack 4565
+Data 101
+Exclusive_Data 12610
+Writeback_Ack 0
+Writeback_Ack_Data 0
+Writeback_Nack 0
+All_acks 4508
+Use_Timeout 12616
+
+ - Transitions -
+I Load 8210
+I Ifetch 0 <--
+I Store 4378
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 127
+S Ifetch 0 <--
+S Store 91
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 10
+
+O Load 89
+O Ifetch 0 <--
+O Store 40
+O L1_Replacement 0 <--
+O Fwd_GETX 4
+O Fwd_GETS 3
+O Fwd_DMA 0 <--
+
+M Load 90
+M Ifetch 0 <--
+M Store 58
+M L1_Replacement 0 <--
+M Fwd_GETX 25
+M Fwd_GETS 44
+M Fwd_DMA 0 <--
+
+M_W Load 14800
+M_W Ifetch 0 <--
+M_W Store 7982
+M_W L1_Replacement 0 <--
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 1304
+M_W Fwd_GETS 2559
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 127
+
+MM Load 11246
+MM Ifetch 0 <--
+MM Store 6025
+MM L1_Replacement 0 <--
+MM Fwd_GETX 4382
+MM Fwd_GETS 8165
+MM Fwd_DMA 0 <--
+
+MM_W Load 62612
+MM_W Ifetch 0 <--
+MM_W Store 33634
+MM_W L1_Replacement 0 <--
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 15904
+MM_W Fwd_GETS 29554
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 12489
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 4505
+IM Data 0 <--
+IM Exclusive_Data 4491
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 81
+SM Ack 18
+SM Data 0 <--
+SM Exclusive_Data 10
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 7
+OM Fwd_GETX 33
+OM Fwd_GETS 28
+OM Fwd_DMA 0 <--
+OM Ack 42
+OM All_acks 4508
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 101
+IS Exclusive_Data 8109
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 0 <--
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 7 ---
+ - Event Counts -
+Load 97834
+Ifetch 0
+Store 53099
+L1_Replacement 0
+Own_GETX 13
+Fwd_GETX 22333
+Fwd_GETS 40296
+Fwd_DMA 0
+Inv 104
+Ack 4677
+Data 118
+Exclusive_Data 12724
+Writeback_Ack 0
+Writeback_Ack_Data 0
+Writeback_Nack 0
+All_acks 4584
+Use_Timeout 12737
+
+ - Transitions -
+I Load 8273
+I Ifetch 0 <--
+I Store 4435
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 179
+S Ifetch 0 <--
+S Store 97
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 21
+
+O Load 86
+O Ifetch 0 <--
+O Store 52
+O L1_Replacement 0 <--
+O Fwd_GETX 2
+O Fwd_GETS 4
+O Fwd_DMA 0 <--
+
+M Load 124
+M Ifetch 0 <--
+M Store 57
+M L1_Replacement 0 <--
+M Fwd_GETX 36
+M Fwd_GETS 54
+M Fwd_DMA 0 <--
+
+M_W Load 14687
+M_W Ifetch 0 <--
+M_W Store 8006
+M_W L1_Replacement 0 <--
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 1372
+M_W Fwd_GETS 2424
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 147
+
+MM Load 11353
+MM Ifetch 0 <--
+MM Store 6107
+MM L1_Replacement 0 <--
+MM Fwd_GETX 4510
+MM Fwd_GETS 8137
+MM Fwd_DMA 0 <--
+
+MM_W Load 63132
+MM_W Ifetch 0 <--
+MM_W Store 34345
+MM_W L1_Replacement 0 <--
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 16374
+MM_W Fwd_GETS 29631
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 12590
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Inv 0 <--
+IM Ack 4572
+IM Data 0 <--
+IM Exclusive_Data 4557
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 83
+SM Ack 29
+SM Data 0 <--
+SM Exclusive_Data 14
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Own_GETX 13
+OM Fwd_GETX 39
+OM Fwd_GETS 46
+OM Fwd_DMA 0 <--
+OM Ack 76
+OM All_acks 4584
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Inv 0 <--
+IS Data 118
+IS Exclusive_Data 8153
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 0 <--
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GETS 2691181
+L1_GETX 1503417
+L1_PUTO 0
+L1_PUTX 0
+L1_PUTS_only 0
+L1_PUTS 0
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_DMA 0
+Own_GETX 0
+Inv 0
+IntAck 0
+ExtAck 0
+All_Acks 2
+Data 2
+Data_Exclusive 0
+L1_WBCLEANDATA 0
+L1_WBDIRTYDATA 0
+Writeback_Ack 0
+Writeback_Nack 0
+Unblock 802
+Exclusive_Unblock 101969
+L2_Replacement 0
+
+ - Transitions -
+NP L1_GETS 0 <--
+NP L1_GETX 2
+NP L1_PUTO 0 <--
+NP L1_PUTX 0 <--
+NP L1_PUTS 0 <--
+NP Inv 0 <--
+
+I L1_GETS 0 <--
+I L1_GETX 0 <--
+I L1_PUTO 0 <--
+I L1_PUTX 0 <--
+I L1_PUTS 0 <--
+I Inv 0 <--
+I L2_Replacement 0 <--
+
+ILS L1_GETS 0 <--
+ILS L1_GETX 0 <--
+ILS L1_PUTO 0 <--
+ILS L1_PUTX 0 <--
+ILS L1_PUTS_only 0 <--
+ILS L1_PUTS 0 <--
+ILS Inv 0 <--
+ILS L2_Replacement 0 <--
+
+ILX L1_GETS 65707
+ILX L1_GETX 36262
+ILX L1_PUTO 0 <--
+ILX L1_PUTX 0 <--
+ILX L1_PUTS_only 0 <--
+ILX L1_PUTS 0 <--
+ILX Fwd_GETX 0 <--
+ILX Fwd_GETS 0 <--
+ILX Fwd_DMA 0 <--
+ILX Inv 0 <--
+ILX Data 0 <--
+ILX L2_Replacement 0 <--
+
+ILO L1_GETS 0 <--
+ILO L1_GETX 0 <--
+ILO L1_PUTO 0 <--
+ILO L1_PUTX 0 <--
+ILO L1_PUTS 0 <--
+ILO Fwd_GETX 0 <--
+ILO Fwd_GETS 0 <--
+ILO Fwd_DMA 0 <--
+ILO Inv 0 <--
+ILO Data 0 <--
+ILO L2_Replacement 0 <--
+
+ILOX L1_GETS 0 <--
+ILOX L1_GETX 0 <--
+ILOX L1_PUTO 0 <--
+ILOX L1_PUTX 0 <--
+ILOX L1_PUTS 0 <--
+ILOX Fwd_GETX 0 <--
+ILOX Fwd_GETS 0 <--
+ILOX Fwd_DMA 0 <--
+ILOX Data 0 <--
+
+ILOS L1_GETS 0 <--
+ILOS L1_GETX 0 <--
+ILOS L1_PUTO 0 <--
+ILOS L1_PUTX 0 <--
+ILOS L1_PUTS_only 0 <--
+ILOS L1_PUTS 0 <--
+ILOS Fwd_GETX 0 <--
+ILOS Fwd_GETS 0 <--
+ILOS Fwd_DMA 0 <--
+ILOS Data 0 <--
+ILOS L2_Replacement 0 <--
+
+ILOSX L1_GETS 386
+ILOSX L1_GETX 416
+ILOSX L1_PUTO 0 <--
+ILOSX L1_PUTX 0 <--
+ILOSX L1_PUTS_only 0 <--
+ILOSX L1_PUTS 0 <--
+ILOSX Fwd_GETX 0 <--
+ILOSX Fwd_GETS 0 <--
+ILOSX Fwd_DMA 0 <--
+ILOSX Data 0 <--
+
+S L1_GETS 0 <--
+S L1_GETX 0 <--
+S L1_PUTX 0 <--
+S L1_PUTS 0 <--
+S Inv 0 <--
+S L2_Replacement 0 <--
+
+O L1_GETS 0 <--
+O L1_GETX 0 <--
+O L1_PUTX 0 <--
+O Fwd_GETX 0 <--
+O Fwd_GETS 0 <--
+O Fwd_DMA 0 <--
+O L2_Replacement 0 <--
+
+OLS L1_GETS 0 <--
+OLS L1_GETX 0 <--
+OLS L1_PUTX 0 <--
+OLS L1_PUTS_only 0 <--
+OLS L1_PUTS 0 <--
+OLS Fwd_GETX 0 <--
+OLS Fwd_GETS 0 <--
+OLS Fwd_DMA 0 <--
+OLS L2_Replacement 0 <--
+
+OLSX L1_GETS 0 <--
+OLSX L1_GETX 0 <--
+OLSX L1_PUTO 0 <--
+OLSX L1_PUTX 0 <--
+OLSX L1_PUTS_only 0 <--
+OLSX L1_PUTS 0 <--
+OLSX Fwd_GETX 0 <--
+OLSX Fwd_GETS 0 <--
+OLSX Fwd_DMA 0 <--
+OLSX L2_Replacement 0 <--
+
+SLS L1_GETS 0 <--
+SLS L1_GETX 0 <--
+SLS L1_PUTX 0 <--
+SLS L1_PUTS_only 0 <--
+SLS L1_PUTS 0 <--
+SLS Inv 0 <--
+SLS L2_Replacement 0 <--
+
+M L1_GETS 0 <--
+M L1_GETX 0 <--
+M L1_PUTO 0 <--
+M L1_PUTX 0 <--
+M L1_PUTS 0 <--
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_DMA 0 <--
+M L2_Replacement 0 <--
+
+IFGX L1_GETS 0 <--
+IFGX L1_GETX 0 <--
+IFGX L1_PUTO 0 <--
+IFGX L1_PUTX 0 <--
+IFGX L1_PUTS_only 0 <--
+IFGX L1_PUTS 0 <--
+IFGX Fwd_GETX 0 <--
+IFGX Fwd_GETS 0 <--
+IFGX Fwd_DMA 0 <--
+IFGX Inv 0 <--
+IFGX Data 0 <--
+IFGX Data_Exclusive 0 <--
+IFGX L2_Replacement 0 <--
+
+IFGS L1_GETS 0 <--
+IFGS L1_GETX 0 <--
+IFGS L1_PUTO 0 <--
+IFGS L1_PUTX 0 <--
+IFGS L1_PUTS_only 0 <--
+IFGS L1_PUTS 0 <--
+IFGS Fwd_GETX 0 <--
+IFGS Fwd_GETS 0 <--
+IFGS Fwd_DMA 0 <--
+IFGS Inv 0 <--
+IFGS Data 0 <--
+IFGS Data_Exclusive 0 <--
+IFGS L2_Replacement 0 <--
+
+ISFGS L1_GETS 0 <--
+ISFGS L1_GETX 0 <--
+ISFGS L1_PUTO 0 <--
+ISFGS L1_PUTX 0 <--
+ISFGS L1_PUTS_only 0 <--
+ISFGS L1_PUTS 0 <--
+ISFGS Fwd_GETX 0 <--
+ISFGS Fwd_GETS 0 <--
+ISFGS Fwd_DMA 0 <--
+ISFGS Inv 0 <--
+ISFGS Data 0 <--
+ISFGS L2_Replacement 0 <--
+
+IFGXX L1_GETS 0 <--
+IFGXX L1_GETX 0 <--
+IFGXX L1_PUTO 0 <--
+IFGXX L1_PUTX 0 <--
+IFGXX L1_PUTS_only 0 <--
+IFGXX L1_PUTS 0 <--
+IFGXX Fwd_GETX 0 <--
+IFGXX Fwd_GETS 0 <--
+IFGXX Fwd_DMA 0 <--
+IFGXX Inv 0 <--
+IFGXX IntAck 0 <--
+IFGXX All_Acks 0 <--
+IFGXX Data_Exclusive 0 <--
+IFGXX L2_Replacement 0 <--
+
+OFGX L1_GETS 0 <--
+OFGX L1_GETX 0 <--
+OFGX L1_PUTO 0 <--
+OFGX L1_PUTX 0 <--
+OFGX L1_PUTS_only 0 <--
+OFGX L1_PUTS 0 <--
+OFGX Fwd_GETX 0 <--
+OFGX Fwd_GETS 0 <--
+OFGX Fwd_DMA 0 <--
+OFGX Inv 0 <--
+OFGX L2_Replacement 0 <--
+
+OLSF L1_GETS 0 <--
+OLSF L1_GETX 0 <--
+OLSF L1_PUTO 0 <--
+OLSF L1_PUTX 0 <--
+OLSF L1_PUTS_only 0 <--
+OLSF L1_PUTS 0 <--
+OLSF Fwd_GETX 0 <--
+OLSF Fwd_GETS 0 <--
+OLSF Fwd_DMA 0 <--
+OLSF Inv 0 <--
+OLSF IntAck 0 <--
+OLSF All_Acks 0 <--
+OLSF L2_Replacement 0 <--
+
+ILOW L1_GETS 0 <--
+ILOW L1_GETX 0 <--
+ILOW L1_PUTO 0 <--
+ILOW L1_PUTX 0 <--
+ILOW L1_PUTS_only 0 <--
+ILOW L1_PUTS 0 <--
+ILOW Fwd_GETX 0 <--
+ILOW Fwd_GETS 0 <--
+ILOW Fwd_DMA 0 <--
+ILOW Inv 0 <--
+ILOW L1_WBCLEANDATA 0 <--
+ILOW L1_WBDIRTYDATA 0 <--
+ILOW Unblock 0 <--
+ILOW L2_Replacement 0 <--
+
+ILOXW L1_GETS 0 <--
+ILOXW L1_GETX 0 <--
+ILOXW L1_PUTO 0 <--
+ILOXW L1_PUTX 0 <--
+ILOXW L1_PUTS_only 0 <--
+ILOXW L1_PUTS 0 <--
+ILOXW Fwd_GETX 0 <--
+ILOXW Fwd_GETS 0 <--
+ILOXW Fwd_DMA 0 <--
+ILOXW Inv 0 <--
+ILOXW L1_WBCLEANDATA 0 <--
+ILOXW L1_WBDIRTYDATA 0 <--
+ILOXW Unblock 0 <--
+ILOXW L2_Replacement 0 <--
+
+ILOSW L1_GETS 0 <--
+ILOSW L1_GETX 0 <--
+ILOSW L1_PUTO 0 <--
+ILOSW L1_PUTX 0 <--
+ILOSW L1_PUTS_only 0 <--
+ILOSW L1_PUTS 0 <--
+ILOSW Fwd_GETX 0 <--
+ILOSW Fwd_GETS 0 <--
+ILOSW Fwd_DMA 0 <--
+ILOSW Inv 0 <--
+ILOSW L1_WBCLEANDATA 0 <--
+ILOSW L1_WBDIRTYDATA 0 <--
+ILOSW Unblock 0 <--
+ILOSW L2_Replacement 0 <--
+
+ILOSXW L1_GETS 0 <--
+ILOSXW L1_GETX 0 <--
+ILOSXW L1_PUTO 0 <--
+ILOSXW L1_PUTX 0 <--
+ILOSXW L1_PUTS_only 0 <--
+ILOSXW L1_PUTS 0 <--
+ILOSXW Fwd_GETX 0 <--
+ILOSXW Fwd_GETS 0 <--
+ILOSXW Fwd_DMA 0 <--
+ILOSXW Inv 0 <--
+ILOSXW L1_WBCLEANDATA 0 <--
+ILOSXW L1_WBDIRTYDATA 0 <--
+ILOSXW Unblock 0 <--
+ILOSXW L2_Replacement 0 <--
+
+SLSW L1_GETS 0 <--
+SLSW L1_GETX 0 <--
+SLSW L1_PUTO 0 <--
+SLSW L1_PUTX 0 <--
+SLSW L1_PUTS_only 0 <--
+SLSW L1_PUTS 0 <--
+SLSW Fwd_GETX 0 <--
+SLSW Fwd_GETS 0 <--
+SLSW Fwd_DMA 0 <--
+SLSW Inv 0 <--
+SLSW Unblock 0 <--
+SLSW L2_Replacement 0 <--
+
+OLSW L1_GETS 0 <--
+OLSW L1_GETX 0 <--
+OLSW L1_PUTO 0 <--
+OLSW L1_PUTX 0 <--
+OLSW L1_PUTS_only 0 <--
+OLSW L1_PUTS 0 <--
+OLSW Fwd_GETX 0 <--
+OLSW Fwd_GETS 0 <--
+OLSW Fwd_DMA 0 <--
+OLSW Inv 0 <--
+OLSW Unblock 0 <--
+OLSW L2_Replacement 0 <--
+
+ILSW L1_GETS 0 <--
+ILSW L1_GETX 0 <--
+ILSW L1_PUTO 0 <--
+ILSW L1_PUTX 0 <--
+ILSW L1_PUTS_only 0 <--
+ILSW L1_PUTS 0 <--
+ILSW Fwd_GETX 0 <--
+ILSW Fwd_GETS 0 <--
+ILSW Fwd_DMA 0 <--
+ILSW Inv 0 <--
+ILSW L1_WBCLEANDATA 0 <--
+ILSW Unblock 0 <--
+ILSW L2_Replacement 0 <--
+
+IW L1_GETS 0 <--
+IW L1_GETX 0 <--
+IW L1_PUTO 0 <--
+IW L1_PUTX 0 <--
+IW L1_PUTS_only 0 <--
+IW L1_PUTS 0 <--
+IW Fwd_GETX 0 <--
+IW Fwd_GETS 0 <--
+IW Fwd_DMA 0 <--
+IW Inv 0 <--
+IW L1_WBCLEANDATA 0 <--
+IW L2_Replacement 0 <--
+
+OW L1_GETS 0 <--
+OW L1_GETX 0 <--
+OW L1_PUTO 0 <--
+OW L1_PUTX 0 <--
+OW L1_PUTS_only 0 <--
+OW L1_PUTS 0 <--
+OW Fwd_GETX 0 <--
+OW Fwd_GETS 0 <--
+OW Fwd_DMA 0 <--
+OW Inv 0 <--
+OW Unblock 0 <--
+OW L2_Replacement 0 <--
+
+SW L1_GETS 0 <--
+SW L1_GETX 0 <--
+SW L1_PUTO 0 <--
+SW L1_PUTX 0 <--
+SW L1_PUTS_only 0 <--
+SW L1_PUTS 0 <--
+SW Fwd_GETX 0 <--
+SW Fwd_GETS 0 <--
+SW Fwd_DMA 0 <--
+SW Inv 0 <--
+SW Unblock 0 <--
+SW L2_Replacement 0 <--
+
+OXW L1_GETS 0 <--
+OXW L1_GETX 0 <--
+OXW L1_PUTO 0 <--
+OXW L1_PUTX 0 <--
+OXW L1_PUTS_only 0 <--
+OXW L1_PUTS 0 <--
+OXW Fwd_GETX 0 <--
+OXW Fwd_GETS 0 <--
+OXW Fwd_DMA 0 <--
+OXW Inv 0 <--
+OXW Unblock 0 <--
+OXW L2_Replacement 0 <--
+
+OLSXW L1_GETS 0 <--
+OLSXW L1_GETX 0 <--
+OLSXW L1_PUTO 0 <--
+OLSXW L1_PUTX 0 <--
+OLSXW L1_PUTS_only 0 <--
+OLSXW L1_PUTS 0 <--
+OLSXW Fwd_GETX 0 <--
+OLSXW Fwd_GETS 0 <--
+OLSXW Fwd_DMA 0 <--
+OLSXW Inv 0 <--
+OLSXW Unblock 0 <--
+OLSXW L2_Replacement 0 <--
+
+ILXW L1_GETS 0 <--
+ILXW L1_GETX 0 <--
+ILXW L1_PUTO 0 <--
+ILXW L1_PUTX 0 <--
+ILXW L1_PUTS_only 0 <--
+ILXW L1_PUTS 0 <--
+ILXW Fwd_GETX 0 <--
+ILXW Fwd_GETS 0 <--
+ILXW Fwd_DMA 0 <--
+ILXW Inv 0 <--
+ILXW Data 0 <--
+ILXW L1_WBCLEANDATA 0 <--
+ILXW L1_WBDIRTYDATA 0 <--
+ILXW Unblock 0 <--
+ILXW L2_Replacement 0 <--
+
+IFLS L1_GETS 0 <--
+IFLS L1_GETX 0 <--
+IFLS L1_PUTO 0 <--
+IFLS L1_PUTX 0 <--
+IFLS L1_PUTS_only 0 <--
+IFLS L1_PUTS 0 <--
+IFLS Fwd_GETX 0 <--
+IFLS Fwd_GETS 0 <--
+IFLS Fwd_DMA 0 <--
+IFLS Inv 0 <--
+IFLS Unblock 0 <--
+IFLS L2_Replacement 0 <--
+
+IFLO L1_GETS 0 <--
+IFLO L1_GETX 0 <--
+IFLO L1_PUTO 0 <--
+IFLO L1_PUTX 0 <--
+IFLO L1_PUTS_only 0 <--
+IFLO L1_PUTS 0 <--
+IFLO Fwd_GETX 0 <--
+IFLO Fwd_GETS 0 <--
+IFLO Fwd_DMA 0 <--
+IFLO Inv 0 <--
+IFLO Unblock 0 <--
+IFLO L2_Replacement 0 <--
+
+IFLOX L1_GETS 0 <--
+IFLOX L1_GETX 0 <--
+IFLOX L1_PUTO 0 <--
+IFLOX L1_PUTX 0 <--
+IFLOX L1_PUTS_only 0 <--
+IFLOX L1_PUTS 0 <--
+IFLOX Fwd_GETX 0 <--
+IFLOX Fwd_GETS 0 <--
+IFLOX Fwd_DMA 0 <--
+IFLOX Inv 0 <--
+IFLOX Unblock 0 <--
+IFLOX Exclusive_Unblock 0 <--
+IFLOX L2_Replacement 0 <--
+
+IFLOXX L1_GETS 2618863
+IFLOXX L1_GETX 1458605
+IFLOXX L1_PUTO 0 <--
+IFLOXX L1_PUTX 0 <--
+IFLOXX L1_PUTS_only 0 <--
+IFLOXX L1_PUTS 0 <--
+IFLOXX Fwd_GETX 0 <--
+IFLOXX Fwd_GETS 0 <--
+IFLOXX Fwd_DMA 0 <--
+IFLOXX Inv 0 <--
+IFLOXX Unblock 416
+IFLOXX Exclusive_Unblock 101551
+IFLOXX L2_Replacement 0 <--
+
+IFLOSX L1_GETS 2718
+IFLOSX L1_GETX 3761
+IFLOSX L1_PUTO 0 <--
+IFLOSX L1_PUTX 0 <--
+IFLOSX L1_PUTS_only 0 <--
+IFLOSX L1_PUTS 0 <--
+IFLOSX Fwd_GETX 0 <--
+IFLOSX Fwd_GETS 0 <--
+IFLOSX Fwd_DMA 0 <--
+IFLOSX Inv 0 <--
+IFLOSX Unblock 386
+IFLOSX Exclusive_Unblock 0 <--
+IFLOSX L2_Replacement 0 <--
+
+IFLXO L1_GETS 3247
+IFLXO L1_GETX 4176
+IFLXO L1_PUTO 0 <--
+IFLXO L1_PUTX 0 <--
+IFLXO L1_PUTS_only 0 <--
+IFLXO L1_PUTS 0 <--
+IFLXO Fwd_GETX 0 <--
+IFLXO Fwd_GETS 0 <--
+IFLXO Fwd_DMA 0 <--
+IFLXO Inv 0 <--
+IFLXO Exclusive_Unblock 416
+IFLXO L2_Replacement 0 <--
+
+IGS L1_GETS 0 <--
+IGS L1_GETX 0 <--
+IGS L1_PUTO 0 <--
+IGS L1_PUTX 0 <--
+IGS L1_PUTS_only 0 <--
+IGS L1_PUTS 0 <--
+IGS Fwd_GETX 0 <--
+IGS Fwd_GETS 0 <--
+IGS Fwd_DMA 0 <--
+IGS Own_GETX 0 <--
+IGS Inv 0 <--
+IGS Data 0 <--
+IGS Data_Exclusive 0 <--
+IGS Unblock 0 <--
+IGS Exclusive_Unblock 0 <--
+IGS L2_Replacement 0 <--
+
+IGM L1_GETS 244
+IGM L1_GETX 183
+IGM L1_PUTO 0 <--
+IGM L1_PUTX 0 <--
+IGM L1_PUTS_only 0 <--
+IGM L1_PUTS 0 <--
+IGM Fwd_GETX 0 <--
+IGM Fwd_GETS 0 <--
+IGM Fwd_DMA 0 <--
+IGM Own_GETX 0 <--
+IGM Inv 0 <--
+IGM ExtAck 0 <--
+IGM Data 2
+IGM Data_Exclusive 0 <--
+IGM L2_Replacement 0 <--
+
+IGMLS L1_GETS 0 <--
+IGMLS L1_GETX 0 <--
+IGMLS L1_PUTO 0 <--
+IGMLS L1_PUTX 0 <--
+IGMLS L1_PUTS_only 0 <--
+IGMLS L1_PUTS 0 <--
+IGMLS Inv 0 <--
+IGMLS IntAck 0 <--
+IGMLS ExtAck 0 <--
+IGMLS All_Acks 0 <--
+IGMLS Data 0 <--
+IGMLS Data_Exclusive 0 <--
+IGMLS L2_Replacement 0 <--
+
+IGMO L1_GETS 16
+IGMO L1_GETX 12
+IGMO L1_PUTO 0 <--
+IGMO L1_PUTX 0 <--
+IGMO L1_PUTS_only 0 <--
+IGMO L1_PUTS 0 <--
+IGMO Fwd_GETX 0 <--
+IGMO Fwd_GETS 0 <--
+IGMO Fwd_DMA 0 <--
+IGMO Own_GETX 0 <--
+IGMO ExtAck 0 <--
+IGMO All_Acks 2
+IGMO Exclusive_Unblock 2
+IGMO L2_Replacement 0 <--
+
+IGMIO L1_GETS 0 <--
+IGMIO L1_GETX 0 <--
+IGMIO L1_PUTO 0 <--
+IGMIO L1_PUTX 0 <--
+IGMIO L1_PUTS_only 0 <--
+IGMIO L1_PUTS 0 <--
+IGMIO Fwd_GETX 0 <--
+IGMIO Fwd_GETS 0 <--
+IGMIO Fwd_DMA 0 <--
+IGMIO Own_GETX 0 <--
+IGMIO ExtAck 0 <--
+IGMIO All_Acks 0 <--
+
+OGMIO L1_GETS 0 <--
+OGMIO L1_GETX 0 <--
+OGMIO L1_PUTO 0 <--
+OGMIO L1_PUTX 0 <--
+OGMIO L1_PUTS_only 0 <--
+OGMIO L1_PUTS 0 <--
+OGMIO Fwd_GETX 0 <--
+OGMIO Fwd_GETS 0 <--
+OGMIO Fwd_DMA 0 <--
+OGMIO Own_GETX 0 <--
+OGMIO ExtAck 0 <--
+OGMIO All_Acks 0 <--
+
+IGMIOF L1_GETS 0 <--
+IGMIOF L1_GETX 0 <--
+IGMIOF L1_PUTO 0 <--
+IGMIOF L1_PUTX 0 <--
+IGMIOF L1_PUTS_only 0 <--
+IGMIOF L1_PUTS 0 <--
+IGMIOF IntAck 0 <--
+IGMIOF All_Acks 0 <--
+IGMIOF Data_Exclusive 0 <--
+
+IGMIOFS L1_GETS 0 <--
+IGMIOFS L1_GETX 0 <--
+IGMIOFS L1_PUTO 0 <--
+IGMIOFS L1_PUTX 0 <--
+IGMIOFS L1_PUTS_only 0 <--
+IGMIOFS L1_PUTS 0 <--
+IGMIOFS Fwd_GETX 0 <--
+IGMIOFS Fwd_GETS 0 <--
+IGMIOFS Fwd_DMA 0 <--
+IGMIOFS Inv 0 <--
+IGMIOFS Data 0 <--
+IGMIOFS L2_Replacement 0 <--
+
+OGMIOF L1_GETS 0 <--
+OGMIOF L1_GETX 0 <--
+OGMIOF L1_PUTO 0 <--
+OGMIOF L1_PUTX 0 <--
+OGMIOF L1_PUTS_only 0 <--
+OGMIOF L1_PUTS 0 <--
+OGMIOF IntAck 0 <--
+OGMIOF All_Acks 0 <--
+
+II L1_GETS 0 <--
+II L1_GETX 0 <--
+II L1_PUTO 0 <--
+II L1_PUTX 0 <--
+II L1_PUTS_only 0 <--
+II L1_PUTS 0 <--
+II IntAck 0 <--
+II All_Acks 0 <--
+
+MM L1_GETS 0 <--
+MM L1_GETX 0 <--
+MM L1_PUTO 0 <--
+MM L1_PUTX 0 <--
+MM L1_PUTS_only 0 <--
+MM L1_PUTS 0 <--
+MM Fwd_GETX 0 <--
+MM Fwd_GETS 0 <--
+MM Fwd_DMA 0 <--
+MM Inv 0 <--
+MM Exclusive_Unblock 0 <--
+MM L2_Replacement 0 <--
+
+SS L1_GETS 0 <--
+SS L1_GETX 0 <--
+SS L1_PUTO 0 <--
+SS L1_PUTX 0 <--
+SS L1_PUTS_only 0 <--
+SS L1_PUTS 0 <--
+SS Fwd_GETX 0 <--
+SS Fwd_GETS 0 <--
+SS Fwd_DMA 0 <--
+SS Inv 0 <--
+SS Unblock 0 <--
+SS L2_Replacement 0 <--
+
+OO L1_GETS 0 <--
+OO L1_GETX 0 <--
+OO L1_PUTO 0 <--
+OO L1_PUTX 0 <--
+OO L1_PUTS_only 0 <--
+OO L1_PUTS 0 <--
+OO Fwd_GETX 0 <--
+OO Fwd_GETS 0 <--
+OO Fwd_DMA 0 <--
+OO Inv 0 <--
+OO Unblock 0 <--
+OO Exclusive_Unblock 0 <--
+OO L2_Replacement 0 <--
+
+OLSS L1_GETS 0 <--
+OLSS L1_GETX 0 <--
+OLSS L1_PUTO 0 <--
+OLSS L1_PUTX 0 <--
+OLSS L1_PUTS_only 0 <--
+OLSS L1_PUTS 0 <--
+OLSS Fwd_GETX 0 <--
+OLSS Fwd_GETS 0 <--
+OLSS Fwd_DMA 0 <--
+OLSS Inv 0 <--
+OLSS Unblock 0 <--
+OLSS L2_Replacement 0 <--
+
+OLSXS L1_GETS 0 <--
+OLSXS L1_GETX 0 <--
+OLSXS L1_PUTO 0 <--
+OLSXS L1_PUTX 0 <--
+OLSXS L1_PUTS_only 0 <--
+OLSXS L1_PUTS 0 <--
+OLSXS Fwd_GETX 0 <--
+OLSXS Fwd_GETS 0 <--
+OLSXS Fwd_DMA 0 <--
+OLSXS Inv 0 <--
+OLSXS Unblock 0 <--
+OLSXS L2_Replacement 0 <--
+
+SLSS L1_GETS 0 <--
+SLSS L1_GETX 0 <--
+SLSS L1_PUTO 0 <--
+SLSS L1_PUTX 0 <--
+SLSS L1_PUTS_only 0 <--
+SLSS L1_PUTS 0 <--
+SLSS Fwd_GETX 0 <--
+SLSS Fwd_GETS 0 <--
+SLSS Fwd_DMA 0 <--
+SLSS Inv 0 <--
+SLSS Unblock 0 <--
+SLSS L2_Replacement 0 <--
+
+OI L1_GETS 0 <--
+OI L1_GETX 0 <--
+OI L1_PUTO 0 <--
+OI L1_PUTX 0 <--
+OI L1_PUTS_only 0 <--
+OI L1_PUTS 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Nack 0 <--
+OI L2_Replacement 0 <--
+
+MI L1_GETS 0 <--
+MI L1_GETX 0 <--
+MI L1_PUTO 0 <--
+MI L1_PUTX 0 <--
+MI L1_PUTS_only 0 <--
+MI L1_PUTS 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI L2_Replacement 0 <--
+
+MII L1_GETS 0 <--
+MII L1_GETX 0 <--
+MII L1_PUTO 0 <--
+MII L1_PUTX 0 <--
+MII L1_PUTS_only 0 <--
+MII L1_PUTS 0 <--
+MII Writeback_Ack 0 <--
+MII Writeback_Nack 0 <--
+MII L2_Replacement 0 <--
+
+OLSI L1_GETS 0 <--
+OLSI L1_GETX 0 <--
+OLSI L1_PUTO 0 <--
+OLSI L1_PUTX 0 <--
+OLSI L1_PUTS_only 0 <--
+OLSI L1_PUTS 0 <--
+OLSI Fwd_GETX 0 <--
+OLSI Fwd_GETS 0 <--
+OLSI Fwd_DMA 0 <--
+OLSI Writeback_Ack 0 <--
+OLSI L2_Replacement 0 <--
+
+ILSI L1_GETS 0 <--
+ILSI L1_GETX 0 <--
+ILSI L1_PUTO 0 <--
+ILSI L1_PUTX 0 <--
+ILSI L1_PUTS_only 0 <--
+ILSI L1_PUTS 0 <--
+ILSI IntAck 0 <--
+ILSI All_Acks 0 <--
+ILSI Writeback_Ack 0 <--
+ILSI L2_Replacement 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer:
+ memory_total_requests: 2
+ memory_reads: 2
+ memory_writes: 0
+ memory_refreshes: 22
+ memory_total_request_delays: 31
+ memory_delays_per_request: 15.5
+ memory_delays_in_input_queue: 1
+ memory_delays_behind_head_of_bank_queue: 10
+ memory_delays_stalled_at_head_of_bank_queue: 20
+ memory_stalls_for_bank_busy: 20
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 0
+ memory_stalls_for_bus: 0
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 0
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 2
+GETS 0
+PUTX 0
+PUTO 0
+PUTO_SHARERS 0
+Unblock 0
+Last_Unblock 0
+Exclusive_Unblock 2
+Clean_Writeback 0
+Dirty_Writeback 0
+Memory_Data 2
+Memory_Ack 0
+DMA_READ 0
+DMA_WRITE 0
+Data 0
+
+ - Transitions -
+I GETX 2
+I GETS 0 <--
+I PUTX 0 <--
+I PUTO 0 <--
+I Memory_Data 0 <--
+I Memory_Ack 0 <--
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+S GETX 0 <--
+S GETS 0 <--
+S PUTX 0 <--
+S PUTO 0 <--
+S Memory_Data 0 <--
+S Memory_Ack 0 <--
+S DMA_READ 0 <--
+S DMA_WRITE 0 <--
+
+O GETX 0 <--
+O GETS 0 <--
+O PUTX 0 <--
+O PUTO 0 <--
+O PUTO_SHARERS 0 <--
+O Memory_Data 0 <--
+O Memory_Ack 0 <--
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+
+M GETX 0 <--
+M GETS 0 <--
+M PUTX 0 <--
+M PUTO 0 <--
+M PUTO_SHARERS 0 <--
+M Memory_Data 0 <--
+M Memory_Ack 0 <--
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+
+IS GETX 0 <--
+IS GETS 0 <--
+IS PUTX 0 <--
+IS PUTO 0 <--
+IS PUTO_SHARERS 0 <--
+IS Unblock 0 <--
+IS Exclusive_Unblock 0 <--
+IS Memory_Data 0 <--
+IS Memory_Ack 0 <--
+IS DMA_READ 0 <--
+IS DMA_WRITE 0 <--
+
+SS GETX 0 <--
+SS GETS 0 <--
+SS PUTX 0 <--
+SS PUTO 0 <--
+SS PUTO_SHARERS 0 <--
+SS Unblock 0 <--
+SS Last_Unblock 0 <--
+SS Memory_Data 0 <--
+SS Memory_Ack 0 <--
+SS DMA_READ 0 <--
+SS DMA_WRITE 0 <--
+
+OO GETX 0 <--
+OO GETS 0 <--
+OO PUTX 0 <--
+OO PUTO 0 <--
+OO PUTO_SHARERS 0 <--
+OO Unblock 0 <--
+OO Last_Unblock 0 <--
+OO Memory_Data 0 <--
+OO Memory_Ack 0 <--
+OO DMA_READ 0 <--
+OO DMA_WRITE 0 <--
+
+MO GETX 0 <--
+MO GETS 0 <--
+MO PUTX 0 <--
+MO PUTO 0 <--
+MO PUTO_SHARERS 0 <--
+MO Unblock 0 <--
+MO Exclusive_Unblock 0 <--
+MO Memory_Data 0 <--
+MO Memory_Ack 0 <--
+MO DMA_READ 0 <--
+MO DMA_WRITE 0 <--
+
+MM GETX 0 <--
+MM GETS 0 <--
+MM PUTX 0 <--
+MM PUTO 0 <--
+MM PUTO_SHARERS 0 <--
+MM Exclusive_Unblock 2
+MM Memory_Data 2
+MM Memory_Ack 0 <--
+MM DMA_READ 0 <--
+MM DMA_WRITE 0 <--
+
+
+MI GETX 0 <--
+MI GETS 0 <--
+MI PUTX 0 <--
+MI PUTO 0 <--
+MI PUTO_SHARERS 0 <--
+MI Unblock 0 <--
+MI Clean_Writeback 0 <--
+MI Dirty_Writeback 0 <--
+MI Memory_Data 0 <--
+MI Memory_Ack 0 <--
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+
+MIS GETX 0 <--
+MIS GETS 0 <--
+MIS PUTX 0 <--
+MIS PUTO 0 <--
+MIS PUTO_SHARERS 0 <--
+MIS Unblock 0 <--
+MIS Clean_Writeback 0 <--
+MIS Dirty_Writeback 0 <--
+MIS Memory_Data 0 <--
+MIS Memory_Ack 0 <--
+MIS DMA_READ 0 <--
+MIS DMA_WRITE 0 <--
+
+OS GETX 0 <--
+OS GETS 0 <--
+OS PUTX 0 <--
+OS PUTO 0 <--
+OS PUTO_SHARERS 0 <--
+OS Unblock 0 <--
+OS Clean_Writeback 0 <--
+OS Dirty_Writeback 0 <--
+OS Memory_Data 0 <--
+OS Memory_Ack 0 <--
+OS DMA_READ 0 <--
+OS DMA_WRITE 0 <--
+
+OSS GETX 0 <--
+OSS GETS 0 <--
+OSS PUTX 0 <--
+OSS PUTO 0 <--
+OSS PUTO_SHARERS 0 <--
+OSS Unblock 0 <--
+OSS Clean_Writeback 0 <--
+OSS Dirty_Writeback 0 <--
+OSS Memory_Data 0 <--
+OSS Memory_Ack 0 <--
+OSS DMA_READ 0 <--
+OSS DMA_WRITE 0 <--
+
+XI_M GETX 0 <--
+XI_M GETS 0 <--
+XI_M PUTX 0 <--
+XI_M PUTO 0 <--
+XI_M PUTO_SHARERS 0 <--
+XI_M Memory_Data 0 <--
+XI_M Memory_Ack 0 <--
+XI_M DMA_READ 0 <--
+XI_M DMA_WRITE 0 <--
+
+XI_U GETX 0 <--
+XI_U GETS 0 <--
+XI_U PUTX 0 <--
+XI_U PUTO 0 <--
+XI_U PUTO_SHARERS 0 <--
+XI_U Exclusive_Unblock 0 <--
+XI_U Memory_Ack 0 <--
+XI_U DMA_READ 0 <--
+XI_U DMA_WRITE 0 <--
+
+OI_D GETX 0 <--
+OI_D GETS 0 <--
+OI_D PUTX 0 <--
+OI_D PUTO 0 <--
+OI_D PUTO_SHARERS 0 <--
+OI_D DMA_READ 0 <--
+OI_D DMA_WRITE 0 <--
+OI_D Data 0 <--
+
--- /dev/null
+system.cpu0: completed 10000 read accesses @325610
+system.cpu1: completed 10000 read accesses @328426
+system.cpu2: completed 10000 read accesses @330443
+system.cpu5: completed 10000 read accesses @338385
+system.cpu7: completed 10000 read accesses @344032
+system.cpu3: completed 10000 read accesses @350837
+system.cpu4: completed 10000 read accesses @358597
+system.cpu6: completed 10000 read accesses @362921
+system.cpu0: completed 20000 read accesses @651713
+system.cpu1: completed 20000 read accesses @654395
+system.cpu5: completed 20000 read accesses @675104
+system.cpu7: completed 20000 read accesses @678502
+system.cpu2: completed 20000 read accesses @686227
+system.cpu3: completed 20000 read accesses @688125
+system.cpu4: completed 20000 read accesses @701024
+system.cpu6: completed 20000 read accesses @714978
+system.cpu1: completed 30000 read accesses @992058
+system.cpu0: completed 30000 read accesses @996204
+system.cpu2: completed 30000 read accesses @1012415
+system.cpu5: completed 30000 read accesses @1018935
+system.cpu3: completed 30000 read accesses @1028572
+system.cpu7: completed 30000 read accesses @1034750
+system.cpu4: completed 30000 read accesses @1035581
+system.cpu6: completed 30000 read accesses @1057109
+system.cpu1: completed 40000 read accesses @1328565
+system.cpu0: completed 40000 read accesses @1342349
+system.cpu5: completed 40000 read accesses @1358651
+system.cpu2: completed 40000 read accesses @1362244
+system.cpu3: completed 40000 read accesses @1365572
+system.cpu4: completed 40000 read accesses @1376682
+system.cpu7: completed 40000 read accesses @1377955
+system.cpu6: completed 40000 read accesses @1385954
+system.cpu1: completed 50000 read accesses @1651444
+system.cpu0: completed 50000 read accesses @1681780
+system.cpu2: completed 50000 read accesses @1697366
+system.cpu5: completed 50000 read accesses @1705801
+system.cpu3: completed 50000 read accesses @1712915
+system.cpu4: completed 50000 read accesses @1717462
+system.cpu7: completed 50000 read accesses @1728540
+system.cpu6: completed 50000 read accesses @1732862
+system.cpu1: completed 60000 read accesses @2001756
+system.cpu0: completed 60000 read accesses @2007806
+system.cpu4: completed 60000 read accesses @2036786
+system.cpu3: completed 60000 read accesses @2041761
+system.cpu2: completed 60000 read accesses @2049223
+system.cpu5: completed 60000 read accesses @2054495
+system.cpu6: completed 60000 read accesses @2073699
+system.cpu7: completed 60000 read accesses @2074170
+system.cpu1: completed 70000 read accesses @2344028
+system.cpu0: completed 70000 read accesses @2351090
+system.cpu4: completed 70000 read accesses @2367786
+system.cpu5: completed 70000 read accesses @2386819
+system.cpu2: completed 70000 read accesses @2390297
+system.cpu3: completed 70000 read accesses @2399080
+system.cpu6: completed 70000 read accesses @2409182
+system.cpu7: completed 70000 read accesses @2411377
+system.cpu1: completed 80000 read accesses @2685330
+system.cpu0: completed 80000 read accesses @2689745
+system.cpu4: completed 80000 read accesses @2704099
+system.cpu2: completed 80000 read accesses @2728887
+system.cpu5: completed 80000 read accesses @2735646
+system.cpu3: completed 80000 read accesses @2736625
+system.cpu7: completed 80000 read accesses @2740886
+system.cpu6: completed 80000 read accesses @2752448
+system.cpu1: completed 90000 read accesses @3013853
+system.cpu0: completed 90000 read accesses @3029349
+system.cpu4: completed 90000 read accesses @3054103
+system.cpu2: completed 90000 read accesses @3064472
+system.cpu3: completed 90000 read accesses @3075826
+system.cpu7: completed 90000 read accesses @3076830
+system.cpu5: completed 90000 read accesses @3082514
+system.cpu6: completed 90000 read accesses @3098674
+system.cpu1: completed 100000 read accesses @3340930
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 14:49:51
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 15:08:16
+M5 executing on svvint05
+command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 3340930 because maximum number of loads reached
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 345104 # Number of bytes of host memory used
+host_seconds 37.10 # Real time elapsed on the host
+host_tick_rate 90051 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.003341 # Number of seconds simulated
+sim_ticks 3340930 # Number of ticks simulated
+system.cpu0.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 99074 # number of read accesses completed
+system.cpu0.num_writes 53010 # number of write accesses completed
+system.cpu1.num_copies 0 # number of copy accesses completed
+system.cpu1.num_reads 100000 # number of read accesses completed
+system.cpu1.num_writes 53538 # number of write accesses completed
+system.cpu2.num_copies 0 # number of copy accesses completed
+system.cpu2.num_reads 98064 # number of read accesses completed
+system.cpu2.num_writes 52759 # number of write accesses completed
+system.cpu3.num_copies 0 # number of copy accesses completed
+system.cpu3.num_reads 97746 # number of read accesses completed
+system.cpu3.num_writes 52714 # number of write accesses completed
+system.cpu4.num_copies 0 # number of copy accesses completed
+system.cpu4.num_reads 98341 # number of read accesses completed
+system.cpu4.num_writes 53558 # number of write accesses completed
+system.cpu5.num_copies 0 # number of copy accesses completed
+system.cpu5.num_reads 97456 # number of read accesses completed
+system.cpu5.num_writes 52785 # number of write accesses completed
+system.cpu6.num_copies 0 # number of copy accesses completed
+system.cpu6.num_reads 97173 # number of read accesses completed
+system.cpu6.num_writes 52207 # number of write accesses completed
+system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu7.num_reads 97832 # number of read accesses completed
+system.cpu7.num_writes 53099 # number of write accesses completed
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu0]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu1]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
+
+[system.cpu2]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
+
+[system.cpu3]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
+num_int_nodes=11
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
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+latency=1
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+
+[system.ruby.network.topology.ext_links0.ext_node]
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+children=sequencer
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+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+N_tokens=9
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+fixed_timeout_latency=300
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+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
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+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
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+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L1Cache_Controller
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+L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+N_tokens=9
+buffer_size=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
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+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
+transitions_per_cycle=32
+version=1
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache]
+type=RubyCache
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+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=L1Cache_Controller
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+L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+N_tokens=9
+buffer_size=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
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+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer
+transitions_per_cycle=32
+version=2
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[2]
+port=system.cpu2.test
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links3]
+type=ExtLink
+children=ext_node
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+int_node=3
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links3.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+N_tokens=9
+buffer_size=0
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+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer
+transitions_per_cycle=32
+version=3
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+max_outstanding_requests=16
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+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache]
+type=RubyCache
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+size=256
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
+type=RubyCache
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+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links4]
+type=ExtLink
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+ext_node=system.ruby.network.topology.ext_links4.ext_node
+int_node=4
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links4.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+N_tokens=9
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+sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer
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+version=4
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer]
+type=RubySequencer
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+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache]
+type=RubyCache
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+size=256
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
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+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links5]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links5.ext_node
+int_node=5
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links5.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+N_tokens=9
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+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
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+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer
+transitions_per_cycle=32
+version=5
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links6]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links6.ext_node
+int_node=6
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links6.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+N_tokens=9
+buffer_size=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
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+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
+transitions_per_cycle=32
+version=6
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache]
+type=RubyCache
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+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
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+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links7]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links7.ext_node
+int_node=7
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links7.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+N_tokens=9
+buffer_size=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
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+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
+transitions_per_cycle=32
+version=7
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links8]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links8.ext_node
+int_node=8
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links8.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory
+N_tokens=9
+buffer_size=0
+filtering_enabled=true
+l2_request_latency=10
+l2_response_latency=10
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links9]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links9.ext_node
+int_node=9
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links9.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links9.ext_node.directory
+directory_latency=6
+distributed_persistent=true
+fixed_timeout_latency=300
+l2_select_num_bits=0
+memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links9.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links9.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=3
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=4
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=5
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=6
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=7
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=8
+node_b=10
+weight=1
+
+[system.ruby.network.topology.int_links9]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=9
+node_b=10
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: active, ordered
+virtual_net_3: active, unordered
+virtual_net_4: active, unordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 15:56:26
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 39
+Elapsed_time_in_minutes: 0.65
+Elapsed_time_in_hours: 0.0108333
+Elapsed_time_in_days: 0.000451389
+
+Virtual_time_in_seconds: 35.9
+Virtual_time_in_minutes: 0.598333
+Virtual_time_in_hours: 0.00997222
+Virtual_time_in_days: 0.000415509
+
+Ruby_current_time: 3231932
+Ruby_start_time: 0
+Ruby_cycles: 3231932
+
+mbytes_resident: 31.7773
+mbytes_total: 31.7812
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+
+ruby_cycles_executed: 25855464 [ 3231933 3231933 3231933 3231933 3231933 3231933 3231933 3231933 ]
+
+transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
+transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
+cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
+
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1209894 average: 1.99167 | standard deviation: 0.0908904 | 0 10078 1199816 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 8 max: 1007 count: 1209878 average: 40.7363 | standard deviation: 150.889 | 1138544 0 115 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69625 817 110 141 166 130 111 43 34 22 1 0 0 0 1 6 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 8 max: 1007 count: 786333 average: 40.9465 | standard deviation: 151.281 | 739784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45504 542 75 89 120 82 65 25 24 12 0 0 0 0 0 4 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 8 max: 1007 count: 423545 average: 40.346 | standard deviation: 150.157 | 398760 0 115 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24121 275 35 52 46 48 46 18 10 10 1 0 0 0 1 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 35
+system_time: 0
+page_reclaims: 6951
+page_faults: 1964
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.151595
+ links_utilized_percent_switch_0_link_0: 0.110246 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.192945 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Request_Control: 62433 499464 [ 0 0 0 0 62433 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 8904 641088 [ 0 8904 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseLocal_Data: 4 288 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 17830 142640 [ 0 0 0 0 17830 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Data: 8898 640656 [ 0 8898 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_ResponseLocal_Data: 10 720 [ 0 10 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Control: 8907 71256 [ 0 8907 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Persistent_Control: 17808 142464 [ 0 0 17808 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.151593
+ links_utilized_percent_switch_1_link_0: 0.110245 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.19294 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 62433 499464 [ 0 0 0 0 62433 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 8902 640944 [ 0 8902 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_ResponseLocal_Data: 6 432 [ 0 6 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Control: 6 48 [ 0 6 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 17830 142640 [ 0 0 0 0 17830 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 8901 640872 [ 0 8901 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseLocal_Data: 7 504 [ 0 7 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 8908 71264 [ 0 8908 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Persistent_Control: 17804 142432 [ 0 0 17804 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.151589
+ links_utilized_percent_switch_2_link_0: 0.110242 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.192936 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Request_Control: 62429 499432 [ 0 0 0 0 62429 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Data: 8903 641016 [ 0 8903 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_ResponseLocal_Data: 4 288 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Control: 12 96 [ 0 12 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 17838 142704 [ 0 0 0 0 17838 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 8900 640800 [ 0 8900 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_ResponseLocal_Data: 7 504 [ 0 7 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Control: 8904 71232 [ 0 8904 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Persistent_Control: 17806 142448 [ 0 0 17806 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 0.15158
+ links_utilized_percent_switch_3_link_0: 0.110242 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.192917 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Request_Control: 62434 499472 [ 0 0 0 0 62434 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Data: 8902 640944 [ 0 8902 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_ResponseLocal_Data: 5 360 [ 0 5 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 6 48 [ 0 6 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 17828 142624 [ 0 0 0 0 17828 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 8900 640800 [ 0 8900 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_ResponseLocal_Data: 7 504 [ 0 7 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Control: 8904 71232 [ 0 8904 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Persistent_Control: 17804 142432 [ 0 0 17804 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 0.151642
+ links_utilized_percent_switch_4_link_0: 0.110261 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_4_link_1: 0.193024 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_4_link_0_Request_Control: 62425 499400 [ 0 0 0 0 62425 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Response_Data: 8901 640872 [ 0 8901 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_ResponseLocal_Data: 12 864 [ 0 12 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Response_Control: 10 80 [ 0 10 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Request_Control: 17846 142768 [ 0 0 0 0 17846 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Response_Data: 8907 641304 [ 0 8907 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_ResponseLocal_Data: 6 432 [ 0 6 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Response_Control: 8903 71224 [ 0 8903 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Persistent_Control: 17802 142416 [ 0 0 17802 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_5_inlinks: 2
+switch_5_outlinks: 2
+links_utilized_percent_switch_5: 0.151682
+ links_utilized_percent_switch_5_link_0: 0.110273 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_5_link_1: 0.19309 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_5_link_0_Request_Control: 62420 499360 [ 0 0 0 0 62420 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Data: 8900 640800 [ 0 8900 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_ResponseLocal_Data: 17 1224 [ 0 17 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Control: 10 80 [ 0 10 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Request_Control: 17856 142848 [ 0 0 0 0 17856 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Data: 8910 641520 [ 0 8910 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_ResponseLocal_Data: 7 504 [ 0 7 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Control: 8902 71216 [ 0 8902 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Persistent_Control: 17800 142400 [ 0 0 17800 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_6_inlinks: 2
+switch_6_outlinks: 2
+links_utilized_percent_switch_6: 0.151632
+ links_utilized_percent_switch_6_link_0: 0.110261 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_6_link_1: 0.193002 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_6_link_0_Request_Control: 62430 499440 [ 0 0 0 0 62430 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Response_Data: 8903 641016 [ 0 8903 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_ResponseLocal_Data: 10 720 [ 0 10 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Response_Control: 6 48 [ 0 6 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Request_Control: 17836 142688 [ 0 0 0 0 17836 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Response_Data: 8905 641160 [ 0 8905 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_ResponseLocal_Data: 7 504 [ 0 7 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Response_Control: 8906 71248 [ 0 8906 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Persistent_Control: 17804 142432 [ 0 0 17804 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_7_inlinks: 2
+switch_7_outlinks: 2
+links_utilized_percent_switch_7: 0.151577
+ links_utilized_percent_switch_7_link_0: 0.110242 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_7_link_1: 0.192912 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_7_link_0_Request_Control: 62432 499456 [ 0 0 0 0 62432 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Response_Data: 8904 641088 [ 0 8904 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_ResponseLocal_Data: 3 216 [ 0 3 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Request_Control: 17832 142656 [ 0 0 0 0 17832 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Response_Data: 8896 640512 [ 0 8896 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_ResponseLocal_Data: 10 720 [ 0 10 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Response_Control: 8905 71240 [ 0 8905 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Persistent_Control: 17805 142440 [ 0 0 17805 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_8_inlinks: 2
+switch_8_outlinks: 2
+links_utilized_percent_switch_8: 0.110295
+ links_utilized_percent_switch_8_link_0: 0.11021 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_8_link_1: 0.11038 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_8_link_0_Request_Control: 71348 570784 [ 0 0 0 0 71348 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_0_Response_Control: 71173 569384 [ 0 71173 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Request_Control: 71348 570784 [ 0 0 0 71348 0 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 2
+switch_9_outlinks: 2
+links_utilized_percent_switch_9: 0.0413555
+ links_utilized_percent_switch_9_link_0: 0.0826831 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_9_link_1: 2.78471e-05 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_9_link_0_Request_Control: 71348 570784 [ 0 0 0 71348 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_0_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_10_inlinks: 10
+switch_10_outlinks: 10
+links_utilized_percent_switch_10: 0.407928
+ links_utilized_percent_switch_10_link_0: 0.413434 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_1: 0.413437 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_2: 0.413423 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_3: 0.413425 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_4: 0.413503 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_5: 0.413554 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_6: 0.413502 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_7: 0.413423 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_8: 0.440842 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_10_link_9: 0.330733 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_10_link_0_Request_Control: 62433 499464 [ 0 0 0 0 62433 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_Response_Data: 8904 641088 [ 0 8904 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_ResponseLocal_Data: 4 288 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_Persistent_Control: 124625 997000 [ 0 0 124625 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Request_Control: 62433 499464 [ 0 0 0 0 62433 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Response_Data: 8902 640944 [ 0 8902 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_ResponseLocal_Data: 6 432 [ 0 6 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Response_Control: 6 48 [ 0 6 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Persistent_Control: 124629 997032 [ 0 0 124629 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Request_Control: 62429 499432 [ 0 0 0 0 62429 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Response_Data: 8903 641016 [ 0 8903 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_ResponseLocal_Data: 4 288 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Response_Control: 12 96 [ 0 12 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_2_Persistent_Control: 124627 997016 [ 0 0 124627 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Request_Control: 62434 499472 [ 0 0 0 0 62434 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Response_Data: 8902 640944 [ 0 8902 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_ResponseLocal_Data: 5 360 [ 0 5 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Response_Control: 6 48 [ 0 6 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_3_Persistent_Control: 124629 997032 [ 0 0 124629 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Request_Control: 62425 499400 [ 0 0 0 0 62425 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Response_Data: 8901 640872 [ 0 8901 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_ResponseLocal_Data: 12 864 [ 0 12 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Response_Control: 10 80 [ 0 10 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_4_Persistent_Control: 124631 997048 [ 0 0 124631 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Request_Control: 62420 499360 [ 0 0 0 0 62420 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Response_Data: 8900 640800 [ 0 8900 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_ResponseLocal_Data: 17 1224 [ 0 17 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Response_Control: 10 80 [ 0 10 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_5_Persistent_Control: 124633 997064 [ 0 0 124633 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Request_Control: 62430 499440 [ 0 0 0 0 62430 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Response_Data: 8903 641016 [ 0 8903 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_ResponseLocal_Data: 10 720 [ 0 10 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Response_Control: 6 48 [ 0 6 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_6_Persistent_Control: 124629 997032 [ 0 0 124629 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Request_Control: 62432 499456 [ 0 0 0 0 62432 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Response_Data: 8904 641088 [ 0 8904 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_ResponseLocal_Data: 3 216 [ 0 3 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_7_Persistent_Control: 124628 997024 [ 0 0 124628 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_8_Request_Control: 71348 570784 [ 0 0 0 0 71348 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_8_Response_Control: 71173 569384 [ 0 71173 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_8_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_9_Request_Control: 71348 570784 [ 0 0 0 71348 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_9_Persistent_Control: 142433 1139464 [ 0 0 142433 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 97883
+Ifetch 0
+Store 52729
+L1_Replacement 0
+Data_Shared 0
+Data_Owner 17
+Data_All_Tokens 8891
+Ack 2
+Ack_All_Tokens 6
+Transient_GETX 0
+Transient_Local_GETX 21689
+Transient_GETS 0
+Transient_Local_GETS 40744
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 23662
+Persistent_GETS 44658
+Own_Lock_or_Unlock 74113
+Request_Timeout 8913
+Use_TimeoutStarverX 2
+Use_TimeoutStarverS 2
+Use_TimeoutNoStarvers 8893
+
+ - Transitions -
+NP Load 1
+NP Ifetch 0 <--
+NP Store 1
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 10
+I Ifetch 0 <--
+I Store 1
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 3
+
+S Load 1
+S Ifetch 0 <--
+S Store 2
+S L1_Replacement 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 1
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 17
+O Ifetch 0 <--
+O Store 6
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 10
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 13
+
+M Load 134
+M Ifetch 0 <--
+M Store 88
+M L1_Replacement 0 <--
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 5
+M Persistent_GETS 8
+M Own_Lock_or_Unlock 66
+
+MM Load 37466
+MM Ifetch 0 <--
+MM Store 20004
+MM L1_Replacement 0 <--
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 3064
+MM Persistent_GETS 5816
+MM Own_Lock_or_Unlock 8723
+
+M_W Load 10517
+M_W Ifetch 0 <--
+M_W Store 5696
+M_W L1_Replacement 0 <--
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 1616
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 2909
+M_W Persistent_GETX 0 <--
+M_W Persistent_GETS 0 <--
+M_W Own_Lock_or_Unlock 3
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 101
+
+MM_W Load 43923
+MM_W Ifetch 0 <--
+MM_W Store 23840
+MM_W L1_Replacement 0 <--
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 924
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 1714
+MM_W Persistent_GETX 2
+MM_W Persistent_GETS 2
+MM_W Own_Lock_or_Unlock 91
+MM_W Use_TimeoutStarverX 2
+MM_W Use_TimeoutStarverS 2
+MM_W Use_TimeoutNoStarvers 8792
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 1
+IM Data_All_Tokens 3091
+IM Ack 2
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 230
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 445
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 5661
+IM Persistent_GETS 10789
+IM Own_Lock_or_Unlock 3096
+IM Request_Timeout 2248
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 3
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 5
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 0 <--
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 6
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 2
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 0 <--
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 0 <--
+OM Persistent_GETS 1
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 0 <--
+IS Data_Owner 16
+IS Data_All_Tokens 5797
+IS Ack 0 <--
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 462
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 754
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 10798
+IS Persistent_GETS 20156
+IS Own_Lock_or_Unlock 5817
+IS Request_Timeout 4250
+
+I_L Load 5803
+I_L Ifetch 0 <--
+I_L Store 3086
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 0 <--
+I_L Persistent_GETS 0 <--
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 11
+S_L Ifetch 0 <--
+S_L Store 5
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 3
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 0 <--
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 6400
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 12121
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 1406
+IM_L Persistent_GETS 2774
+IM_L Own_Lock_or_Unlock 19535
+IM_L Request_Timeout 843
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 6
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 0 <--
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 12039
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 22801
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 2726
+IS_L Persistent_GETS 5112
+IS_L Own_Lock_or_Unlock 36757
+IS_L Request_Timeout 1572
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 1 ---
+ - Event Counts -
+Load 97697
+Ifetch 0
+Store 52572
+L1_Replacement 0
+Data_Shared 0
+Data_Owner 14
+Data_All_Tokens 8894
+Ack 0
+Ack_All_Tokens 6
+Transient_GETX 0
+Transient_Local_GETX 21664
+Transient_GETS 0
+Transient_Local_GETS 40769
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 23737
+Persistent_GETS 44880
+Own_Lock_or_Unlock 73816
+Request_Timeout 9321
+Use_TimeoutStarverX 2
+Use_TimeoutStarverS 5
+Use_TimeoutNoStarvers 8893
+
+ - Transitions -
+NP Load 0 <--
+NP Ifetch 0 <--
+NP Store 2
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 8
+I Ifetch 0 <--
+I Store 4
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 5
+
+S Load 8
+S Ifetch 0 <--
+S Store 5
+S L1_Replacement 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 5
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 8
+O Ifetch 0 <--
+O Store 6
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 7
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 8
+
+M Load 132
+M Ifetch 0 <--
+M Store 87
+M L1_Replacement 0 <--
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 3
+M Persistent_GETS 16
+M Own_Lock_or_Unlock 71
+
+MM Load 37172
+MM Ifetch 0 <--
+MM Store 19876
+MM L1_Replacement 0 <--
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 3054
+MM Persistent_GETS 5820
+MM Own_Lock_or_Unlock 8677
+
+M_W Load 10230
+M_W Ifetch 0 <--
+M_W Store 5669
+M_W L1_Replacement 0 <--
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 1592
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 2903
+M_W Persistent_GETX 0 <--
+M_W Persistent_GETS 0 <--
+M_W Own_Lock_or_Unlock 13
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 106
+
+MM_W Load 44323
+MM_W Ifetch 0 <--
+MM_W Store 23814
+MM_W L1_Replacement 0 <--
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 931
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 1725
+MM_W Persistent_GETX 2
+MM_W Persistent_GETS 5
+MM_W Own_Lock_or_Unlock 109
+MM_W Use_TimeoutStarverX 2
+MM_W Use_TimeoutStarverS 5
+MM_W Use_TimeoutNoStarvers 8787
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 1
+IM Data_All_Tokens 3114
+IM Ack 0 <--
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 246
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 435
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 5733
+IM Persistent_GETS 10880
+IM Own_Lock_or_Unlock 3030
+IM Request_Timeout 2402
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 5
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 7
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 1
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 6
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 4
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 1
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 0 <--
+OM Persistent_GETS 1
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 0 <--
+IS Data_Owner 13
+IS Data_All_Tokens 5775
+IS Ack 0 <--
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 420
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 786
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 10679
+IS Persistent_GETS 20087
+IS Own_Lock_or_Unlock 5624
+IS Request_Timeout 4436
+
+I_L Load 5781
+I_L Ifetch 0 <--
+I_L Store 3103
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 3
+I_L Persistent_GETS 3
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 35
+S_L Ifetch 0 <--
+S_L Store 6
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 10
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 0 <--
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 6515
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 12145
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 1461
+IM_L Persistent_GETS 2768
+IM_L Own_Lock_or_Unlock 19715
+IM_L Request_Timeout 870
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 7
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 0 <--
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 11937
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 22773
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 2802
+IS_L Persistent_GETS 5300
+IS_L Own_Lock_or_Unlock 36547
+IS_L Request_Timeout 1613
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 2 ---
+ - Event Counts -
+Load 97956
+Ifetch 0
+Store 52878
+L1_Replacement 0
+Data_Shared 0
+Data_Owner 17
+Data_All_Tokens 8890
+Ack 2
+Ack_All_Tokens 10
+Transient_GETX 0
+Transient_Local_GETX 21675
+Transient_GETS 0
+Transient_Local_GETS 40754
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 23962
+Persistent_GETS 45240
+Own_Lock_or_Unlock 73231
+Request_Timeout 8987
+Use_TimeoutStarverX 5
+Use_TimeoutStarverS 10
+Use_TimeoutNoStarvers 8885
+
+ - Transitions -
+NP Load 1
+NP Ifetch 0 <--
+NP Store 1
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 4
+I Ifetch 0 <--
+I Store 3
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 4
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 2
+S L1_Replacement 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 0 <--
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 23
+O Ifetch 0 <--
+O Store 10
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 1
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 7
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 13
+
+M Load 140
+M Ifetch 0 <--
+M Store 83
+M L1_Replacement 0 <--
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 3
+M Persistent_GETS 11
+M Own_Lock_or_Unlock 63
+
+MM Load 37371
+MM Ifetch 0 <--
+MM Store 20167
+MM L1_Replacement 0 <--
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 3107
+MM Persistent_GETS 5764
+MM Own_Lock_or_Unlock 8676
+
+M_W Load 10582
+M_W Ifetch 0 <--
+M_W Store 5688
+M_W L1_Replacement 0 <--
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 1627
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 2843
+M_W Persistent_GETX 1
+M_W Persistent_GETS 0 <--
+M_W Own_Lock_or_Unlock 3
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 97
+
+MM_W Load 44020
+MM_W Ifetch 0 <--
+MM_W Store 23825
+MM_W L1_Replacement 0 <--
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 938
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 1683
+MM_W Persistent_GETX 4
+MM_W Persistent_GETS 10
+MM_W Own_Lock_or_Unlock 101
+MM_W Use_TimeoutStarverX 5
+MM_W Use_TimeoutStarverS 10
+MM_W Use_TimeoutNoStarvers 8788
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 0 <--
+IM Data_All_Tokens 3101
+IM Ack 1
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 248
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 441
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 5858
+IM Persistent_GETS 10624
+IM Own_Lock_or_Unlock 2831
+IM Request_Timeout 2274
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 4
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 7
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 1
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 10
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 0 <--
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 1
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 0 <--
+OM Persistent_GETS 0 <--
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 0 <--
+IS Data_Owner 17
+IS Data_All_Tokens 5785
+IS Ack 0 <--
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 478
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 790
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 10533
+IS Persistent_GETS 20399
+IS Own_Lock_or_Unlock 5227
+IS Request_Timeout 4208
+
+I_L Load 5799
+I_L Ifetch 0 <--
+I_L Store 3090
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 7
+I_L Persistent_GETS 14
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 16
+S_L Ifetch 0 <--
+S_L Store 9
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 2
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 0 <--
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 6414
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 12170
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 1571
+IM_L Persistent_GETS 2954
+IM_L Own_Lock_or_Unlock 19572
+IM_L Request_Timeout 872
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 9
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 0 <--
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 11956
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 22825
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 2878
+IS_L Persistent_GETS 5464
+IS_L Own_Lock_or_Unlock 36730
+IS_L Request_Timeout 1633
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 3 ---
+ - Event Counts -
+Load 97904
+Ifetch 0
+Store 52888
+L1_Replacement 0
+Data_Shared 0
+Data_Owner 12
+Data_All_Tokens 8895
+Ack 1
+Ack_All_Tokens 5
+Transient_GETX 0
+Transient_Local_GETX 21715
+Transient_GETS 0
+Transient_Local_GETS 40719
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 23965
+Persistent_GETS 45225
+Own_Lock_or_Unlock 73243
+Request_Timeout 8974
+Use_TimeoutStarverX 14
+Use_TimeoutStarverS 17
+Use_TimeoutNoStarvers 8869
+
+ - Transitions -
+NP Load 2
+NP Ifetch 0 <--
+NP Store 0 <--
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 6
+I Ifetch 0 <--
+I Store 2
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 2
+
+S Load 1
+S Ifetch 0 <--
+S Store 1
+S L1_Replacement 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 1
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 3
+O Ifetch 0 <--
+O Store 5
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 7
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 10
+
+M Load 166
+M Ifetch 0 <--
+M Store 91
+M L1_Replacement 0 <--
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 6
+M Persistent_GETS 11
+M Own_Lock_or_Unlock 70
+
+MM Load 37368
+MM Ifetch 0 <--
+MM Store 20351
+MM L1_Replacement 0 <--
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 3114
+MM Persistent_GETS 5738
+MM Own_Lock_or_Unlock 8624
+
+M_W Load 10547
+M_W Ifetch 0 <--
+M_W Store 5719
+M_W L1_Replacement 0 <--
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 1540
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 2994
+M_W Persistent_GETX 0 <--
+M_W Persistent_GETS 1
+M_W Own_Lock_or_Unlock 0 <--
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 108
+
+MM_W Load 43970
+MM_W Ifetch 0 <--
+MM_W Store 23652
+MM_W L1_Replacement 0 <--
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 858
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 1705
+MM_W Persistent_GETX 13
+MM_W Persistent_GETS 15
+MM_W Own_Lock_or_Unlock 31
+MM_W Use_TimeoutStarverX 14
+MM_W Use_TimeoutStarverS 17
+MM_W Use_TimeoutNoStarvers 8761
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 0 <--
+IM Data_All_Tokens 3063
+IM Ack 1
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 239
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 456
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 5615
+IM Persistent_GETS 10610
+IM Own_Lock_or_Unlock 2866
+IM Request_Timeout 2287
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 5
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 5
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 0 <--
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 5
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 3
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 1
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 0 <--
+OM Persistent_GETS 0 <--
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 0 <--
+IS Data_Owner 12
+IS Data_All_Tokens 5825
+IS Ack 0 <--
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 459
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 801
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 10766
+IS Persistent_GETS 20325
+IS Own_Lock_or_Unlock 5427
+IS Request_Timeout 4341
+
+I_L Load 5831
+I_L Ifetch 0 <--
+I_L Store 3058
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 23
+I_L Persistent_GETS 63
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 10
+S_L Ifetch 0 <--
+S_L Store 9
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 2
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 0 <--
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 6384
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 11985
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 1498
+IM_L Persistent_GETS 3051
+IM_L Own_Lock_or_Unlock 19282
+IM_L Request_Timeout 804
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 9
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 2
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 12219
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 22777
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 2930
+IS_L Persistent_GETS 5411
+IS_L Own_Lock_or_Unlock 36920
+IS_L Request_Timeout 1542
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 4 ---
+ - Event Counts -
+Load 98146
+Ifetch 0
+Store 52672
+L1_Replacement 0
+Data_Shared 0
+Data_Owner 14
+Data_All_Tokens 8899
+Ack 2
+Ack_All_Tokens 8
+Transient_GETX 0
+Transient_Local_GETX 21662
+Transient_GETS 0
+Transient_Local_GETS 40763
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 24165
+Persistent_GETS 45609
+Own_Lock_or_Unlock 72659
+Request_Timeout 8980
+Use_TimeoutStarverX 9
+Use_TimeoutStarverS 18
+Use_TimeoutNoStarvers 8880
+
+ - Transitions -
+NP Load 0 <--
+NP Ifetch 0 <--
+NP Store 2
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 3
+I Ifetch 0 <--
+I Store 4
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 1
+
+S Load 4
+S Ifetch 0 <--
+S Store 0 <--
+S L1_Replacement 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 1
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 10
+O Ifetch 0 <--
+O Store 8
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 6
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 13
+
+M Load 171
+M Ifetch 0 <--
+M Store 89
+M L1_Replacement 0 <--
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 5
+M Persistent_GETS 19
+M Own_Lock_or_Unlock 78
+
+MM Load 37528
+MM Ifetch 0 <--
+MM Store 20133
+MM L1_Replacement 0 <--
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 3140
+MM Persistent_GETS 5716
+MM Own_Lock_or_Unlock 8533
+
+M_W Load 10817
+M_W Ifetch 0 <--
+M_W Store 5665
+M_W L1_Replacement 0 <--
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 1495
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 3001
+M_W Persistent_GETX 0 <--
+M_W Persistent_GETS 0 <--
+M_W Own_Lock_or_Unlock 1
+M_W Use_TimeoutStarverX 1
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 113
+
+MM_W Load 43807
+MM_W Ifetch 0 <--
+MM_W Store 23657
+MM_W L1_Replacement 0 <--
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 909
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 1707
+MM_W Persistent_GETX 8
+MM_W Persistent_GETS 17
+MM_W Own_Lock_or_Unlock 62
+MM_W Use_TimeoutStarverX 8
+MM_W Use_TimeoutStarverS 18
+MM_W Use_TimeoutNoStarvers 8767
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 0 <--
+IM Data_All_Tokens 3107
+IM Ack 2
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 258
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 445
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 5632
+IM Persistent_GETS 10908
+IM Own_Lock_or_Unlock 2711
+IM Request_Timeout 2335
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 12
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 6
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 3
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 8
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 4
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 1
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 0 <--
+OM Persistent_GETS 0 <--
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 0 <--
+IS Data_Owner 14
+IS Data_All_Tokens 5778
+IS Ack 0 <--
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 438
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 789
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 10702
+IS Persistent_GETS 20100
+IS Own_Lock_or_Unlock 5014
+IS Request_Timeout 4222
+
+I_L Load 5792
+I_L Ifetch 0 <--
+I_L Store 3096
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 30
+I_L Persistent_GETS 83
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 14
+S_L Ifetch 0 <--
+S_L Store 18
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 2
+S_L Own_Lock_or_Unlock 1
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 1
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 6542
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 12084
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 1616
+IM_L Persistent_GETS 3035
+IM_L Own_Lock_or_Unlock 19635
+IM_L Request_Timeout 831
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 18
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 1
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 12003
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 22733
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 3032
+IS_L Persistent_GETS 5729
+IS_L Own_Lock_or_Unlock 36592
+IS_L Request_Timeout 1592
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 5 ---
+ - Event Counts -
+Load 97311
+Ifetch 0
+Store 52055
+L1_Replacement 0
+Data_Shared 0
+Data_Owner 18
+Data_All_Tokens 8899
+Ack 0
+Ack_All_Tokens 10
+Transient_GETX 0
+Transient_Local_GETX 21662
+Transient_GETS 0
+Transient_Local_GETS 40758
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 24194
+Persistent_GETS 45642
+Own_Lock_or_Unlock 72597
+Request_Timeout 9661
+Use_TimeoutStarverX 33
+Use_TimeoutStarverS 84
+Use_TimeoutNoStarvers 8792
+
+ - Transitions -
+NP Load 1
+NP Ifetch 0 <--
+NP Store 1
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 5
+I Ifetch 0 <--
+I Store 4
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 4
+
+S Load 3
+S Ifetch 0 <--
+S Store 3
+S L1_Replacement 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 2
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 10
+O Ifetch 0 <--
+O Store 10
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 7
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 13
+
+M Load 177
+M Ifetch 0 <--
+M Store 101
+M L1_Replacement 0 <--
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 7
+M Persistent_GETS 27
+M Own_Lock_or_Unlock 89
+
+MM Load 36363
+MM Ifetch 0 <--
+MM Store 19587
+MM L1_Replacement 0 <--
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 3042
+MM Persistent_GETS 5716
+MM Own_Lock_or_Unlock 8378
+
+M_W Load 10939
+M_W Ifetch 0 <--
+M_W Store 5646
+M_W L1_Replacement 0 <--
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 1554
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 2892
+M_W Persistent_GETX 2
+M_W Persistent_GETS 7
+M_W Own_Lock_or_Unlock 18
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 1
+M_W Use_TimeoutNoStarvers 135
+
+MM_W Load 43984
+MM_W Ifetch 0 <--
+MM_W Store 23593
+MM_W L1_Replacement 0 <--
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 931
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 1748
+MM_W Persistent_GETX 28
+MM_W Persistent_GETS 73
+MM_W Own_Lock_or_Unlock 94
+MM_W Use_TimeoutStarverX 33
+MM_W Use_TimeoutStarverS 83
+MM_W Use_TimeoutNoStarvers 8657
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 1
+IM Data_All_Tokens 3100
+IM Ack 0 <--
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 242
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 410
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 5835
+IM Persistent_GETS 10788
+IM Own_Lock_or_Unlock 2636
+IM Request_Timeout 2435
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 16
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 10
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 1
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 10
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 7
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 2
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 1
+OM Persistent_GETS 0 <--
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 0 <--
+IS Data_Owner 17
+IS Data_All_Tokens 5776
+IS Ack 0 <--
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 450
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 792
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 10671
+IS Persistent_GETS 20295
+IS Own_Lock_or_Unlock 4874
+IS Request_Timeout 4489
+
+I_L Load 5794
+I_L Ifetch 0 <--
+I_L Store 3087
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 46
+I_L Persistent_GETS 86
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 35
+S_L Ifetch 0 <--
+S_L Store 23
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 3
+S_L Own_Lock_or_Unlock 5
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 1
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 6417
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 12178
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 1518
+IM_L Persistent_GETS 2984
+IM_L Own_Lock_or_Unlock 19709
+IM_L Request_Timeout 935
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 23
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 6
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 12042
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 22735
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 3044
+IS_L Persistent_GETS 5663
+IS_L Own_Lock_or_Unlock 36754
+IS_L Request_Timeout 1802
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 6 ---
+ - Event Counts -
+Load 99444
+Ifetch 0
+Store 53518
+L1_Replacement 0
+Data_Shared 0
+Data_Owner 13
+Data_All_Tokens 8900
+Ack 1
+Ack_All_Tokens 5
+Transient_GETX 0
+Transient_Local_GETX 21749
+Transient_GETS 0
+Transient_Local_GETS 40681
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 24381
+Persistent_GETS 45743
+Own_Lock_or_Unlock 72309
+Request_Timeout 9444
+Use_TimeoutStarverX 44
+Use_TimeoutStarverS 87
+Use_TimeoutNoStarvers 8774
+
+ - Transitions -
+NP Load 2
+NP Ifetch 0 <--
+NP Store 0 <--
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 6
+I Ifetch 0 <--
+I Store 5
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 2
+
+S Load 9
+S Ifetch 0 <--
+S Store 0 <--
+S L1_Replacement 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 4
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 5
+O Ifetch 0 <--
+O Store 5
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 1
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 7
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 10
+
+M Load 162
+M Ifetch 0 <--
+M Store 91
+M L1_Replacement 0 <--
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 4
+M Persistent_GETS 14
+M Own_Lock_or_Unlock 73
+
+MM Load 39008
+MM Ifetch 0 <--
+MM Store 20869
+MM L1_Replacement 0 <--
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 2879
+MM Persistent_GETS 5876
+MM Own_Lock_or_Unlock 8554
+
+M_W Load 10538
+M_W Ifetch 0 <--
+M_W Store 5755
+M_W L1_Replacement 0 <--
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 1631
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 2932
+M_W Persistent_GETX 5
+M_W Persistent_GETS 7
+M_W Own_Lock_or_Unlock 0 <--
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 109
+
+MM_W Load 43828
+MM_W Ifetch 0 <--
+MM_W Store 23762
+MM_W L1_Replacement 0 <--
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 870
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 1676
+MM_W Persistent_GETX 38
+MM_W Persistent_GETS 79
+MM_W Own_Lock_or_Unlock 15
+MM_W Use_TimeoutStarverX 44
+MM_W Use_TimeoutStarverS 87
+MM_W Use_TimeoutNoStarvers 8665
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 1
+IM Data_All_Tokens 3027
+IM Ack 0 <--
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 258
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 412
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 5696
+IM Persistent_GETS 10383
+IM Own_Lock_or_Unlock 2562
+IM Request_Timeout 2309
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 9
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 1
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 0 <--
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 5
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 3
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 1
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 1
+OM Persistent_GETS 0 <--
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 0 <--
+IS Data_Owner 12
+IS Data_All_Tokens 5862
+IS Ack 0 <--
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 466
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 802
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 10873
+IS Persistent_GETS 20270
+IS Own_Lock_or_Unlock 4969
+IS Request_Timeout 4491
+
+I_L Load 5869
+I_L Ifetch 0 <--
+I_L Store 3021
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 33
+I_L Persistent_GETS 62
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 17
+S_L Ifetch 0 <--
+S_L Store 10
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 1
+S_L Own_Lock_or_Unlock 4
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 0 <--
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 6275
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 11871
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 1685
+IM_L Persistent_GETS 2994
+IM_L Own_Lock_or_Unlock 19101
+IM_L Request_Timeout 880
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 10
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 2
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 12234
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 22987
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 3167
+IS_L Persistent_GETS 6057
+IS_L Own_Lock_or_Unlock 37009
+IS_L Request_Timeout 1764
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 7 ---
+ - Event Counts -
+Load 100001
+Ifetch 0
+Store 54238
+L1_Replacement 0
+Data_Shared 0
+Data_Owner 18
+Data_All_Tokens 8889
+Ack 0
+Ack_All_Tokens 8
+Transient_GETX 0
+Transient_Local_GETX 21714
+Transient_GETS 0
+Transient_Local_GETS 40718
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 24428
+Persistent_GETS 46108
+Own_Lock_or_Unlock 71897
+Request_Timeout 8944
+Use_TimeoutStarverX 9
+Use_TimeoutStarverS 21
+Use_TimeoutNoStarvers 8867
+
+ - Transitions -
+NP Load 1
+NP Ifetch 0 <--
+NP Store 1
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 0 <--
+
+I Load 8
+I Ifetch 0 <--
+I Store 4
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 7
+
+S Load 2
+S Ifetch 0 <--
+S Store 1
+S L1_Replacement 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 2
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 6
+O Ifetch 0 <--
+O Store 8
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 10
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 11
+
+M Load 146
+M Ifetch 0 <--
+M Store 81
+M L1_Replacement 0 <--
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 7
+M Persistent_GETS 10
+M Own_Lock_or_Unlock 72
+
+MM Load 39684
+MM Ifetch 0 <--
+MM Store 21406
+MM L1_Replacement 0 <--
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 3110
+MM Persistent_GETS 5739
+MM Own_Lock_or_Unlock 8649
+
+M_W Load 10251
+M_W Ifetch 0 <--
+M_W Store 5723
+M_W L1_Replacement 0 <--
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 1566
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 2971
+M_W Persistent_GETX 1
+M_W Persistent_GETS 0 <--
+M_W Own_Lock_or_Unlock 0 <--
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 98
+
+MM_W Load 44054
+MM_W Ifetch 0 <--
+MM_W Store 23952
+MM_W L1_Replacement 0 <--
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 849
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 1704
+MM_W Persistent_GETX 7
+MM_W Persistent_GETS 17
+MM_W Own_Lock_or_Unlock 0 <--
+MM_W Use_TimeoutStarverX 9
+MM_W Use_TimeoutStarverS 21
+MM_W Use_TimeoutNoStarvers 8769
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 0 <--
+IM Data_Shared 0 <--
+IM Data_Owner 0 <--
+IM Data_All_Tokens 3061
+IM Ack 0 <--
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 245
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 455
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 5583
+IM Persistent_GETS 10624
+IM Own_Lock_or_Unlock 2485
+IM Request_Timeout 2256
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 3
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 5
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 0 <--
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 8
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 6
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 0 <--
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 0 <--
+OM Persistent_GETS 0 <--
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 0 <--
+IS Data_Shared 0 <--
+IS Data_Owner 18
+IS Data_All_Tokens 5820
+IS Ack 0 <--
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 455
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 791
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 10732
+IS Persistent_GETS 20115
+IS Own_Lock_or_Unlock 4728
+IS Request_Timeout 4324
+
+I_L Load 5831
+I_L Ifetch 0 <--
+I_L Store 3055
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 33
+I_L Persistent_GETS 65
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 18
+S_L Ifetch 0 <--
+S_L Store 7
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 3
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 4
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 6396
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 11977
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 1706
+IM_L Persistent_GETS 3266
+IM_L Own_Lock_or_Unlock 19258
+IM_L Request_Timeout 833
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 7
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 1
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 12180
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 22820
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 3249
+IS_L Persistent_GETS 6272
+IS_L Own_Lock_or_Unlock 36677
+IS_L Request_Timeout 1531
+
+Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GETS 46558
+L1_GETS_Last_Token 0
+L1_GETX 24790
+L1_INV 71173
+Transient_GETX 0
+Transient_GETS 0
+Transient_GETS_Last_Token 0
+L2_Replacement 0
+Writeback_Tokens 0
+Writeback_Shared_Data 0
+Writeback_All_Tokens 0
+Writeback_Owned 0
+Data_Shared 0
+Data_Owner 0
+Data_All_Tokens 0
+Ack 0
+Ack_All_Tokens 0
+Persistent_GETX 27489
+Persistent_GETS 51827
+Own_Lock_or_Unlock 63117
+
+ - Transitions -
+NP L1_GETS 58
+NP L1_GETX 130
+NP L1_INV 77
+NP Transient_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Writeback_Tokens 0 <--
+NP Writeback_Shared_Data 0 <--
+NP Writeback_All_Tokens 0 <--
+NP Writeback_Owned 0 <--
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 63117
+
+I L1_GETS 0 <--
+I L1_GETS_Last_Token 0 <--
+I L1_GETX 0 <--
+I L1_INV 0 <--
+I Transient_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I L2_Replacement 0 <--
+I Writeback_Tokens 0 <--
+I Writeback_Shared_Data 0 <--
+I Writeback_All_Tokens 0 <--
+I Writeback_Owned 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 0 <--
+
+S L1_GETS 0 <--
+S L1_GETS_Last_Token 0 <--
+S L1_GETX 0 <--
+S L1_INV 0 <--
+S Transient_GETX 0 <--
+S Transient_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S L2_Replacement 0 <--
+S Writeback_Tokens 0 <--
+S Writeback_Shared_Data 0 <--
+S Writeback_All_Tokens 0 <--
+S Writeback_Owned 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O L1_GETS 0 <--
+O L1_GETS_Last_Token 0 <--
+O L1_GETX 0 <--
+O L1_INV 0 <--
+O Transient_GETX 0 <--
+O Transient_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O L2_Replacement 0 <--
+O Writeback_Tokens 0 <--
+O Writeback_Shared_Data 0 <--
+O Writeback_All_Tokens 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 0 <--
+
+M L1_GETS 0 <--
+M L1_GETX 0 <--
+M L1_INV 0 <--
+M Transient_GETX 0 <--
+M Transient_GETS 0 <--
+M L2_Replacement 0 <--
+M Persistent_GETX 0 <--
+M Persistent_GETS 0 <--
+M Own_Lock_or_Unlock 0 <--
+
+I_L L1_GETS 46500
+I_L L1_GETX 24660
+I_L L1_INV 71096
+I_L Transient_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L L2_Replacement 0 <--
+I_L Writeback_Tokens 0 <--
+I_L Writeback_Shared_Data 0 <--
+I_L Writeback_All_Tokens 0 <--
+I_L Writeback_Owned 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Persistent_GETX 27489
+I_L Persistent_GETS 51827
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L L1_GETS 0 <--
+S_L L1_GETS_Last_Token 0 <--
+S_L L1_GETX 0 <--
+S_L L1_INV 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L L2_Replacement 0 <--
+S_L Writeback_Tokens 0 <--
+S_L Writeback_Shared_Data 0 <--
+S_L Writeback_All_Tokens 0 <--
+S_L Writeback_Owned 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer:
+ memory_total_requests: 2
+ memory_reads: 2
+ memory_writes: 0
+ memory_refreshes: 22
+ memory_total_request_delays: 31
+ memory_delays_per_request: 15.5
+ memory_delays_in_input_queue: 1
+ memory_delays_behind_head_of_bank_queue: 10
+ memory_delays_stalled_at_head_of_bank_queue: 20
+ memory_stalls_for_bank_busy: 20
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 0
+ memory_stalls_for_bus: 0
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 0
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 25022
+GETS 46731
+Lockdown 79316
+Unlockdown 63117
+Own_Lock_or_Unlock 0
+Data_Owner 0
+Data_All_Tokens 0
+Ack_Owner 0
+Ack_Owner_All_Tokens 0
+Tokens 0
+Ack_All_Tokens 0
+Request_Timeout 0
+Memory_Data 2
+Memory_Ack 0
+DMA_READ 0
+DMA_WRITE 0
+DMA_WRITE_All_Tokens 0
+
+ - Transitions -
+O GETX 0 <--
+O GETS 2
+O Lockdown 0 <--
+O Own_Lock_or_Unlock 0 <--
+O Data_Owner 0 <--
+O Data_All_Tokens 0 <--
+O Tokens 0 <--
+O Ack_All_Tokens 0 <--
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+O DMA_WRITE_All_Tokens 0 <--
+
+NO GETX 194
+NO GETS 56
+NO Lockdown 63118
+NO Own_Lock_or_Unlock 0 <--
+NO Data_Owner 0 <--
+NO Data_All_Tokens 0 <--
+NO Ack_Owner 0 <--
+NO Ack_Owner_All_Tokens 0 <--
+NO Tokens 0 <--
+NO DMA_READ 0 <--
+NO DMA_WRITE 0 <--
+
+L GETX 24596
+L GETS 46500
+L Lockdown 16198
+L Unlockdown 63117
+L Own_Lock_or_Unlock 0 <--
+L Data_Owner 0 <--
+L Data_All_Tokens 0 <--
+L Ack_Owner 0 <--
+L Ack_Owner_All_Tokens 0 <--
+L Tokens 0 <--
+L DMA_READ 0 <--
+L DMA_WRITE 0 <--
+
+O_W GETX 0 <--
+O_W GETS 0 <--
+O_W Lockdown 0 <--
+O_W Unlockdown 0 <--
+O_W Own_Lock_or_Unlock 0 <--
+O_W Data_Owner 0 <--
+O_W Ack_Owner 0 <--
+O_W Tokens 0 <--
+O_W Ack_All_Tokens 0 <--
+O_W Memory_Data 0 <--
+O_W Memory_Ack 0 <--
+O_W DMA_READ 0 <--
+O_W DMA_WRITE 0 <--
+
+L_O_W GETX 0 <--
+L_O_W GETS 0 <--
+L_O_W Lockdown 0 <--
+L_O_W Unlockdown 0 <--
+L_O_W Own_Lock_or_Unlock 0 <--
+L_O_W Data_Owner 0 <--
+L_O_W Ack_Owner 0 <--
+L_O_W Tokens 0 <--
+L_O_W Ack_All_Tokens 0 <--
+L_O_W Memory_Data 0 <--
+L_O_W Memory_Ack 0 <--
+L_O_W DMA_READ 0 <--
+L_O_W DMA_WRITE 0 <--
+
+L_NO_W GETX 0 <--
+L_NO_W GETS 0 <--
+L_NO_W Lockdown 0 <--
+L_NO_W Unlockdown 0 <--
+L_NO_W Own_Lock_or_Unlock 0 <--
+L_NO_W Data_Owner 0 <--
+L_NO_W Ack_Owner 0 <--
+L_NO_W Tokens 0 <--
+L_NO_W Ack_All_Tokens 0 <--
+L_NO_W Memory_Data 0 <--
+L_NO_W DMA_READ 0 <--
+L_NO_W DMA_WRITE 0 <--
+
+DR_L_W GETX 0 <--
+DR_L_W GETS 0 <--
+DR_L_W Lockdown 0 <--
+DR_L_W Unlockdown 0 <--
+DR_L_W Own_Lock_or_Unlock 0 <--
+DR_L_W Data_Owner 0 <--
+DR_L_W Ack_Owner 0 <--
+DR_L_W Tokens 0 <--
+DR_L_W Ack_All_Tokens 0 <--
+DR_L_W Request_Timeout 0 <--
+DR_L_W Memory_Data 0 <--
+DR_L_W DMA_READ 0 <--
+DR_L_W DMA_WRITE 0 <--
+
+NO_W GETX 232
+NO_W GETS 173
+NO_W Lockdown 0 <--
+NO_W Unlockdown 0 <--
+NO_W Own_Lock_or_Unlock 0 <--
+NO_W Data_Owner 0 <--
+NO_W Ack_Owner 0 <--
+NO_W Tokens 0 <--
+NO_W Ack_All_Tokens 0 <--
+NO_W Memory_Data 2
+NO_W DMA_READ 0 <--
+NO_W DMA_WRITE 0 <--
+
+O_DW_W GETX 0 <--
+O_DW_W GETS 0 <--
+O_DW_W Data_Owner 0 <--
+O_DW_W Ack_Owner 0 <--
+O_DW_W Tokens 0 <--
+O_DW_W Ack_All_Tokens 0 <--
+O_DW_W Memory_Ack 0 <--
+O_DW_W DMA_READ 0 <--
+O_DW_W DMA_WRITE 0 <--
+
+O_DR_W GETX 0 <--
+O_DR_W GETS 0 <--
+O_DR_W Lockdown 0 <--
+O_DR_W Unlockdown 0 <--
+O_DR_W Own_Lock_or_Unlock 0 <--
+O_DR_W Data_Owner 0 <--
+O_DR_W Ack_Owner 0 <--
+O_DR_W Tokens 0 <--
+O_DR_W Ack_All_Tokens 0 <--
+O_DR_W Memory_Data 0 <--
+O_DR_W DMA_READ 0 <--
+O_DR_W DMA_WRITE 0 <--
+
+O_DW GETX 0 <--
+O_DW GETS 0 <--
+O_DW Lockdown 0 <--
+O_DW Own_Lock_or_Unlock 0 <--
+O_DW Data_Owner 0 <--
+O_DW Data_All_Tokens 0 <--
+O_DW Ack_Owner 0 <--
+O_DW Ack_Owner_All_Tokens 0 <--
+O_DW Tokens 0 <--
+O_DW Ack_All_Tokens 0 <--
+O_DW DMA_READ 0 <--
+O_DW DMA_WRITE 0 <--
+
+NO_DW GETX 0 <--
+NO_DW GETS 0 <--
+NO_DW Lockdown 0 <--
+NO_DW Own_Lock_or_Unlock 0 <--
+NO_DW Data_Owner 0 <--
+NO_DW Data_All_Tokens 0 <--
+NO_DW Tokens 0 <--
+NO_DW Request_Timeout 0 <--
+NO_DW DMA_READ 0 <--
+NO_DW DMA_WRITE 0 <--
+
+NO_DR GETX 0 <--
+NO_DR GETS 0 <--
+NO_DR Lockdown 0 <--
+NO_DR Own_Lock_or_Unlock 0 <--
+NO_DR Data_Owner 0 <--
+NO_DR Data_All_Tokens 0 <--
+NO_DR Tokens 0 <--
+NO_DR Request_Timeout 0 <--
+NO_DR DMA_READ 0 <--
+NO_DR DMA_WRITE 0 <--
+
+DW_L GETX 0 <--
+DW_L GETS 0 <--
+DW_L Lockdown 0 <--
+DW_L Unlockdown 0 <--
+DW_L Own_Lock_or_Unlock 0 <--
+DW_L Data_Owner 0 <--
+DW_L Data_All_Tokens 0 <--
+DW_L Ack_Owner 0 <--
+DW_L Ack_Owner_All_Tokens 0 <--
+DW_L Tokens 0 <--
+DW_L Request_Timeout 0 <--
+DW_L DMA_READ 0 <--
+DW_L DMA_WRITE 0 <--
+
+DR_L GETX 0 <--
+DR_L GETS 0 <--
+DR_L Lockdown 0 <--
+DR_L Unlockdown 0 <--
+DR_L Own_Lock_or_Unlock 0 <--
+DR_L Data_Owner 0 <--
+DR_L Data_All_Tokens 0 <--
+DR_L Ack_Owner 0 <--
+DR_L Ack_Owner_All_Tokens 0 <--
+DR_L Tokens 0 <--
+DR_L Request_Timeout 0 <--
+DR_L DMA_READ 0 <--
+DR_L DMA_WRITE 0 <--
+
--- /dev/null
+system.cpu7: completed 10000 read accesses @318017
+system.cpu2: completed 10000 read accesses @320606
+system.cpu4: completed 10000 read accesses @323032
+system.cpu3: completed 10000 read accesses @325540
+system.cpu1: completed 10000 read accesses @326237
+system.cpu0: completed 10000 read accesses @334891
+system.cpu6: completed 10000 read accesses @335973
+system.cpu5: completed 10000 read accesses @338167
+system.cpu7: completed 20000 read accesses @641721
+system.cpu4: completed 20000 read accesses @650207
+system.cpu2: completed 20000 read accesses @650997
+system.cpu3: completed 20000 read accesses @655547
+system.cpu1: completed 20000 read accesses @658571
+system.cpu6: completed 20000 read accesses @659101
+system.cpu0: completed 20000 read accesses @665545
+system.cpu5: completed 20000 read accesses @668660
+system.cpu7: completed 30000 read accesses @967051
+system.cpu2: completed 30000 read accesses @980241
+system.cpu4: completed 30000 read accesses @981752
+system.cpu6: completed 30000 read accesses @982555
+system.cpu3: completed 30000 read accesses @983533
+system.cpu1: completed 30000 read accesses @988722
+system.cpu0: completed 30000 read accesses @995306
+system.cpu5: completed 30000 read accesses @998193
+system.cpu7: completed 40000 read accesses @1292004
+system.cpu4: completed 40000 read accesses @1308492
+system.cpu6: completed 40000 read accesses @1308579
+system.cpu2: completed 40000 read accesses @1312752
+system.cpu3: completed 40000 read accesses @1315420
+system.cpu1: completed 40000 read accesses @1322630
+system.cpu0: completed 40000 read accesses @1325206
+system.cpu5: completed 40000 read accesses @1331673
+system.cpu7: completed 50000 read accesses @1612614
+system.cpu6: completed 50000 read accesses @1633357
+system.cpu4: completed 50000 read accesses @1639815
+system.cpu2: completed 50000 read accesses @1645007
+system.cpu3: completed 50000 read accesses @1648886
+system.cpu0: completed 50000 read accesses @1653577
+system.cpu1: completed 50000 read accesses @1654071
+system.cpu5: completed 50000 read accesses @1661892
+system.cpu7: completed 60000 read accesses @1934242
+system.cpu6: completed 60000 read accesses @1953245
+system.cpu4: completed 60000 read accesses @1969088
+system.cpu2: completed 60000 read accesses @1978395
+system.cpu3: completed 60000 read accesses @1980508
+system.cpu0: completed 60000 read accesses @1980832
+system.cpu1: completed 60000 read accesses @1989869
+system.cpu5: completed 60000 read accesses @2000681
+system.cpu7: completed 70000 read accesses @2258807
+system.cpu6: completed 70000 read accesses @2276271
+system.cpu4: completed 70000 read accesses @2301792
+system.cpu2: completed 70000 read accesses @2307314
+system.cpu3: completed 70000 read accesses @2311283
+system.cpu0: completed 70000 read accesses @2312940
+system.cpu1: completed 70000 read accesses @2317714
+system.cpu5: completed 70000 read accesses @2327977
+system.cpu7: completed 80000 read accesses @2583771
+system.cpu6: completed 80000 read accesses @2602700
+system.cpu4: completed 80000 read accesses @2632241
+system.cpu2: completed 80000 read accesses @2635301
+system.cpu3: completed 80000 read accesses @2641526
+system.cpu0: completed 80000 read accesses @2641647
+system.cpu1: completed 80000 read accesses @2649443
+system.cpu5: completed 80000 read accesses @2661743
+system.cpu7: completed 90000 read accesses @2907382
+system.cpu6: completed 90000 read accesses @2926398
+system.cpu4: completed 90000 read accesses @2962227
+system.cpu2: completed 90000 read accesses @2968253
+system.cpu3: completed 90000 read accesses @2971557
+system.cpu0: completed 90000 read accesses @2972136
+system.cpu1: completed 90000 read accesses @2977260
+system.cpu5: completed 90000 read accesses @2992697
+system.cpu7: completed 100000 read accesses @3231932
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 15:54:34
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 15:55:47
+M5 executing on svvint04
+command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 3231932 because maximum number of loads reached
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 345240 # Number of bytes of host memory used
+host_seconds 39.07 # Real time elapsed on the host
+host_tick_rate 82719 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.003232 # Number of seconds simulated
+sim_ticks 3231932 # Number of ticks simulated
+system.cpu0.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 97882 # number of read accesses completed
+system.cpu0.num_writes 52728 # number of write accesses completed
+system.cpu1.num_copies 0 # number of copy accesses completed
+system.cpu1.num_reads 97696 # number of read accesses completed
+system.cpu1.num_writes 52571 # number of write accesses completed
+system.cpu2.num_copies 0 # number of copy accesses completed
+system.cpu2.num_reads 97954 # number of read accesses completed
+system.cpu2.num_writes 52878 # number of write accesses completed
+system.cpu3.num_copies 0 # number of copy accesses completed
+system.cpu3.num_reads 97904 # number of read accesses completed
+system.cpu3.num_writes 52886 # number of write accesses completed
+system.cpu4.num_copies 0 # number of copy accesses completed
+system.cpu4.num_reads 98144 # number of read accesses completed
+system.cpu4.num_writes 52672 # number of write accesses completed
+system.cpu5.num_copies 0 # number of copy accesses completed
+system.cpu5.num_reads 97310 # number of read accesses completed
+system.cpu5.num_writes 52054 # number of write accesses completed
+system.cpu6.num_copies 0 # number of copy accesses completed
+system.cpu6.num_reads 99443 # number of read accesses completed
+system.cpu6.num_writes 53518 # number of write accesses completed
+system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu7.num_reads 100000 # number of read accesses completed
+system.cpu7.num_writes 54238 # number of write accesses completed
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu0]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+
+[system.cpu1]
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+test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
+
+[system.cpu2]
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+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
+
+[system.cpu3]
+type=MemTest
+atomic=false
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+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+max_loads=100000
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+percent_dest_unaligned=50
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+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
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+memory_size=65536
+percent_dest_unaligned=50
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+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=0
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8
+num_int_nodes=10
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
+buffer_size=0
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
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+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+buffer_size=0
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
+transitions_per_cycle=32
+version=1
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
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+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache]
+type=RubyCache
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+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
+type=RubyCache
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+size=256
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
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+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+L2cacheMemory=system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory
+buffer_size=0
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+transitions_per_cycle=32
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+
+[system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory]
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+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer]
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+version=0
+physMemPort=system.physmem.port[2]
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+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache]
+type=RubyCache
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+size=256
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
+type=RubyCache
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+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links3]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links3.ext_node
+int_node=3
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links3.ext_node]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
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+L2cacheMemory=system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory
+buffer_size=0
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+
+[system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory]
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+size=512
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer]
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+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
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+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
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+
+[system.ruby.network.topology.ext_links4]
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+weight=1
+
+[system.ruby.network.topology.ext_links4.ext_node]
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+L2cacheMemory=system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory
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+
+[system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory]
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+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer]
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+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache]
+type=RubyCache
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+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
+type=RubyCache
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+size=256
+
+[system.ruby.network.topology.ext_links5]
+type=ExtLink
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+int_node=5
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links5.ext_node]
+type=L1Cache_Controller
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+L2cacheMemory=system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory
+buffer_size=0
+cache_response_latency=12
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+version=5
+
+[system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
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+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer]
+type=RubySequencer
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+dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
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+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache]
+type=RubyCache
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+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
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+
+[system.ruby.network.topology.ext_links6]
+type=ExtLink
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+ext_node=system.ruby.network.topology.ext_links6.ext_node
+int_node=6
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links6.ext_node]
+type=L1Cache_Controller
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+L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+L2cacheMemory=system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory
+buffer_size=0
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
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+sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
+transitions_per_cycle=32
+version=6
+
+[system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
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+size=512
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
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+icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
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+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links7]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links7.ext_node
+int_node=7
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links7.ext_node]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+L2cacheMemory=system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory
+buffer_size=0
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
+transitions_per_cycle=32
+version=7
+
+[system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links8]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links8.ext_node
+int_node=8
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links8.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links8.ext_node.directory
+memBuffer=system.ruby.network.topology.ext_links8.ext_node.memBuffer
+memory_controller_latency=12
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links8.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links8.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=3
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=4
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=5
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=6
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=7
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=8
+node_b=9
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 0
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: active, unordered
+virtual_net_4: active, ordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/28/2010 11:56:06
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 54
+Elapsed_time_in_minutes: 0.9
+Elapsed_time_in_hours: 0.015
+Elapsed_time_in_days: 0.000625
+
+Virtual_time_in_seconds: 49.12
+Virtual_time_in_minutes: 0.818667
+Virtual_time_in_hours: 0.0136444
+Virtual_time_in_days: 0.000568519
+
+Ruby_current_time: 4369301
+Ruby_start_time: 0
+Ruby_cycles: 4369301
+
+mbytes_resident: 30.4922
+mbytes_total: 30.4961
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+
+ruby_cycles_executed: 34954416 [ 4369302 4369302 4369302 4369302 4369302 4369302 4369302 4369302 ]
+
+transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
+transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
+cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
+
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1228166 average: 1.9556 | standard deviation: 0.205985 | 0 54532 1173634 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 32 max: 3707 count: 1228150 average: 54.9169 | standard deviation: 182.221 | 1071820 301 18738 8313 776 31105 485 5222 784 21916 1363 3831 11827 1144 5147 311 6447 348 5347 3491 401 4333 238 2990 2520 1024 1952 559 2236 204 1844 627 1098 1352 228 1094 126 981 581 358 565 247 482 282 408 218 298 212 215 299 63 214 70 170 143 67 110 37 102 34 60 33 45 46 18 34 18 34 21 11 21 10 16 13 9 7 7 9 3 11 3 2 2 3 1 1 1 1 2 1 0 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 32 max: 3707 count: 797798 average: 52.0062 | standard deviation: 177.259 | 701441 1 11975 5115 188 19843 34 3274 42 14118 645 2330 7346 537 3336 17 4059 76 3334 2170 159 2767 65 1876 1543 569 1195 304 1434 60 1183 339 702 807 106 706 65 633 358 207 338 147 275 146 257 133 186 127 130 190 32 131 38 104 95 47 68 25 68 23 37 18 28 27 10 23 10 15 12 8 17 7 11 7 6 3 5 7 1 8 2 2 2 3 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 32 max: 3357 count: 430352 average: 60.3128 | standard deviation: 190.962 | 370379 300 6763 3198 588 11262 451 1948 742 7798 718 1501 4481 607 1811 294 2388 272 2013 1321 242 1566 173 1114 977 455 757 255 802 144 661 288 396 545 122 388 61 348 223 151 227 100 207 136 151 85 112 85 85 109 31 83 32 66 48 20 42 12 34 11 23 15 17 19 8 11 8 19 9 3 4 3 5 6 3 4 2 2 2 3 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 48
+system_time: 0
+page_reclaims: 6708
+page_faults: 1861
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.251471
+ links_utilized_percent_switch_0_link_0: 0.122959 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.379983 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 19501 1404072 [ 0 19501 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 117532 940256 [ 0 117532 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Forwarded_Control: 136754 1094032 [ 0 0 136754 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 19578 156624 [ 0 0 0 19578 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Data: 19518 1405296 [ 0 19518 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Control: 117236 937888 [ 0 117236 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 19576 156608 [ 19576 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.250926
+ links_utilized_percent_switch_1_link_0: 0.122775 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.379078 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Response_Data: 19456 1400832 [ 0 19456 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Control: 117247 937976 [ 0 117247 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Forwarded_Control: 136801 1094408 [ 0 0 136801 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 19531 156248 [ 0 0 0 19531 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 19425 1398600 [ 0 19425 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 117376 939008 [ 0 117376 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Unblock_Control: 19529 156232 [ 19529 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.250929
+ links_utilized_percent_switch_2_link_0: 0.122806 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.379051 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 19469 1401768 [ 0 19469 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Control: 117241 937928 [ 0 117241 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Forwarded_Control: 136800 1094400 [ 0 0 136800 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 19532 156256 [ 0 0 0 19532 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 19422 1398384 [ 0 19422 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Control: 117378 939024 [ 0 117378 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Unblock_Control: 19530 156240 [ 19530 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 0.251074
+ links_utilized_percent_switch_3_link_0: 0.122798 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.37935 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Response_Data: 19460 1401120 [ 0 19460 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 117299 938392 [ 0 117299 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Forwarded_Control: 136793 1094344 [ 0 0 136793 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 19537 156296 [ 0 0 0 19537 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 19454 1400688 [ 0 19454 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Control: 117339 938712 [ 0 117339 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Unblock_Control: 19537 156296 [ 19537 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 0.251214
+ links_utilized_percent_switch_4_link_0: 0.122557 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_4_link_1: 0.37987 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_4_link_0_Response_Data: 19400 1396800 [ 0 19400 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Response_Control: 116939 935512 [ 0 116939 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Forwarded_Control: 136853 1094824 [ 0 0 136853 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Request_Control: 19479 155832 [ 0 0 0 19479 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Response_Data: 19518 1405296 [ 0 19518 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Response_Control: 117335 938680 [ 0 117335 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Unblock_Control: 19477 155816 [ 19477 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_5_inlinks: 2
+switch_5_outlinks: 2
+links_utilized_percent_switch_5: 0.251252
+ links_utilized_percent_switch_5_link_0: 0.123033 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_5_link_1: 0.379471 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_5_link_0_Response_Data: 19521 1405512 [ 0 19521 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Control: 117630 941040 [ 0 117630 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Forwarded_Control: 136737 1093896 [ 0 0 136737 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Request_Control: 19595 156760 [ 0 0 0 19595 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Data: 19460 1401120 [ 0 19460 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Control: 117277 938216 [ 0 117277 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Unblock_Control: 19593 156744 [ 19593 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_6_inlinks: 2
+switch_6_outlinks: 2
+links_utilized_percent_switch_6: 0.251006
+ links_utilized_percent_switch_6_link_0: 0.122647 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_6_link_1: 0.379365 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_6_link_0_Response_Data: 19422 1398384 [ 0 19422 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Response_Control: 117078 936624 [ 0 117078 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Forwarded_Control: 136830 1094640 [ 0 0 136830 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Request_Control: 19502 156016 [ 0 0 0 19502 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Response_Data: 19460 1401120 [ 0 19460 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Response_Control: 117370 938960 [ 0 117370 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Unblock_Control: 19500 156000 [ 19500 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_7_inlinks: 2
+switch_7_outlinks: 2
+links_utilized_percent_switch_7: 0.251313
+ links_utilized_percent_switch_7_link_0: 0.122995 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_7_link_1: 0.379631 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_7_link_0_Response_Data: 19508 1404576 [ 0 19508 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Response_Control: 117609 940872 [ 0 117609 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Forwarded_Control: 136742 1093936 [ 0 0 136742 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Request_Control: 19590 156720 [ 0 0 0 19590 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Response_Data: 19478 1402416 [ 0 19478 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Response_Control: 117264 938112 [ 0 117264 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Unblock_Control: 19588 156704 [ 19588 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_8_inlinks: 2
+switch_8_outlinks: 2
+links_utilized_percent_switch_8: 0.134184
+ links_utilized_percent_switch_8_link_0: 0.089452 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_8_link_1: 0.178916 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_8_link_0_Request_Control: 156344 1250752 [ 0 0 0 156344 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_0_Unblock_Control: 156330 1250640 [ 156330 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Forwarded_Control: 156330 1250640 [ 0 0 156330 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 9
+switch_9_outlinks: 9
+links_utilized_percent_switch_9: 0.476455
+ links_utilized_percent_switch_9_link_0: 0.491835 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_1: 0.491099 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_2: 0.491225 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_3: 0.491191 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_4: 0.490229 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_5: 0.492134 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_6: 0.490589 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_7: 0.491981 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_8: 0.357808 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_9_link_0_Response_Data: 19501 1404072 [ 0 19501 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_0_Response_Control: 117532 940256 [ 0 117532 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_0_Forwarded_Control: 136754 1094032 [ 0 0 136754 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_1_Response_Data: 19456 1400832 [ 0 19456 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_1_Response_Control: 117247 937976 [ 0 117247 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_1_Forwarded_Control: 136801 1094408 [ 0 0 136801 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_2_Response_Data: 19469 1401768 [ 0 19469 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_2_Response_Control: 117241 937928 [ 0 117241 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_2_Forwarded_Control: 136800 1094400 [ 0 0 136800 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_3_Response_Data: 19460 1401120 [ 0 19460 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_3_Response_Control: 117299 938392 [ 0 117299 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_3_Forwarded_Control: 136793 1094344 [ 0 0 136793 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_4_Response_Data: 19400 1396800 [ 0 19400 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_4_Response_Control: 116939 935512 [ 0 116939 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_4_Forwarded_Control: 136853 1094824 [ 0 0 136853 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_5_Response_Data: 19521 1405512 [ 0 19521 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_5_Response_Control: 117630 941040 [ 0 117630 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_5_Forwarded_Control: 136737 1093896 [ 0 0 136737 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_6_Response_Data: 19422 1398384 [ 0 19422 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_6_Response_Control: 117078 936624 [ 0 117078 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_6_Forwarded_Control: 136830 1094640 [ 0 0 136830 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_7_Response_Data: 19508 1404576 [ 0 19508 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_7_Response_Control: 117609 940872 [ 0 117609 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_7_Forwarded_Control: 136742 1093936 [ 0 0 136742 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_8_Request_Control: 156344 1250752 [ 0 0 0 156344 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_8_Unblock_Control: 156330 1250640 [ 156330 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 19578
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 19578
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 61.4721%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 38.5279%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19578 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19578 average: 1 | standard deviation: 0 | 0 19578 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 99704
+Ifetch 0
+Store 54194
+L2_Replacement 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+Other_GETX 52430
+Other_GETS 84324
+Ack 116988
+Shared_Ack 544
+Data 284
+Shared_Data 700
+Exclusive_Data 18517
+Writeback_Ack 0
+Writeback_Nack 0
+All_acks 700
+All_acks_no_sharers 18876
+
+ - Transitions -
+I Load 12035
+I Ifetch 0 <--
+I Store 6508
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 1411
+S Ifetch 0 <--
+S Store 677
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 23
+S Other_GETS 18
+
+O Load 620
+O Ifetch 0 <--
+O Store 358
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 0 <--
+O Other_GETS 1
+
+M Load 19988
+M Ifetch 0 <--
+M Store 10753
+M L2_Replacement 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M Other_GETX 222
+M Other_GETS 358
+
+MM Load 65650
+MM Ifetch 0 <--
+MM Store 35898
+MM L2_Replacement 0 <--
+MM L1_to_L2 0 <--
+MM L2_to_L1D 0 <--
+MM L2_to_L1I 0 <--
+MM Other_GETX 6953
+MM Other_GETS 11343
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 16954
+IM Other_GETS 26740
+IM Ack 22392
+IM Data 197
+IM Exclusive_Data 7184
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 590
+SM Other_GETS 558
+SM Ack 299
+SM Data 87
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 283
+OM Other_GETS 358
+OM Ack 525
+OM All_acks 0 <--
+OM All_acks_no_sharers 75
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 816
+ISM All_acks_no_sharers 284
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 33932
+M_W All_acks_no_sharers 11333
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 21302
+MM_W All_acks_no_sharers 7184
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 27405
+IS Other_GETS 44948
+IS Ack 35935
+IS Shared_Ack 270
+IS Data 0 <--
+IS Shared_Data 700
+IS Exclusive_Data 11333
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 1787
+SS Shared_Ack 274
+SS All_acks 700
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 19531
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 19531
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_type_LD: 62.0398%
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_type_ST: 37.9602%
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19531 100%
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19531 average: 1 | standard deviation: 0 | 0 19531 ]
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 1 ---
+ - Event Counts -
+Load 99604
+Ifetch 0
+Store 53836
+L2_Replacement 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+Other_GETX 52560
+Other_GETS 84241
+Ack 116625
+Shared_Ack 622
+Data 293
+Shared_Data 700
+Exclusive_Data 18463
+Writeback_Ack 0
+Writeback_Nack 0
+All_acks 700
+All_acks_no_sharers 18829
+
+ - Transitions -
+I Load 12117
+I Ifetch 0 <--
+I Store 6403
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 1272
+S Ifetch 0 <--
+S Store 683
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 17
+S Other_GETS 19
+
+O Load 676
+O Ifetch 0 <--
+O Store 328
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 1
+O Other_GETS 5
+
+M Load 19939
+M Ifetch 0 <--
+M Store 10854
+M L2_Replacement 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M Other_GETX 233
+M Other_GETS 329
+
+MM Load 65600
+MM Ifetch 0 <--
+MM Store 35568
+MM L2_Replacement 0 <--
+MM L1_to_L2 0 <--
+MM L2_to_L1D 0 <--
+MM L2_to_L1I 0 <--
+MM Other_GETX 6942
+MM Other_GETS 11325
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 17278
+IM Other_GETS 26752
+IM Ack 21951
+IM Data 204
+IM Exclusive_Data 7047
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 594
+SM Other_GETS 495
+SM Ack 305
+SM Data 89
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 255
+OM Other_GETS 335
+OM Ack 511
+OM All_acks 0 <--
+OM All_acks_no_sharers 73
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 833
+ISM All_acks_no_sharers 293
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 34390
+M_W All_acks_no_sharers 11416
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 20951
+MM_W All_acks_no_sharers 7047
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 27240
+IS Other_GETS 44981
+IS Ack 35817
+IS Shared_Ack 301
+IS Data 0 <--
+IS Shared_Data 700
+IS Exclusive_Data 11416
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 1867
+SS Shared_Ack 321
+SS All_acks 700
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 19532
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 19532
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_type_LD: 61.8063%
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_type_ST: 38.1937%
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19532 100%
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19532 average: 1 | standard deviation: 0 | 0 19532 ]
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 2 ---
+ - Event Counts -
+Load 99784
+Ifetch 0
+Store 53417
+L2_Replacement 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+Other_GETX 52513
+Other_GETS 84287
+Ack 116642
+Shared_Ack 599
+Data 303
+Shared_Data 728
+Exclusive_Data 18438
+Writeback_Ack 0
+Writeback_Nack 0
+All_acks 728
+All_acks_no_sharers 18802
+
+ - Transitions -
+I Load 12072
+I Ifetch 0 <--
+I Store 6403
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 1236
+S Ifetch 0 <--
+S Store 709
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 19
+S Other_GETS 17
+
+O Load 640
+O Ifetch 0 <--
+O Store 348
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 0 <--
+O Other_GETS 3
+
+M Load 19826
+M Ifetch 0 <--
+M Store 10761
+M L2_Replacement 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M Other_GETX 233
+M Other_GETS 348
+
+MM Load 66010
+MM Ifetch 0 <--
+MM Store 35196
+MM L2_Replacement 0 <--
+MM L1_to_L2 0 <--
+MM L2_to_L1D 0 <--
+MM L2_to_L1I 0 <--
+MM Other_GETX 6891
+MM Other_GETS 11330
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 17146
+IM Other_GETS 27091
+IM Ack 21872
+IM Data 208
+IM Exclusive_Data 7096
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 614
+SM Other_GETS 586
+SM Ack 301
+SM Data 95
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 287
+OM Other_GETS 330
+OM Ack 427
+OM All_acks 0 <--
+OM All_acks_no_sharers 61
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 925
+ISM All_acks_no_sharers 303
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 33680
+M_W All_acks_no_sharers 11342
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 21296
+MM_W All_acks_no_sharers 7096
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 27323
+IS Other_GETS 44582
+IS Ack 36255
+IS Shared_Ack 289
+IS Data 0 <--
+IS Shared_Data 728
+IS Exclusive_Data 11342
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 1886
+SS Shared_Ack 310
+SS All_acks 728
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 19537
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 19537
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_type_LD: 61.4014%
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_type_ST: 38.5986%
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19537 100%
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19537 average: 1 | standard deviation: 0 | 0 19537 ]
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 3 ---
+ - Event Counts -
+Load 100000
+Ifetch 0
+Store 53655
+L2_Replacement 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+Other_GETX 52432
+Other_GETS 84361
+Ack 116739
+Shared_Ack 560
+Data 309
+Shared_Data 694
+Exclusive_Data 18457
+Writeback_Ack 0
+Writeback_Nack 0
+All_acks 694
+All_acks_no_sharers 18843
+
+ - Transitions -
+I Load 11996
+I Ifetch 0 <--
+I Store 6516
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 1285
+S Ifetch 0 <--
+S Store 677
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 17
+S Other_GETS 21
+
+O Load 658
+O Ifetch 0 <--
+O Store 348
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 2
+O Other_GETS 4
+
+M Load 19730
+M Ifetch 0 <--
+M Store 10706
+M L2_Replacement 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M Other_GETX 246
+M Other_GETS 350
+
+MM Load 66331
+MM Ifetch 0 <--
+MM Store 35408
+MM L2_Replacement 0 <--
+MM L1_to_L2 0 <--
+MM L2_to_L1D 0 <--
+MM L2_to_L1I 0 <--
+MM Other_GETX 6849
+MM Other_GETS 11396
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 17261
+IM Other_GETS 26890
+IM Ack 21925
+IM Data 214
+IM Exclusive_Data 7155
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 582
+SM Other_GETS 577
+SM Ack 266
+SM Data 95
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 271
+OM Other_GETS 336
+OM Ack 539
+OM All_acks 0 <--
+OM All_acks_no_sharers 77
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 952
+ISM All_acks_no_sharers 309
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 33965
+M_W All_acks_no_sharers 11302
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 21641
+MM_W All_acks_no_sharers 7155
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 27204
+IS Other_GETS 44787
+IS Ack 35597
+IS Shared_Ack 269
+IS Data 0 <--
+IS Shared_Data 694
+IS Exclusive_Data 11302
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 1854
+SS Shared_Ack 291
+SS All_acks 694
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 19479
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 19479
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_type_LD: 61.4457%
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_type_ST: 38.5543%
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19479 100%
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19479 average: 1 | standard deviation: 0 | 0 19479 ]
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 4 ---
+ - Event Counts -
+Load 99543
+Ifetch 0
+Store 53625
+L2_Replacement 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+Other_GETX 52463
+Other_GETS 84390
+Ack 116321
+Shared_Ack 618
+Data 248
+Shared_Data 717
+Exclusive_Data 18435
+Writeback_Ack 0
+Writeback_Nack 0
+All_acks 717
+All_acks_no_sharers 18760
+
+ - Transitions -
+I Load 11969
+I Ifetch 0 <--
+I Store 6391
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 1265
+S Ifetch 0 <--
+S Store 704
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 13
+S Other_GETS 21
+
+O Load 817
+O Ifetch 0 <--
+O Store 415
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 0 <--
+O Other_GETS 1
+
+M Load 19857
+M Ifetch 0 <--
+M Store 10633
+M L2_Replacement 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M Other_GETX 202
+M Other_GETS 415
+
+MM Load 65635
+MM Ifetch 0 <--
+MM Store 35482
+MM L2_Replacement 0 <--
+MM L1_to_L2 0 <--
+MM L2_to_L1D 0 <--
+MM L2_to_L1I 0 <--
+MM Other_GETX 6959
+MM Other_GETS 11184
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 17207
+IM Other_GETS 27075
+IM Ack 22197
+IM Data 174
+IM Exclusive_Data 7185
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 630
+SM Other_GETS 554
+SM Ack 242
+SM Data 74
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 338
+OM Other_GETS 419
+OM Ack 539
+OM All_acks 0 <--
+OM All_acks_no_sharers 77
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 750
+ISM All_acks_no_sharers 248
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 34130
+M_W All_acks_no_sharers 11250
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 21409
+MM_W All_acks_no_sharers 7185
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 27114
+IS Other_GETS 44721
+IS Ack 35260
+IS Shared_Ack 308
+IS Data 0 <--
+IS Shared_Data 717
+IS Exclusive_Data 11250
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 1794
+SS Shared_Ack 310
+SS All_acks 717
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 19595
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 19595
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_type_LD: 61.1278%
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_type_ST: 38.8722%
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19595 100%
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19595 average: 1 | standard deviation: 0 | 0 19595 ]
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 5 ---
+ - Event Counts -
+Load 99749
+Ifetch 0
+Store 53938
+L2_Replacement 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+Other_GETX 52357
+Other_GETS 84380
+Ack 117004
+Shared_Ack 626
+Data 310
+Shared_Data 764
+Exclusive_Data 18447
+Writeback_Ack 0
+Writeback_Nack 0
+All_acks 764
+All_acks_no_sharers 18829
+
+ - Transitions -
+I Load 11978
+I Ifetch 0 <--
+I Store 6514
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 1326
+S Ifetch 0 <--
+S Store 742
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 22
+S Other_GETS 12
+
+O Load 678
+O Ifetch 0 <--
+O Store 361
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 6
+O Other_GETS 1
+
+M Load 19860
+M Ifetch 0 <--
+M Store 10632
+M L2_Replacement 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M Other_GETX 214
+M Other_GETS 367
+
+MM Load 65907
+MM Ifetch 0 <--
+MM Store 35689
+MM L2_Replacement 0 <--
+MM L1_to_L2 0 <--
+MM L2_to_L1D 0 <--
+MM L2_to_L1I 0 <--
+MM Other_GETX 6881
+MM Other_GETS 11367
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 17398
+IM Other_GETS 27387
+IM Ack 22561
+IM Data 201
+IM Exclusive_Data 7234
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 633
+SM Other_GETS 629
+SM Ack 331
+SM Data 109
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 289
+OM Other_GETS 335
+OM Ack 504
+OM All_acks 0 <--
+OM All_acks_no_sharers 72
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 910
+ISM All_acks_no_sharers 310
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 33272
+M_W All_acks_no_sharers 11213
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 21462
+MM_W All_acks_no_sharers 7234
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 26914
+IS Other_GETS 44282
+IS Ack 35998
+IS Shared_Ack 321
+IS Data 0 <--
+IS Shared_Data 764
+IS Exclusive_Data 11213
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 1966
+SS Shared_Ack 305
+SS All_acks 764
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 19502
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 19502
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_type_LD: 62.2757%
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_type_ST: 37.7243%
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19502 100%
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19502 average: 1 | standard deviation: 0 | 0 19502 ]
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 6 ---
+ - Event Counts -
+Load 99532
+Ifetch 0
+Store 53708
+L2_Replacement 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+Other_GETX 52616
+Other_GETS 84214
+Ack 116483
+Shared_Ack 595
+Data 275
+Shared_Data 697
+Exclusive_Data 18450
+Writeback_Ack 0
+Writeback_Nack 0
+All_acks 697
+All_acks_no_sharers 18803
+
+ - Transitions -
+I Load 12145
+I Ifetch 0 <--
+I Store 6303
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 1204
+S Ifetch 0 <--
+S Store 680
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 17
+S Other_GETS 20
+
+O Load 724
+O Ifetch 0 <--
+O Store 374
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 3
+O Other_GETS 4
+
+M Load 20018
+M Ifetch 0 <--
+M Store 10841
+M L2_Replacement 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M Other_GETX 228
+M Other_GETS 377
+
+MM Load 65441
+MM Ifetch 0 <--
+MM Store 35510
+MM L2_Replacement 0 <--
+MM L1_to_L2 0 <--
+MM L2_to_L1D 0 <--
+MM L2_to_L1I 0 <--
+MM Other_GETX 6823
+MM Other_GETS 11375
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 17095
+IM Other_GETS 26819
+IM Ack 21955
+IM Data 207
+IM Exclusive_Data 7004
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 612
+SM Other_GETS 558
+SM Ack 193
+SM Data 68
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 296
+OM Other_GETS 354
+OM Ack 546
+OM All_acks 0 <--
+OM All_acks_no_sharers 78
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 839
+ISM All_acks_no_sharers 275
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 34354
+M_W All_acks_no_sharers 11446
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 20687
+MM_W All_acks_no_sharers 7004
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 27542
+IS Other_GETS 44707
+IS Ack 36128
+IS Shared_Ack 291
+IS Data 0 <--
+IS Shared_Data 697
+IS Exclusive_Data 11446
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 1781
+SS Shared_Ack 304
+SS All_acks 697
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 19590
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 19590
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_type_LD: 61.5416%
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_type_ST: 38.4584%
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19590 100%
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19590 average: 1 | standard deviation: 0 | 0 19590 ]
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 7 ---
+ - Event Counts -
+Load 99893
+Ifetch 0
+Store 53982
+L2_Replacement 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+Other_GETX 52440
+Other_GETS 84302
+Ack 117049
+Shared_Ack 560
+Data 284
+Shared_Data 737
+Exclusive_Data 18487
+Writeback_Ack 0
+Writeback_Nack 0
+All_acks 737
+All_acks_no_sharers 18851
+
+ - Transitions -
+I Load 12056
+I Ifetch 0 <--
+I Store 6465
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 1382
+S Ifetch 0 <--
+S Store 714
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 23
+S Other_GETS 19
+
+O Load 645
+O Ifetch 0 <--
+O Store 355
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 0 <--
+O Other_GETS 3
+
+M Load 19774
+M Ifetch 0 <--
+M Store 10769
+M L2_Replacement 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M Other_GETX 194
+M Other_GETS 355
+
+MM Load 66036
+MM Ifetch 0 <--
+MM Store 35679
+MM L2_Replacement 0 <--
+MM L1_to_L2 0 <--
+MM L2_to_L1D 0 <--
+MM L2_to_L1I 0 <--
+MM Other_GETX 7003
+MM Other_GETS 11299
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 0 <--
+IM Other_GETX 17041
+IM Other_GETS 26788
+IM Ack 22004
+IM Data 203
+IM Exclusive_Data 7169
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 633
+SM Other_GETS 620
+SM Ack 237
+SM Data 81
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 275
+OM Other_GETS 349
+OM Ack 560
+OM All_acks 0 <--
+OM All_acks_no_sharers 80
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 883
+ISM All_acks_no_sharers 284
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 0 <--
+M_W Ack 33832
+M_W All_acks_no_sharers 11318
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 0 <--
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 0 <--
+MM_W Ack 21594
+MM_W All_acks_no_sharers 7169
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 0 <--
+IS Other_GETX 27271
+IS Other_GETS 44869
+IS Ack 36049
+IS Shared_Ack 313
+IS Data 0 <--
+IS Shared_Data 737
+IS Exclusive_Data 11318
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 1890
+SS Shared_Ack 247
+SS All_acks 737
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer:
+ memory_total_requests: 2
+ memory_reads: 2
+ memory_writes: 0
+ memory_refreshes: 22
+ memory_total_request_delays: 31
+ memory_delays_per_request: 15.5
+ memory_delays_in_input_queue: 1
+ memory_delays_behind_head_of_bank_queue: 10
+ memory_delays_stalled_at_head_of_bank_queue: 20
+ memory_stalls_for_bank_busy: 20
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 0
+ memory_stalls_for_bus: 0
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 0
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 2262370
+GETS 3582344
+PUT 0
+Unblock 156330
+Writeback_Clean 0
+Writeback_Dirty 0
+Writeback_Exclusive_Clean 0
+Writeback_Exclusive_Dirty 0
+DMA_READ 0
+DMA_WRITE 0
+Memory_Data 2
+Memory_Ack 0
+Ack 0
+Shared_Ack 0
+Shared_Data 0
+Exclusive_Data 0
+All_acks_and_data 0
+All_acks_and_data_no_sharers 0
+
+ - Transitions -
+NO GETX 59974
+NO GETS 96356
+NO PUT 0 <--
+NO DMA_READ 0 <--
+NO DMA_WRITE 0 <--
+
+O GETX 0 <--
+O GETS 0 <--
+O PUT 0 <--
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+
+E GETX 1
+E GETS 1
+E PUT 0 <--
+E DMA_READ 0 <--
+E DMA_WRITE 0 <--
+
+NO_B GETX 2202196
+NO_B GETS 3485775
+NO_B PUT 0 <--
+NO_B Unblock 156330
+NO_B DMA_READ 0 <--
+NO_B DMA_WRITE 0 <--
+
+O_B GETX 0 <--
+O_B GETS 0 <--
+O_B PUT 0 <--
+O_B Unblock 0 <--
+O_B DMA_READ 0 <--
+O_B DMA_WRITE 0 <--
+
+NO_B_W GETX 199
+NO_B_W GETS 212
+NO_B_W PUT 0 <--
+NO_B_W Unblock 0 <--
+NO_B_W DMA_READ 0 <--
+NO_B_W DMA_WRITE 0 <--
+NO_B_W Memory_Data 2
+
+O_B_W GETX 0 <--
+O_B_W GETS 0 <--
+O_B_W PUT 0 <--
+O_B_W Unblock 0 <--
+O_B_W DMA_READ 0 <--
+O_B_W DMA_WRITE 0 <--
+O_B_W Memory_Data 0 <--
+
+NO_W GETX 0 <--
+NO_W GETS 0 <--
+NO_W PUT 0 <--
+NO_W DMA_READ 0 <--
+NO_W DMA_WRITE 0 <--
+NO_W Memory_Data 0 <--
+
+O_W GETX 0 <--
+O_W GETS 0 <--
+O_W PUT 0 <--
+O_W DMA_READ 0 <--
+O_W DMA_WRITE 0 <--
+O_W Memory_Data 0 <--
+
+NO_DW_B_W GETX 0 <--
+NO_DW_B_W GETS 0 <--
+NO_DW_B_W PUT 0 <--
+NO_DW_B_W DMA_READ 0 <--
+NO_DW_B_W DMA_WRITE 0 <--
+NO_DW_B_W Ack 0 <--
+NO_DW_B_W Exclusive_Data 0 <--
+NO_DW_B_W All_acks_and_data_no_sharers 0 <--
+
+NO_DR_B_W GETX 0 <--
+NO_DR_B_W GETS 0 <--
+NO_DR_B_W PUT 0 <--
+NO_DR_B_W DMA_READ 0 <--
+NO_DR_B_W DMA_WRITE 0 <--
+NO_DR_B_W Memory_Data 0 <--
+NO_DR_B_W Ack 0 <--
+NO_DR_B_W Shared_Ack 0 <--
+NO_DR_B_W Shared_Data 0 <--
+NO_DR_B_W Exclusive_Data 0 <--
+
+NO_DR_B_D GETX 0 <--
+NO_DR_B_D GETS 0 <--
+NO_DR_B_D PUT 0 <--
+NO_DR_B_D DMA_READ 0 <--
+NO_DR_B_D DMA_WRITE 0 <--
+NO_DR_B_D Ack 0 <--
+NO_DR_B_D Shared_Ack 0 <--
+NO_DR_B_D Shared_Data 0 <--
+NO_DR_B_D Exclusive_Data 0 <--
+NO_DR_B_D All_acks_and_data 0 <--
+NO_DR_B_D All_acks_and_data_no_sharers 0 <--
+
+NO_DR_B GETX 0 <--
+NO_DR_B GETS 0 <--
+NO_DR_B PUT 0 <--
+NO_DR_B DMA_READ 0 <--
+NO_DR_B DMA_WRITE 0 <--
+NO_DR_B Ack 0 <--
+NO_DR_B Shared_Ack 0 <--
+NO_DR_B Shared_Data 0 <--
+NO_DR_B Exclusive_Data 0 <--
+NO_DR_B All_acks_and_data 0 <--
+NO_DR_B All_acks_and_data_no_sharers 0 <--
+
+NO_DW_W GETX 0 <--
+NO_DW_W GETS 0 <--
+NO_DW_W PUT 0 <--
+NO_DW_W DMA_READ 0 <--
+NO_DW_W DMA_WRITE 0 <--
+NO_DW_W Memory_Ack 0 <--
+
+O_DR_B_W GETX 0 <--
+O_DR_B_W GETS 0 <--
+O_DR_B_W PUT 0 <--
+O_DR_B_W DMA_READ 0 <--
+O_DR_B_W DMA_WRITE 0 <--
+O_DR_B_W Memory_Data 0 <--
+
+O_DR_B GETX 0 <--
+O_DR_B GETS 0 <--
+O_DR_B PUT 0 <--
+O_DR_B DMA_READ 0 <--
+O_DR_B DMA_WRITE 0 <--
+O_DR_B Ack 0 <--
+O_DR_B All_acks_and_data_no_sharers 0 <--
+
+WB GETX 0 <--
+WB GETS 0 <--
+WB PUT 0 <--
+WB Unblock 0 <--
+WB Writeback_Clean 0 <--
+WB Writeback_Dirty 0 <--
+WB Writeback_Exclusive_Clean 0 <--
+WB Writeback_Exclusive_Dirty 0 <--
+WB DMA_READ 0 <--
+WB DMA_WRITE 0 <--
+
+WB_O_W GETX 0 <--
+WB_O_W GETS 0 <--
+WB_O_W PUT 0 <--
+WB_O_W DMA_READ 0 <--
+WB_O_W DMA_WRITE 0 <--
+WB_O_W Memory_Ack 0 <--
+
+WB_E_W GETX 0 <--
+WB_E_W GETS 0 <--
+WB_E_W PUT 0 <--
+WB_E_W DMA_READ 0 <--
+WB_E_W DMA_WRITE 0 <--
+WB_E_W Memory_Ack 0 <--
+
--- /dev/null
+system.cpu7: completed 10000 read accesses @425814
+system.cpu1: completed 10000 read accesses @431765
+system.cpu5: completed 10000 read accesses @437116
+system.cpu3: completed 10000 read accesses @437535
+system.cpu6: completed 10000 read accesses @438270
+system.cpu4: completed 10000 read accesses @440833
+system.cpu2: completed 10000 read accesses @444354
+system.cpu0: completed 10000 read accesses @448450
+system.cpu7: completed 20000 read accesses @862753
+system.cpu1: completed 20000 read accesses @872204
+system.cpu2: completed 20000 read accesses @872666
+system.cpu6: completed 20000 read accesses @874110
+system.cpu5: completed 20000 read accesses @878379
+system.cpu0: completed 20000 read accesses @879685
+system.cpu3: completed 20000 read accesses @882760
+system.cpu4: completed 20000 read accesses @884840
+system.cpu7: completed 30000 read accesses @1288068
+system.cpu3: completed 30000 read accesses @1303299
+system.cpu5: completed 30000 read accesses @1305762
+system.cpu6: completed 30000 read accesses @1313571
+system.cpu0: completed 30000 read accesses @1317286
+system.cpu2: completed 30000 read accesses @1317386
+system.cpu1: completed 30000 read accesses @1325478
+system.cpu4: completed 30000 read accesses @1333221
+system.cpu7: completed 40000 read accesses @1730996
+system.cpu5: completed 40000 read accesses @1732724
+system.cpu1: completed 40000 read accesses @1747591
+system.cpu6: completed 40000 read accesses @1753270
+system.cpu0: completed 40000 read accesses @1754662
+system.cpu3: completed 40000 read accesses @1760631
+system.cpu4: completed 40000 read accesses @1765520
+system.cpu2: completed 40000 read accesses @1771010
+system.cpu7: completed 50000 read accesses @2170118
+system.cpu5: completed 50000 read accesses @2171036
+system.cpu1: completed 50000 read accesses @2185469
+system.cpu2: completed 50000 read accesses @2190117
+system.cpu6: completed 50000 read accesses @2190751
+system.cpu0: completed 50000 read accesses @2197570
+system.cpu3: completed 50000 read accesses @2201959
+system.cpu4: completed 50000 read accesses @2222797
+system.cpu7: completed 60000 read accesses @2610778
+system.cpu2: completed 60000 read accesses @2614670
+system.cpu1: completed 60000 read accesses @2623246
+system.cpu5: completed 60000 read accesses @2629220
+system.cpu3: completed 60000 read accesses @2631164
+system.cpu6: completed 60000 read accesses @2632436
+system.cpu0: completed 60000 read accesses @2635088
+system.cpu4: completed 60000 read accesses @2652031
+system.cpu2: completed 70000 read accesses @3051672
+system.cpu7: completed 70000 read accesses @3059272
+system.cpu1: completed 70000 read accesses @3063932
+system.cpu0: completed 70000 read accesses @3068179
+system.cpu6: completed 70000 read accesses @3068899
+system.cpu5: completed 70000 read accesses @3070562
+system.cpu3: completed 70000 read accesses @3074746
+system.cpu4: completed 70000 read accesses @3079887
+system.cpu7: completed 80000 read accesses @3496808
+system.cpu3: completed 80000 read accesses @3497818
+system.cpu1: completed 80000 read accesses @3502491
+system.cpu2: completed 80000 read accesses @3504549
+system.cpu5: completed 80000 read accesses @3505508
+system.cpu6: completed 80000 read accesses @3505668
+system.cpu4: completed 80000 read accesses @3508575
+system.cpu0: completed 80000 read accesses @3514003
+system.cpu7: completed 90000 read accesses @3930059
+system.cpu3: completed 90000 read accesses @3930742
+system.cpu1: completed 90000 read accesses @3940704
+system.cpu4: completed 90000 read accesses @3941146
+system.cpu0: completed 90000 read accesses @3943666
+system.cpu2: completed 90000 read accesses @3945855
+system.cpu6: completed 90000 read accesses @3950281
+system.cpu5: completed 90000 read accesses @3953787
+system.cpu3: completed 100000 read accesses @4369301
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 28 2010 11:30:01
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 11:55:12
+M5 executing on svvint06
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 4369301 because maximum number of loads reached
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 342412 # Number of bytes of host memory used
+host_seconds 54.05 # Real time elapsed on the host
+host_tick_rate 80836 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.004369 # Number of seconds simulated
+sim_ticks 4369301 # Number of ticks simulated
+system.cpu0.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 99702 # number of read accesses completed
+system.cpu0.num_writes 54194 # number of write accesses completed
+system.cpu1.num_copies 0 # number of copy accesses completed
+system.cpu1.num_reads 99603 # number of read accesses completed
+system.cpu1.num_writes 53835 # number of write accesses completed
+system.cpu2.num_copies 0 # number of copy accesses completed
+system.cpu2.num_reads 99782 # number of read accesses completed
+system.cpu2.num_writes 53417 # number of write accesses completed
+system.cpu3.num_copies 0 # number of copy accesses completed
+system.cpu3.num_reads 100000 # number of read accesses completed
+system.cpu3.num_writes 53655 # number of write accesses completed
+system.cpu4.num_copies 0 # number of copy accesses completed
+system.cpu4.num_reads 99541 # number of read accesses completed
+system.cpu4.num_writes 53625 # number of write accesses completed
+system.cpu5.num_copies 0 # number of copy accesses completed
+system.cpu5.num_reads 99748 # number of read accesses completed
+system.cpu5.num_writes 53937 # number of write accesses completed
+system.cpu6.num_copies 0 # number of copy accesses completed
+system.cpu6.num_reads 99530 # number of read accesses completed
+system.cpu6.num_writes 53708 # number of write accesses completed
+system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu7.num_reads 99892 # number of read accesses completed
+system.cpu7.num_writes 53981 # number of write accesses completed
+
+---------- End Simulation Statistics ----------
[system]
type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem membus physmem
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
mem_mode=timing
physmem=system.physmem
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
-percent_functional=50
+percent_functional=0
percent_reads=65
percent_source_unaligned=50
-percent_uncacheable=10
+percent_uncacheable=0
progress_interval=10000
trace_addr=0
functional=system.funcmem.port[0]
-test=system.membus.port[0]
+test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
[system.cpu1]
type=MemTest
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
-percent_functional=50
+percent_functional=0
percent_reads=65
percent_source_unaligned=50
-percent_uncacheable=10
+percent_uncacheable=0
progress_interval=10000
trace_addr=0
functional=system.funcmem.port[1]
-test=system.membus.port[1]
+test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
[system.cpu2]
type=MemTest
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
-percent_functional=50
+percent_functional=0
percent_reads=65
percent_source_unaligned=50
-percent_uncacheable=10
+percent_uncacheable=0
progress_interval=10000
trace_addr=0
functional=system.funcmem.port[2]
-test=system.membus.port[2]
+test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
[system.cpu3]
type=MemTest
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
-percent_functional=50
+percent_functional=0
percent_reads=65
percent_source_unaligned=50
-percent_uncacheable=10
+percent_uncacheable=0
progress_interval=10000
trace_addr=0
functional=system.funcmem.port[3]
-test=system.membus.port[3]
+test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
[system.cpu4]
type=MemTest
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
-percent_functional=50
+percent_functional=0
percent_reads=65
percent_source_unaligned=50
-percent_uncacheable=10
+percent_uncacheable=0
progress_interval=10000
trace_addr=0
functional=system.funcmem.port[4]
-test=system.membus.port[4]
+test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
[system.cpu5]
type=MemTest
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
-percent_functional=50
+percent_functional=0
percent_reads=65
percent_source_unaligned=50
-percent_uncacheable=10
+percent_uncacheable=0
progress_interval=10000
trace_addr=0
functional=system.funcmem.port[5]
-test=system.membus.port[5]
+test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
[system.cpu6]
type=MemTest
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
-percent_functional=50
+percent_functional=0
percent_reads=65
percent_source_unaligned=50
-percent_uncacheable=10
+percent_uncacheable=0
progress_interval=10000
trace_addr=0
functional=system.funcmem.port[6]
-test=system.membus.port[6]
+test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
[system.cpu7]
type=MemTest
max_loads=100000
memory_size=65536
percent_dest_unaligned=50
-percent_functional=50
+percent_functional=0
percent_reads=65
percent_source_unaligned=50
-percent_uncacheable=10
+percent_uncacheable=0
progress_interval=10000
trace_addr=0
functional=system.funcmem.port[7]
-test=system.membus.port[7]
+test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
[system.funcmem]
type=PhysicalMemory
file=
-latency=30000
+latency=30
latency_var=0
null=false
range=0:134217727
zero=false
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=2
-header_cycles=1
-responder_set=false
-width=16
-port=system.cpu0.test system.cpu1.test system.cpu2.test system.cpu3.test system.cpu4.test system.cpu5.test system.cpu6.test system.cpu7.test system.physmem.port[0]
-
[system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
+type=PhysicalMemory
file=
-latency=30000
+latency=30
latency_var=0
null=false
-num_cpus=8
-num_dmas=1
-phase=0
-ports_per_core=2
-range=0:1073741823
-stats_file=ruby.stats
+range=0:134217727
zero=false
-port=system.membus.port[8]
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8
+num_int_nodes=10
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
+transitions_per_cycle=32
+version=1
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer
+transitions_per_cycle=32
+version=2
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[2]
+port=system.cpu2.test
+
+[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links3]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links3.ext_node
+int_node=3
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links3.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer
+transitions_per_cycle=32
+version=3
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links4]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links4.ext_node
+int_node=4
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links4.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer
+transitions_per_cycle=32
+version=4
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links5]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links5.ext_node
+int_node=5
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links5.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer
+transitions_per_cycle=32
+version=5
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links6]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links6.ext_node
+int_node=6
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links6.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
+transitions_per_cycle=32
+version=6
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links7]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links7.ext_node
+int_node=7
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links7.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
+transitions_per_cycle=32
+version=7
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links8]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links8.ext_node
+int_node=8
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links8.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links8.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links8.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links8.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links8.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=3
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=4
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=5
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=6
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=7
+node_b=9
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=8
+node_b=9
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
RubySystem config:
random_seed: 1234
randomization: 0
- tech_nm: 45
- freq_mhz: 3000
+ cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
- memory_size_bytes: 1073741824
- memory_size_bits: 30
-DMA_Controller config: DMAController_0
- version: 0
- buffer_size: 32
- dma_sequencer: DMASequencer_0
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 14
- response_latency: 14
- transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
- version: 0
- buffer_size: 32
- directory: DirectoryMemory_0
- directory_latency: 6
- memory_control: MemoryControl_0
- number_of_TBEs: 256
- recycle_latency: 10
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
- version: 0
- buffer_size: 32
- dcache: l1d_0
- icache: l1i_0
- l2_select_low_bit: 6
- l2_select_num_bits: 1
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 2
- sequencer: Sequencer_0
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_1
- version: 1
- buffer_size: 32
- dcache: l1d_1
- icache: l1i_1
- l2_select_low_bit: 6
- l2_select_num_bits: 1
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 2
- sequencer: Sequencer_1
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_2
- version: 2
- buffer_size: 32
- dcache: l1d_2
- icache: l1i_2
- l2_select_low_bit: 6
- l2_select_num_bits: 1
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 2
- sequencer: Sequencer_2
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_3
- version: 3
- buffer_size: 32
- dcache: l1d_3
- icache: l1i_3
- l2_select_low_bit: 6
- l2_select_num_bits: 1
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 2
- sequencer: Sequencer_3
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_4
- version: 4
- buffer_size: 32
- dcache: l1d_4
- icache: l1i_4
- l2_select_low_bit: 6
- l2_select_num_bits: 1
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 2
- sequencer: Sequencer_4
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_5
- version: 5
- buffer_size: 32
- dcache: l1d_5
- icache: l1i_5
- l2_select_low_bit: 6
- l2_select_num_bits: 1
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 2
- sequencer: Sequencer_5
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_6
- version: 6
- buffer_size: 32
- dcache: l1d_6
- icache: l1i_6
- l2_select_low_bit: 6
- l2_select_num_bits: 1
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 2
- sequencer: Sequencer_6
- transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_7
- version: 7
- buffer_size: 32
- dcache: l1d_7
- icache: l1i_7
- l2_select_low_bit: 6
- l2_select_num_bits: 1
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 2
- sequencer: Sequencer_7
- transitions_per_cycle: 32
-L2Cache_Controller config: L2CacheController_0
- version: 0
- buffer_size: 32
- cache: l2u_0
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 14
- response_latency: 14
- transitions_per_cycle: 32
-L2Cache_Controller config: L2CacheController_1
- version: 1
- buffer_size: 32
- cache: l2u_1
- number_of_TBEs: 256
- recycle_latency: 10
- request_latency: 14
- response_latency: 14
- transitions_per_cycle: 32
-Cache config: l1d_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 4
- num_cache_sets: 16
- cache_set_size_bytes: 1024
- cache_set_size_Kbytes: 1
- cache_set_size_Mbytes: 0.000976562
- cache_size_bytes: 8192
- cache_size_Kbytes: 8
- cache_size_Mbytes: 0.0078125
-Cache config: l1d_1
- controller: L1CacheController_1
- cache_associativity: 8
- num_cache_sets_bits: 4
- num_cache_sets: 16
- cache_set_size_bytes: 1024
- cache_set_size_Kbytes: 1
- cache_set_size_Mbytes: 0.000976562
- cache_size_bytes: 8192
- cache_size_Kbytes: 8
- cache_size_Mbytes: 0.0078125
-Cache config: l1d_2
- controller: L1CacheController_2
- cache_associativity: 8
- num_cache_sets_bits: 4
- num_cache_sets: 16
- cache_set_size_bytes: 1024
- cache_set_size_Kbytes: 1
- cache_set_size_Mbytes: 0.000976562
- cache_size_bytes: 8192
- cache_size_Kbytes: 8
- cache_size_Mbytes: 0.0078125
-Cache config: l1d_3
- controller: L1CacheController_3
- cache_associativity: 8
- num_cache_sets_bits: 4
- num_cache_sets: 16
- cache_set_size_bytes: 1024
- cache_set_size_Kbytes: 1
- cache_set_size_Mbytes: 0.000976562
- cache_size_bytes: 8192
- cache_size_Kbytes: 8
- cache_size_Mbytes: 0.0078125
-Cache config: l1d_4
- controller: L1CacheController_4
- cache_associativity: 8
- num_cache_sets_bits: 4
- num_cache_sets: 16
- cache_set_size_bytes: 1024
- cache_set_size_Kbytes: 1
- cache_set_size_Mbytes: 0.000976562
- cache_size_bytes: 8192
- cache_size_Kbytes: 8
- cache_size_Mbytes: 0.0078125
-Cache config: l1d_5
- controller: L1CacheController_5
- cache_associativity: 8
- num_cache_sets_bits: 4
- num_cache_sets: 16
- cache_set_size_bytes: 1024
- cache_set_size_Kbytes: 1
- cache_set_size_Mbytes: 0.000976562
- cache_size_bytes: 8192
- cache_size_Kbytes: 8
- cache_size_Mbytes: 0.0078125
-Cache config: l1d_6
- controller: L1CacheController_6
- cache_associativity: 8
- num_cache_sets_bits: 4
- num_cache_sets: 16
- cache_set_size_bytes: 1024
- cache_set_size_Kbytes: 1
- cache_set_size_Mbytes: 0.000976562
- cache_size_bytes: 8192
- cache_size_Kbytes: 8
- cache_size_Mbytes: 0.0078125
-Cache config: l1d_7
- controller: L1CacheController_7
- cache_associativity: 8
- num_cache_sets_bits: 4
- num_cache_sets: 16
- cache_set_size_bytes: 1024
- cache_set_size_Kbytes: 1
- cache_set_size_Mbytes: 0.000976562
- cache_size_bytes: 8192
- cache_size_Kbytes: 8
- cache_size_Mbytes: 0.0078125
-Cache config: l1i_0
- controller: L1CacheController_0
- cache_associativity: 8
- num_cache_sets_bits: 7
- num_cache_sets: 128
- cache_set_size_bytes: 8192
- cache_set_size_Kbytes: 8
- cache_set_size_Mbytes: 0.0078125
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-Cache config: l1i_1
- controller: L1CacheController_1
- cache_associativity: 8
- num_cache_sets_bits: 7
- num_cache_sets: 128
- cache_set_size_bytes: 8192
- cache_set_size_Kbytes: 8
- cache_set_size_Mbytes: 0.0078125
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-Cache config: l1i_2
- controller: L1CacheController_2
- cache_associativity: 8
- num_cache_sets_bits: 7
- num_cache_sets: 128
- cache_set_size_bytes: 8192
- cache_set_size_Kbytes: 8
- cache_set_size_Mbytes: 0.0078125
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-Cache config: l1i_3
- controller: L1CacheController_3
- cache_associativity: 8
- num_cache_sets_bits: 7
- num_cache_sets: 128
- cache_set_size_bytes: 8192
- cache_set_size_Kbytes: 8
- cache_set_size_Mbytes: 0.0078125
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-Cache config: l1i_4
- controller: L1CacheController_4
- cache_associativity: 8
- num_cache_sets_bits: 7
- num_cache_sets: 128
- cache_set_size_bytes: 8192
- cache_set_size_Kbytes: 8
- cache_set_size_Mbytes: 0.0078125
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-Cache config: l1i_5
- controller: L1CacheController_5
- cache_associativity: 8
- num_cache_sets_bits: 7
- num_cache_sets: 128
- cache_set_size_bytes: 8192
- cache_set_size_Kbytes: 8
- cache_set_size_Mbytes: 0.0078125
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-Cache config: l1i_6
- controller: L1CacheController_6
- cache_associativity: 8
- num_cache_sets_bits: 7
- num_cache_sets: 128
- cache_set_size_bytes: 8192
- cache_set_size_Kbytes: 8
- cache_set_size_Mbytes: 0.0078125
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-Cache config: l1i_7
- controller: L1CacheController_7
- cache_associativity: 8
- num_cache_sets_bits: 7
- num_cache_sets: 128
- cache_set_size_bytes: 8192
- cache_set_size_Kbytes: 8
- cache_set_size_Mbytes: 0.0078125
- cache_size_bytes: 65536
- cache_size_Kbytes: 64
- cache_size_Mbytes: 0.0625
-Cache config: l2u_0
- controller: L2CacheController_0
- cache_associativity: 16
- num_cache_sets_bits: 12
- num_cache_sets: 4096
- cache_set_size_bytes: 262144
- cache_set_size_Kbytes: 256
- cache_set_size_Mbytes: 0.25
- cache_size_bytes: 4194304
- cache_size_Kbytes: 4096
- cache_size_Mbytes: 4
-Cache config: l2u_1
- controller: L2CacheController_1
- cache_associativity: 16
- num_cache_sets_bits: 12
- num_cache_sets: 4096
- cache_set_size_bytes: 262144
- cache_set_size_Kbytes: 256
- cache_set_size_Mbytes: 0.25
- cache_size_bytes: 4194304
- cache_size_Kbytes: 4096
- cache_size_Mbytes: 4
-DirectoryMemory Global Config:
- number of directory memories: 1
- total memory size bytes: 1073741824
- total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
- controller: DirectoryController_0
- version: 0
- memory_bits: 30
- memory_size_bytes: 1073741824
- memory_size_Kbytes: 1.04858e+06
- memory_size_Mbytes: 1024
- memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
- controller: L1CacheController_0
- version: 0
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-Seqeuncer config: Sequencer_1
- controller: L1CacheController_1
- version: 1
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-Seqeuncer config: Sequencer_2
- controller: L1CacheController_2
- version: 2
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-Seqeuncer config: Sequencer_3
- controller: L1CacheController_3
- version: 3
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-Seqeuncer config: Sequencer_4
- controller: L1CacheController_4
- version: 4
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-Seqeuncer config: Sequencer_5
- controller: L1CacheController_5
- version: 5
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-Seqeuncer config: Sequencer_6
- controller: L1CacheController_6
- version: 6
- max_outstanding_requests: 16
- deadlock_threshold: 500000
-Seqeuncer config: Sequencer_7
- controller: L1CacheController_7
- version: 7
- max_outstanding_requests: 16
- deadlock_threshold: 500000
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: theTopology
+topology:
-virtual_net_0: active, unordered
-virtual_net_1: active, unordered
-virtual_net_2: active, unordered
+virtual_net_0: active, ordered
+virtual_net_1: active, ordered
+virtual_net_2: active, ordered
virtual_net_3: inactive
-virtual_net_4: inactive
+virtual_net_4: active, ordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
Profiler Configuration
================ End RubySystem Configuration Print ================
-Real time: Jan/19/2010 17:15:39
+Real time: Jan/28/2010 11:10:42
Profiler Stats
--------------
-Elapsed_time_in_seconds: 219
-Elapsed_time_in_minutes: 3.65
-Elapsed_time_in_hours: 0.0608333
-Elapsed_time_in_days: 0.00253472
+Elapsed_time_in_seconds: 86
+Elapsed_time_in_minutes: 1.43333
+Elapsed_time_in_hours: 0.0238889
+Elapsed_time_in_days: 0.00099537
-Virtual_time_in_seconds: 219.56
-Virtual_time_in_minutes: 3.65933
-Virtual_time_in_hours: 0.0609889
-Virtual_time_in_days: 0.0025412
+Virtual_time_in_seconds: 83.22
+Virtual_time_in_minutes: 1.387
+Virtual_time_in_hours: 0.0231167
+Virtual_time_in_days: 0.000963194
-Ruby_current_time: 4504973
-Ruby_start_time: 1
-Ruby_cycles: 4504972
+Ruby_current_time: 11043028
+Ruby_start_time: 0
+Ruby_cycles: 11043028
-mbytes_resident: 157.109
-mbytes_total: 1381.15
-resident_ratio: 0.113758
+mbytes_resident: 31.1562
+mbytes_total: 31.1602
+resident_ratio: 1
Total_misses: 0
total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
-ruby_cycles_executed: 36039784 [ 4504973 4504973 4504973 4504973 4504973 4504973 4504973 4504973 ]
+ruby_cycles_executed: 88344232 [ 11043029 11043029 11043029 11043029 11043029 11043029 11043029 11043029 ]
transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
-Memory control MemoryControl_0:
- memory_total_requests: 3005
- memory_reads: 3005
- memory_writes: 0
- memory_refreshes: 249
- memory_total_request_delays: 44377
- memory_delays_per_request: 14.7677
- memory_delays_in_input_queue: 455
- memory_delays_behind_head_of_bank_queue: 5602
- memory_delays_stalled_at_head_of_bank_queue: 38320
- memory_stalls_for_bank_busy: 5925
- memory_stalls_for_random_busy: 3962
- memory_stalls_for_anti_starvation: 2593
- memory_stalls_for_arbitration: 7799
- memory_stalls_for_bus: 11753
- memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 0
- memory_stalls_for_read_read_turnaround: 6288
- accesses_per_bank: 94 95 94 95 95 94 91 93 92 95 94 95 96 93 95 93 92 93 92 93 93 93 94 95 93 96 94 95 94 93 96 95
-
Busy Controller Counts:
-L2Cache-0:0 L2Cache-1:0
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
-DMA-0:0
Directory-0:0
+
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 747279 average: 5.5893 | standard deviation: 1.87929 | 0 2677 17977 57793 118759 170403 177953 124824 52770 12769 2104 651 477 583 776 1441 5322 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1226994 average: 1.93527 | standard deviation: 0.246042 | 0 79418 1147576 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 8 max: 1069 count: 747275 average: 29.6123 | standard deviation: 22.3575 | 27052 0 0 716077 295 143 361 256 13 6 4 10 2 11 5 5 1 2 3 4 1 2 3 164 216 145 112 107 103 92 66 72 72 86 76 73 71 65 82 55 47 55 79 45 56 40 35 49 50 45 32 41 33 41 44 27 44 37 34 38 33 24 33 34 28 21 23 24 18 18 12 16 22 20 9 9 7 12 11 8 6 8 6 9 6 1 4 1 7 3 2 3 3 2 8 1 7 2 2 2 1 2 1 2 1 0 1 2 5 2 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 8 max: 1069 count: 485700 average: 29.3069 | standard deviation: 22.5252 | 17456 0 0 465505 295 1 246 160 7 6 0 8 1 7 5 0 0 1 2 4 0 1 2 111 145 94 63 67 70 67 45 42 41 53 45 49 47 45 60 38 32 35 49 26 44 23 22 40 37 29 25 20 24 31 29 16 28 26 21 33 18 18 20 19 25 15 13 15 12 13 8 12 17 12 7 4 3 8 5 8 4 4 4 9 2 1 4 1 4 2 1 2 2 0 7 1 5 1 2 0 0 0 1 1 1 0 1 1 4 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 8 max: 1059 count: 261575 average: 30.1795 | standard deviation: 22.0315 | 9596 0 0 250572 0 142 115 96 6 0 4 2 1 4 0 5 1 1 1 0 1 1 1 53 71 51 49 40 33 25 21 30 31 33 31 24 24 20 22 17 15 20 30 19 12 17 13 9 13 16 7 21 9 10 15 11 16 11 13 5 15 6 13 15 3 6 10 9 6 5 4 4 5 8 2 5 4 4 6 0 2 4 2 0 4 0 0 0 3 1 1 1 1 2 1 0 2 1 0 2 1 2 0 1 0 0 0 1 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 4 max: 548 count: 1226980 average: 141.939 | standard deviation: 1.7969 | 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 296 4661 76324 1145657 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 4 max: 530 count: 797700 average: 141.938 | standard deviation: 1.74299 | 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 188 2995 49656 744835 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 4 max: 548 count: 429280 average: 141.94 | standard deviation: 1.89302 | 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 108 1666 26668 400822 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_delay_cycles: [binsize: 4 max: 151 count: 2453934 average: 47.4682 | standard deviation: 47.4791 | 1226968 0 1 0 0 0 0 1 0 0 0 1 1 0 0 2 0 0 0 7 141 2386 38040 613044 573338 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
+Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2453934 average: 47.4682 | standard deviation: 47.4791 | 1226968 0 1 0 0 0 0 1 0 0 0 1 1 0 0 2 0 0 0 7 141 2386 38040 613044 573338 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1226967 average: 0 | standard deviation: 0 | 1226967 ]
+ virtual_network_2_delay_cycles: [binsize: 4 max: 151 count: 1226967 average: 94.9364 | standard deviation: 1.44009 | 1 0 1 0 0 0 0 1 0 0 0 1 1 0 0 2 0 0 0 7 141 2386 38040 613044 573338 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
-user_time: 219
-system_time: 0
-page_reclaims: 41446
-page_faults: 0
+user_time: 82
+system_time: 1
+page_reclaims: 6850
+page_faults: 1924
swaps: 0
block_inputs: 0
block_outputs: 0
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 5.79466
- links_utilized_percent_switch_0_link_0: 1.99838 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 9.59095 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_0_link_0_Response_Data: 3005 216360 [ 0 0 3005 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 717218 51639696 [ 0 0 717218 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Writeback_Control: 720095 5760760 [ 720095 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Request_Control: 720227 5761816 [ 720227 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Data: 720094 51846768 [ 0 0 720094 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Control: 720099 5760792 [ 720099 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Unblock_Control: 720222 5761776 [ 0 0 720222 0 0 ] base_latency: 1
+links_utilized_percent_switch_0: 0.434014
+ links_utilized_percent_switch_0_link_0: 0.173606 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.694421 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 153371 1226968 [ 0 0 153371 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 153372 1226976 [ 153372 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0
- links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.434016
+ links_utilized_percent_switch_1_link_0: 0.173606 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.694425 bw: 160000 base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
- links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.434016
+ links_utilized_percent_switch_2_link_0: 0.173606 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.694425 bw: 160000 base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 2
switch_3_outlinks: 2
-links_utilized_percent_switch_3: 0
- links_utilized_percent_switch_3_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
+links_utilized_percent_switch_3: 0.434016
+ links_utilized_percent_switch_3_link_0: 0.173606 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.694425 bw: 160000 base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_4_inlinks: 2
switch_4_outlinks: 2
-links_utilized_percent_switch_4: 0
- links_utilized_percent_switch_4_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_4_link_1: 0 bw: 160000 base_latency: 1
+links_utilized_percent_switch_4: 0.434016
+ links_utilized_percent_switch_4_link_0: 0.173606 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_4_link_1: 0.694425 bw: 160000 base_latency: 1
+ outgoing_messages_switch_4_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_5_inlinks: 2
switch_5_outlinks: 2
-links_utilized_percent_switch_5: 0
- links_utilized_percent_switch_5_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_5_link_1: 0 bw: 160000 base_latency: 1
+links_utilized_percent_switch_5: 0.434014
+ links_utilized_percent_switch_5_link_0: 0.173606 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_5_link_1: 0.694421 bw: 160000 base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Control: 153372 1226976 [ 153372 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_6_inlinks: 2
switch_6_outlinks: 2
-links_utilized_percent_switch_6: 0
- links_utilized_percent_switch_6_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_6_link_1: 0 bw: 160000 base_latency: 1
+links_utilized_percent_switch_6: 0.434016
+ links_utilized_percent_switch_6_link_0: 0.173606 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_6_link_1: 0.694425 bw: 160000 base_latency: 1
+ outgoing_messages_switch_6_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_7_inlinks: 2
switch_7_outlinks: 2
-links_utilized_percent_switch_7: 0
- links_utilized_percent_switch_7_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_7_link_1: 0 bw: 160000 base_latency: 1
+links_utilized_percent_switch_7: 0.434013
+ links_utilized_percent_switch_7_link_0: 0.173605 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_7_link_1: 0.694421 bw: 160000 base_latency: 1
+ outgoing_messages_switch_7_link_0_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Writeback_Control: 153371 1226968 [ 0 0 153371 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Control: 153372 1226976 [ 153372 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_1_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_8_inlinks: 2
switch_8_outlinks: 2
-links_utilized_percent_switch_8: 2.59681
- links_utilized_percent_switch_8_link_0: 1.20053 bw: 640000 base_latency: 1
- links_utilized_percent_switch_8_link_1: 3.99309 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_8_link_0_Request_Control: 359480 2875840 [ 359480 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_8_link_0_Response_Data: 1508 108576 [ 0 0 1508 0 0 ] base_latency: 1
- outgoing_messages_switch_8_link_0_Writeback_Data: 359415 25877880 [ 0 0 359415 0 0 ] base_latency: 1
- outgoing_messages_switch_8_link_0_Writeback_Control: 359416 2875328 [ 359416 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_8_link_0_Unblock_Control: 359479 2875832 [ 0 0 359479 0 0 ] base_latency: 1
- outgoing_messages_switch_8_link_1_Request_Control: 1508 12064 [ 0 1508 0 0 0 ] base_latency: 1
- outgoing_messages_switch_8_link_1_Response_Data: 1508 108576 [ 0 0 1508 0 0 ] base_latency: 1
- outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 357972 25773984 [ 0 0 357972 0 0 ] base_latency: 1
- outgoing_messages_switch_8_link_1_Writeback_Control: 359416 2875328 [ 359416 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_8_link_1_Unblock_Control: 1508 12064 [ 0 0 1508 0 0 ] base_latency: 1
-
-switch_9_inlinks: 2
-switch_9_outlinks: 2
-links_utilized_percent_switch_9: 2.6059
- links_utilized_percent_switch_9_link_0: 1.20471 bw: 640000 base_latency: 1
- links_utilized_percent_switch_9_link_1: 4.00709 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_9_link_0_Request_Control: 360746 2885968 [ 360746 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_9_link_0_Response_Data: 1497 107784 [ 0 0 1497 0 0 ] base_latency: 1
- outgoing_messages_switch_9_link_0_Writeback_Data: 360679 25968888 [ 0 0 360679 0 0 ] base_latency: 1
- outgoing_messages_switch_9_link_0_Writeback_Control: 360682 2885456 [ 360682 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_9_link_0_Unblock_Control: 360743 2885944 [ 0 0 360743 0 0 ] base_latency: 1
- outgoing_messages_switch_9_link_1_Request_Control: 1497 11976 [ 0 1497 0 0 0 ] base_latency: 1
- outgoing_messages_switch_9_link_1_Response_Data: 1497 107784 [ 0 0 1497 0 0 ] base_latency: 1
- outgoing_messages_switch_9_link_1_ResponseL2hit_Data: 359247 25865784 [ 0 0 359247 0 0 ] base_latency: 1
- outgoing_messages_switch_9_link_1_Writeback_Control: 360680 2885440 [ 360680 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_9_link_1_Unblock_Control: 1497 11976 [ 0 0 1497 0 0 ] base_latency: 1
-
-switch_10_inlinks: 2
-switch_10_outlinks: 2
-links_utilized_percent_switch_10: 0.0158422
- links_utilized_percent_switch_10_link_0: 0.0016676 bw: 640000 base_latency: 1
- links_utilized_percent_switch_10_link_1: 0.0300168 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_10_link_0_Request_Control: 3005 24040 [ 0 3005 0 0 0 ] base_latency: 1
- outgoing_messages_switch_10_link_0_Unblock_Control: 3005 24040 [ 0 0 3005 0 0 ] base_latency: 1
- outgoing_messages_switch_10_link_1_Response_Data: 3005 216360 [ 0 0 3005 0 0 ] base_latency: 1
-
-switch_11_inlinks: 2
-switch_11_outlinks: 2
-links_utilized_percent_switch_11: 0
- links_utilized_percent_switch_11_link_0: 0 bw: 640000 base_latency: 1
- links_utilized_percent_switch_11_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_12_inlinks: 12
-switch_12_outlinks: 12
-links_utilized_percent_switch_12: 1.46843
- links_utilized_percent_switch_12_link_0: 7.99351 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_1: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_2: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_3: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_4: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_5: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_6: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_7: 0 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_8: 4.80212 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_9: 4.81885 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_10: 0.00667041 bw: 160000 base_latency: 1
- links_utilized_percent_switch_12_link_11: 0 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_12_link_0_Response_Data: 3005 216360 [ 0 0 3005 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_0_ResponseL2hit_Data: 717219 51639768 [ 0 0 717219 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_0_Writeback_Control: 720096 5760768 [ 720096 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_8_Request_Control: 359480 2875840 [ 359480 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_8_Response_Data: 1508 108576 [ 0 0 1508 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_8_Writeback_Data: 359415 25877880 [ 0 0 359415 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_8_Writeback_Control: 359416 2875328 [ 359416 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_8_Unblock_Control: 359479 2875832 [ 0 0 359479 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_9_Request_Control: 360746 2885968 [ 360746 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_9_Response_Data: 1497 107784 [ 0 0 1497 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_9_Writeback_Data: 360679 25968888 [ 0 0 360679 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_9_Writeback_Control: 360682 2885456 [ 360682 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_9_Unblock_Control: 360743 2885944 [ 0 0 360743 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_10_Request_Control: 3005 24040 [ 0 3005 0 0 0 ] base_latency: 1
- outgoing_messages_switch_12_link_10_Unblock_Control: 3005 24040 [ 0 0 3005 0 0 ] base_latency: 1
-
-Sequencer: Sequencer_0
- store_waiting_on_load_cycles: 281
- store_waiting_on_store_cycles: 133
- load_waiting_on_load_cycles: 459
- load_waiting_on_store_cycles: 265
-Sequencer: Sequencer_1
- store_waiting_on_load_cycles: 0
- store_waiting_on_store_cycles: 0
- load_waiting_on_load_cycles: 0
- load_waiting_on_store_cycles: 0
-Sequencer: Sequencer_2
- store_waiting_on_load_cycles: 0
- store_waiting_on_store_cycles: 0
- load_waiting_on_load_cycles: 0
- load_waiting_on_store_cycles: 0
-Sequencer: Sequencer_3
- store_waiting_on_load_cycles: 0
- store_waiting_on_store_cycles: 0
- load_waiting_on_load_cycles: 0
- load_waiting_on_store_cycles: 0
-Sequencer: Sequencer_4
- store_waiting_on_load_cycles: 0
- store_waiting_on_store_cycles: 0
- load_waiting_on_load_cycles: 0
- load_waiting_on_store_cycles: 0
-Sequencer: Sequencer_5
- store_waiting_on_load_cycles: 0
- store_waiting_on_store_cycles: 0
- load_waiting_on_load_cycles: 0
- load_waiting_on_store_cycles: 0
-Sequencer: Sequencer_6
- store_waiting_on_load_cycles: 0
- store_waiting_on_store_cycles: 0
- load_waiting_on_load_cycles: 0
- load_waiting_on_store_cycles: 0
-Sequencer: Sequencer_7
- store_waiting_on_load_cycles: 0
- store_waiting_on_store_cycles: 0
- load_waiting_on_load_cycles: 0
- load_waiting_on_store_cycles: 0
-l1d_0 cache stats:
- l1d_0_total_misses: 0
- l1d_0_total_demand_misses: 0
- l1d_0_total_prefetches: 0
- l1d_0_total_sw_prefetches: 0
- l1d_0_total_hw_prefetches: 0
- l1d_0_misses_per_transaction: nan
-
- l1d_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1d_1 cache stats:
- l1d_1_total_misses: 0
- l1d_1_total_demand_misses: 0
- l1d_1_total_prefetches: 0
- l1d_1_total_sw_prefetches: 0
- l1d_1_total_hw_prefetches: 0
- l1d_1_misses_per_transaction: nan
-
- l1d_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1d_2 cache stats:
- l1d_2_total_misses: 0
- l1d_2_total_demand_misses: 0
- l1d_2_total_prefetches: 0
- l1d_2_total_sw_prefetches: 0
- l1d_2_total_hw_prefetches: 0
- l1d_2_misses_per_transaction: nan
-
- l1d_2_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1d_3 cache stats:
- l1d_3_total_misses: 0
- l1d_3_total_demand_misses: 0
- l1d_3_total_prefetches: 0
- l1d_3_total_sw_prefetches: 0
- l1d_3_total_hw_prefetches: 0
- l1d_3_misses_per_transaction: nan
-
- l1d_3_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1d_4 cache stats:
- l1d_4_total_misses: 0
- l1d_4_total_demand_misses: 0
- l1d_4_total_prefetches: 0
- l1d_4_total_sw_prefetches: 0
- l1d_4_total_hw_prefetches: 0
- l1d_4_misses_per_transaction: nan
-
- l1d_4_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1d_5 cache stats:
- l1d_5_total_misses: 0
- l1d_5_total_demand_misses: 0
- l1d_5_total_prefetches: 0
- l1d_5_total_sw_prefetches: 0
- l1d_5_total_hw_prefetches: 0
- l1d_5_misses_per_transaction: nan
-
- l1d_5_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1d_6 cache stats:
- l1d_6_total_misses: 0
- l1d_6_total_demand_misses: 0
- l1d_6_total_prefetches: 0
- l1d_6_total_sw_prefetches: 0
- l1d_6_total_hw_prefetches: 0
- l1d_6_misses_per_transaction: nan
-
- l1d_6_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1d_7 cache stats:
- l1d_7_total_misses: 0
- l1d_7_total_demand_misses: 0
- l1d_7_total_prefetches: 0
- l1d_7_total_sw_prefetches: 0
- l1d_7_total_hw_prefetches: 0
- l1d_7_misses_per_transaction: nan
-
- l1d_7_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1i_0 cache stats:
- l1i_0_total_misses: 0
- l1i_0_total_demand_misses: 0
- l1i_0_total_prefetches: 0
- l1i_0_total_sw_prefetches: 0
- l1i_0_total_hw_prefetches: 0
- l1i_0_misses_per_transaction: nan
-
- l1i_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1i_1 cache stats:
- l1i_1_total_misses: 0
- l1i_1_total_demand_misses: 0
- l1i_1_total_prefetches: 0
- l1i_1_total_sw_prefetches: 0
- l1i_1_total_hw_prefetches: 0
- l1i_1_misses_per_transaction: nan
-
- l1i_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1i_2 cache stats:
- l1i_2_total_misses: 0
- l1i_2_total_demand_misses: 0
- l1i_2_total_prefetches: 0
- l1i_2_total_sw_prefetches: 0
- l1i_2_total_hw_prefetches: 0
- l1i_2_misses_per_transaction: nan
-
- l1i_2_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1i_3 cache stats:
- l1i_3_total_misses: 0
- l1i_3_total_demand_misses: 0
- l1i_3_total_prefetches: 0
- l1i_3_total_sw_prefetches: 0
- l1i_3_total_hw_prefetches: 0
- l1i_3_misses_per_transaction: nan
-
- l1i_3_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1i_4 cache stats:
- l1i_4_total_misses: 0
- l1i_4_total_demand_misses: 0
- l1i_4_total_prefetches: 0
- l1i_4_total_sw_prefetches: 0
- l1i_4_total_hw_prefetches: 0
- l1i_4_misses_per_transaction: nan
-
- l1i_4_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1i_5 cache stats:
- l1i_5_total_misses: 0
- l1i_5_total_demand_misses: 0
- l1i_5_total_prefetches: 0
- l1i_5_total_sw_prefetches: 0
- l1i_5_total_hw_prefetches: 0
- l1i_5_misses_per_transaction: nan
-
- l1i_5_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1i_6 cache stats:
- l1i_6_total_misses: 0
- l1i_6_total_demand_misses: 0
- l1i_6_total_prefetches: 0
- l1i_6_total_sw_prefetches: 0
- l1i_6_total_hw_prefetches: 0
- l1i_6_misses_per_transaction: nan
-
- l1i_6_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l1i_7 cache stats:
- l1i_7_total_misses: 0
- l1i_7_total_demand_misses: 0
- l1i_7_total_prefetches: 0
- l1i_7_total_sw_prefetches: 0
- l1i_7_total_hw_prefetches: 0
- l1i_7_misses_per_transaction: nan
-
- l1i_7_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l2u_0 cache stats:
- l2u_0_total_misses: 0
- l2u_0_total_demand_misses: 0
- l2u_0_total_prefetches: 0
- l2u_0_total_sw_prefetches: 0
- l2u_0_total_hw_prefetches: 0
- l2u_0_misses_per_transaction: nan
-
- l2u_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-l2u_1 cache stats:
- l2u_1_total_misses: 0
- l2u_1_total_demand_misses: 0
- l2u_1_total_prefetches: 0
- l2u_1_total_sw_prefetches: 0
- l2u_1_total_hw_prefetches: 0
- l2u_1_misses_per_transaction: nan
-
- l2u_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- DMA 0 ---
- - Event Counts -
-ReadRequest 0
-WriteRequest 0
-Data 0
-DMA_Ack 0
-Inv_Ack 0
-All_Acks 0
-
- - Transitions -
-READY ReadRequest 0 <--
-READY WriteRequest 0 <--
-
-BUSY_RD Data 0 <--
-BUSY_RD Inv_Ack 0 <--
-BUSY_RD All_Acks 0 <--
-
-BUSY_WR DMA_Ack 0 <--
-BUSY_WR Inv_Ack 0 <--
-BUSY_WR All_Acks 0 <--
-
- --- Directory 0 ---
- - Event Counts -
-GETX 1022
-GETS 1983
-PUTX 0
-PUTO 0
-PUTO_SHARERS 0
-Unblock 0
-Last_Unblock 0
-Exclusive_Unblock 3005
-Clean_Writeback 0
-Dirty_Writeback 0
-Memory_Data 3005
-Memory_Ack 0
-DMA_READ 0
-DMA_WRITE 0
-Data 0
-
- - Transitions -
-I GETX 1022
-I GETS 1983
-I PUTX 0 <--
-I PUTO 0 <--
-I Memory_Data 0 <--
-I Memory_Ack 0 <--
-I DMA_READ 0 <--
-I DMA_WRITE 0 <--
-
-S GETX 0 <--
-S GETS 0 <--
-S PUTX 0 <--
-S PUTO 0 <--
-S Memory_Data 0 <--
-S Memory_Ack 0 <--
-S DMA_READ 0 <--
-S DMA_WRITE 0 <--
-
-O GETX 0 <--
-O GETS 0 <--
-O PUTX 0 <--
-O PUTO 0 <--
-O PUTO_SHARERS 0 <--
-O Memory_Data 0 <--
-O Memory_Ack 0 <--
-O DMA_READ 0 <--
-O DMA_WRITE 0 <--
-
-M GETX 0 <--
-M GETS 0 <--
-M PUTX 0 <--
-M PUTO 0 <--
-M PUTO_SHARERS 0 <--
-M Memory_Data 0 <--
-M Memory_Ack 0 <--
-M DMA_READ 0 <--
-M DMA_WRITE 0 <--
-
-IS GETX 0 <--
-IS GETS 0 <--
-IS PUTX 0 <--
-IS PUTO 0 <--
-IS PUTO_SHARERS 0 <--
-IS Unblock 0 <--
-IS Exclusive_Unblock 1983
-IS Memory_Data 1983
-IS Memory_Ack 0 <--
-IS DMA_READ 0 <--
-IS DMA_WRITE 0 <--
-
-SS GETX 0 <--
-SS GETS 0 <--
-SS PUTX 0 <--
-SS PUTO 0 <--
-SS PUTO_SHARERS 0 <--
-SS Unblock 0 <--
-SS Last_Unblock 0 <--
-SS Memory_Data 0 <--
-SS Memory_Ack 0 <--
-SS DMA_READ 0 <--
-SS DMA_WRITE 0 <--
-
-OO GETX 0 <--
-OO GETS 0 <--
-OO PUTX 0 <--
-OO PUTO 0 <--
-OO PUTO_SHARERS 0 <--
-OO Unblock 0 <--
-OO Last_Unblock 0 <--
-OO Memory_Data 0 <--
-OO Memory_Ack 0 <--
-OO DMA_READ 0 <--
-OO DMA_WRITE 0 <--
-
-MO GETX 0 <--
-MO GETS 0 <--
-MO PUTX 0 <--
-MO PUTO 0 <--
-MO PUTO_SHARERS 0 <--
-MO Unblock 0 <--
-MO Exclusive_Unblock 0 <--
-MO Memory_Data 0 <--
-MO Memory_Ack 0 <--
-MO DMA_READ 0 <--
-MO DMA_WRITE 0 <--
-
-MM GETX 0 <--
-MM GETS 0 <--
-MM PUTX 0 <--
-MM PUTO 0 <--
-MM PUTO_SHARERS 0 <--
-MM Exclusive_Unblock 1022
-MM Memory_Data 1022
-MM Memory_Ack 0 <--
-MM DMA_READ 0 <--
-MM DMA_WRITE 0 <--
-
-
-MI GETX 0 <--
-MI GETS 0 <--
-MI PUTX 0 <--
-MI PUTO 0 <--
-MI PUTO_SHARERS 0 <--
-MI Unblock 0 <--
-MI Clean_Writeback 0 <--
-MI Dirty_Writeback 0 <--
-MI Memory_Data 0 <--
-MI Memory_Ack 0 <--
-MI DMA_READ 0 <--
-MI DMA_WRITE 0 <--
-
-MIS GETX 0 <--
-MIS GETS 0 <--
-MIS PUTX 0 <--
-MIS PUTO 0 <--
-MIS PUTO_SHARERS 0 <--
-MIS Unblock 0 <--
-MIS Clean_Writeback 0 <--
-MIS Dirty_Writeback 0 <--
-MIS Memory_Data 0 <--
-MIS Memory_Ack 0 <--
-MIS DMA_READ 0 <--
-MIS DMA_WRITE 0 <--
-
-OS GETX 0 <--
-OS GETS 0 <--
-OS PUTX 0 <--
-OS PUTO 0 <--
-OS PUTO_SHARERS 0 <--
-OS Unblock 0 <--
-OS Clean_Writeback 0 <--
-OS Dirty_Writeback 0 <--
-OS Memory_Data 0 <--
-OS Memory_Ack 0 <--
-OS DMA_READ 0 <--
-OS DMA_WRITE 0 <--
-
-OSS GETX 0 <--
-OSS GETS 0 <--
-OSS PUTX 0 <--
-OSS PUTO 0 <--
-OSS PUTO_SHARERS 0 <--
-OSS Unblock 0 <--
-OSS Clean_Writeback 0 <--
-OSS Dirty_Writeback 0 <--
-OSS Memory_Data 0 <--
-OSS Memory_Ack 0 <--
-OSS DMA_READ 0 <--
-OSS DMA_WRITE 0 <--
-
-XI_M GETX 0 <--
-XI_M GETS 0 <--
-XI_M PUTX 0 <--
-XI_M PUTO 0 <--
-XI_M PUTO_SHARERS 0 <--
-XI_M Memory_Data 0 <--
-XI_M Memory_Ack 0 <--
-XI_M DMA_READ 0 <--
-XI_M DMA_WRITE 0 <--
-
-XI_U GETX 0 <--
-XI_U GETS 0 <--
-XI_U PUTX 0 <--
-XI_U PUTO 0 <--
-XI_U PUTO_SHARERS 0 <--
-XI_U Exclusive_Unblock 0 <--
-XI_U Memory_Ack 0 <--
-XI_U DMA_READ 0 <--
-XI_U DMA_WRITE 0 <--
-
-OI_D GETX 0 <--
-OI_D GETS 0 <--
-OI_D PUTX 0 <--
-OI_D PUTO 0 <--
-OI_D PUTO_SHARERS 0 <--
-OI_D DMA_READ 0 <--
-OI_D DMA_WRITE 0 <--
-OI_D Data 0 <--
+links_utilized_percent_switch_8: 0.347219
+ links_utilized_percent_switch_8_link_0: 0.138886 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_8_link_1: 0.555552 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_8_link_0_Control: 1226981 9815848 [ 1226981 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_1_Writeback_Control: 1226977 9815816 [ 0 0 1226977 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 9
+switch_9_outlinks: 9
+links_utilized_percent_switch_9: 0.678994
+ links_utilized_percent_switch_9_link_0: 0.694425 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_1: 0.694425 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_2: 0.694425 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_3: 0.694425 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_4: 0.694425 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_5: 0.694425 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_6: 0.694425 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_7: 0.69442 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_9_link_8: 0.555546 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_9_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_0_Writeback_Control: 153371 1226968 [ 0 0 153371 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_1_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_2_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_2_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_3_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_3_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_4_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_4_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_5_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_5_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_6_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_6_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_7_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_7_Writeback_Control: 153371 1226968 [ 0 0 153371 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_9_link_8_Control: 1226981 9815848 [ 1226981 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 153372
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 153372
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 65.2016%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 34.7984%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153372 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153372 average: 1 | standard deviation: 0 | 0 153372 ]
--- L1Cache 0 ---
- Event Counts -
-Load 486730
+Load 100001
Ifetch 0
-Store 262117
-L1_Replacement 721707
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
+Store 53371
+Data 153371
+Fwd_GETX 153371
Inv 0
-Ack 0
-Data 0
-Exclusive_Data 720223
+Replacement 0
Writeback_Ack 0
-Writeback_Ack_Data 720095
Writeback_Nack 0
-All_acks 251979
-Use_Timeout 720212
- Transitions -
-I Load 468247
+I Load 100001
I Ifetch 0 <--
-I Store 251980
-I L1_Replacement 0 <--
+I Store 53371
I Inv 0 <--
+I Replacement 0 <--
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
-
-M Load 10418
+II Writeback_Nack 0 <--
+
+M Load 0 <--
M Ifetch 0 <--
-M Store 5725
-M L1_Replacement 462033
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 758
-M_W Ifetch 0 <--
-M_W Store 401
-M_W L1_Replacement 22
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 467835
-
-MM Load 5853
-MM Ifetch 0 <--
-MM Store 3236
-MM L1_Replacement 258066
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 427
-MM_W Ifetch 0 <--
-MM_W Store 234
-MM_W L1_Replacement 11
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 252377
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 400
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 251979
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 1
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 251979
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 1174
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 468244
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 1027
-MI Ifetch 0 <--
-MI Store 541
-MI L1_Replacement 0 <--
+M Store 0 <--
+M Fwd_GETX 153371
+M Inv 0 <--
+M Replacement 0 <--
+
MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
+MI Inv 0 <--
MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 720095
MI Writeback_Nack 0 <--
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
+MII Fwd_GETX 0 <--
+
+IS Data 100000
+
+IM Data 53371
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 153373
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 153373
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_LD: 64.8843%
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_ST: 35.1157%
+
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
+ system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
--- L1Cache 1 ---
- Event Counts -
-Load 0
+Load 99517
Ifetch 0
-Store 0
-L1_Replacement 0
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
+Store 53858
+Data 153371
+Fwd_GETX 153371
Inv 0
-Ack 0
-Data 0
-Exclusive_Data 0
+Replacement 0
Writeback_Ack 0
-Writeback_Ack_Data 0
Writeback_Nack 0
-All_acks 0
-Use_Timeout 0
- Transitions -
-I Load 0 <--
+I Load 99515
I Ifetch 0 <--
-I Store 0 <--
-I L1_Replacement 0 <--
+I Store 53858
I Inv 0 <--
+I Replacement 0 <--
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
+II Writeback_Nack 0 <--
-M Load 0 <--
+M Load 2
M Ifetch 0 <--
M Store 0 <--
-M L1_Replacement 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 0 <--
-M_W Ifetch 0 <--
-M_W Store 0 <--
-M_W L1_Replacement 0 <--
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 0 <--
-
-MM Load 0 <--
-MM Ifetch 0 <--
-MM Store 0 <--
-MM L1_Replacement 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 0 <--
-MM_W Ifetch 0 <--
-MM_W Store 0 <--
-MM_W L1_Replacement 0 <--
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 0 <--
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 0 <--
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 0 <--
-MI Ifetch 0 <--
-MI Store 0 <--
-MI L1_Replacement 0 <--
+M Fwd_GETX 153371
+M Inv 0 <--
+M Replacement 0 <--
+
MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
+MI Inv 0 <--
MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
+MII Fwd_GETX 0 <--
+
+IS Data 99514
+
+IM Data 53857
+
+Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 153373
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 153373
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_LD: 64.8569%
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_ST: 35.1431%
+
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
+ system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
--- L1Cache 2 ---
- Event Counts -
-Load 0
+Load 99480
Ifetch 0
-Store 0
-L1_Replacement 0
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
+Store 53904
+Data 153371
+Fwd_GETX 153371
Inv 0
-Ack 0
-Data 0
-Exclusive_Data 0
+Replacement 0
Writeback_Ack 0
-Writeback_Ack_Data 0
Writeback_Nack 0
-All_acks 0
-Use_Timeout 0
- Transitions -
-I Load 0 <--
+I Load 99473
I Ifetch 0 <--
-I Store 0 <--
-I L1_Replacement 0 <--
+I Store 53900
I Inv 0 <--
+I Replacement 0 <--
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
+II Writeback_Nack 0 <--
-M Load 0 <--
+M Load 7
M Ifetch 0 <--
-M Store 0 <--
-M L1_Replacement 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 0 <--
-M_W Ifetch 0 <--
-M_W Store 0 <--
-M_W L1_Replacement 0 <--
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 0 <--
-
-MM Load 0 <--
-MM Ifetch 0 <--
-MM Store 0 <--
-MM L1_Replacement 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 0 <--
-MM_W Ifetch 0 <--
-MM_W Store 0 <--
-MM_W L1_Replacement 0 <--
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 0 <--
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 0 <--
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 0 <--
-MI Ifetch 0 <--
-MI Store 0 <--
-MI L1_Replacement 0 <--
+M Store 4
+M Fwd_GETX 153371
+M Inv 0 <--
+M Replacement 0 <--
+
MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
+MI Inv 0 <--
MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
+MII Fwd_GETX 0 <--
+
+IS Data 99472
+
+IM Data 53899
+
+Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 153373
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 153373
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_LD: 65.0871%
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_ST: 34.9129%
+
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
+ system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
--- L1Cache 3 ---
- Event Counts -
-Load 0
+Load 99826
Ifetch 0
-Store 0
-L1_Replacement 0
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
+Store 53547
+Data 153371
+Fwd_GETX 153371
Inv 0
-Ack 0
-Data 0
-Exclusive_Data 0
+Replacement 0
Writeback_Ack 0
-Writeback_Ack_Data 0
Writeback_Nack 0
-All_acks 0
-Use_Timeout 0
- Transitions -
-I Load 0 <--
+I Load 99826
I Ifetch 0 <--
-I Store 0 <--
-I L1_Replacement 0 <--
+I Store 53547
I Inv 0 <--
+I Replacement 0 <--
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
+II Writeback_Nack 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
-M L1_Replacement 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 0 <--
-M_W Ifetch 0 <--
-M_W Store 0 <--
-M_W L1_Replacement 0 <--
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 0 <--
-
-MM Load 0 <--
-MM Ifetch 0 <--
-MM Store 0 <--
-MM L1_Replacement 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 0 <--
-MM_W Ifetch 0 <--
-MM_W Store 0 <--
-MM_W L1_Replacement 0 <--
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 0 <--
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 0 <--
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 0 <--
-MI Ifetch 0 <--
-MI Store 0 <--
-MI L1_Replacement 0 <--
+M Fwd_GETX 153371
+M Inv 0 <--
+M Replacement 0 <--
+
MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
+MI Inv 0 <--
MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
+MII Fwd_GETX 0 <--
+
+IS Data 99825
+
+IM Data 53546
+
+Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 153373
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 153373
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_LD: 65.0043%
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_ST: 34.9957%
+
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
+ system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
--- L1Cache 4 ---
- Event Counts -
-Load 0
+Load 99699
Ifetch 0
-Store 0
-L1_Replacement 0
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
+Store 53674
+Data 153371
+Fwd_GETX 153371
Inv 0
-Ack 0
-Data 0
-Exclusive_Data 0
+Replacement 0
Writeback_Ack 0
-Writeback_Ack_Data 0
Writeback_Nack 0
-All_acks 0
-Use_Timeout 0
- Transitions -
-I Load 0 <--
+I Load 99699
I Ifetch 0 <--
-I Store 0 <--
-I L1_Replacement 0 <--
+I Store 53674
I Inv 0 <--
+I Replacement 0 <--
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
+II Writeback_Nack 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
-M L1_Replacement 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 0 <--
-M_W Ifetch 0 <--
-M_W Store 0 <--
-M_W L1_Replacement 0 <--
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 0 <--
-
-MM Load 0 <--
-MM Ifetch 0 <--
-MM Store 0 <--
-MM L1_Replacement 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 0 <--
-MM_W Ifetch 0 <--
-MM_W Store 0 <--
-MM_W L1_Replacement 0 <--
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 0 <--
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 0 <--
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 0 <--
-MI Ifetch 0 <--
-MI Store 0 <--
-MI L1_Replacement 0 <--
+M Fwd_GETX 153371
+M Inv 0 <--
+M Replacement 0 <--
+
MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
+MI Inv 0 <--
MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
+MII Fwd_GETX 0 <--
+
+IS Data 99698
+
+IM Data 53673
+
+Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 153372
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 153372
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_LD: 65.0692%
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_ST: 34.9308%
+
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153372 100%
+ system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153372 average: 1 | standard deviation: 0 | 0 153372 ]
--- L1Cache 5 ---
- Event Counts -
-Load 0
+Load 99798
Ifetch 0
-Store 0
-L1_Replacement 0
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
+Store 53574
+Data 153371
+Fwd_GETX 153371
Inv 0
-Ack 0
-Data 0
-Exclusive_Data 0
+Replacement 0
Writeback_Ack 0
-Writeback_Ack_Data 0
Writeback_Nack 0
-All_acks 0
-Use_Timeout 0
- Transitions -
-I Load 0 <--
+I Load 99798
I Ifetch 0 <--
-I Store 0 <--
-I L1_Replacement 0 <--
+I Store 53574
I Inv 0 <--
+I Replacement 0 <--
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
+II Writeback_Nack 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
-M L1_Replacement 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 0 <--
-M_W Ifetch 0 <--
-M_W Store 0 <--
-M_W L1_Replacement 0 <--
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 0 <--
-
-MM Load 0 <--
-MM Ifetch 0 <--
-MM Store 0 <--
-MM L1_Replacement 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 0 <--
-MM_W Ifetch 0 <--
-MM_W Store 0 <--
-MM_W L1_Replacement 0 <--
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 0 <--
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 0 <--
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 0 <--
-MI Ifetch 0 <--
-MI Store 0 <--
-MI L1_Replacement 0 <--
+M Fwd_GETX 153371
+M Inv 0 <--
+M Replacement 0 <--
+
MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
+MI Inv 0 <--
MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
+MII Fwd_GETX 0 <--
+
+IS Data 99797
+
+IM Data 53574
+
+Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 153373
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 153373
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_LD: 65.0597%
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_ST: 34.9403%
+
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
+ system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
--- L1Cache 6 ---
- Event Counts -
-Load 0
+Load 99784
Ifetch 0
-Store 0
-L1_Replacement 0
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
+Store 53589
+Data 153371
+Fwd_GETX 153371
Inv 0
-Ack 0
-Data 0
-Exclusive_Data 0
+Replacement 0
Writeback_Ack 0
-Writeback_Ack_Data 0
Writeback_Nack 0
-All_acks 0
-Use_Timeout 0
- Transitions -
-I Load 0 <--
+I Load 99784
I Ifetch 0 <--
-I Store 0 <--
-I L1_Replacement 0 <--
+I Store 53589
I Inv 0 <--
+I Replacement 0 <--
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
+II Writeback_Nack 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
-M L1_Replacement 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 0 <--
-M_W Ifetch 0 <--
-M_W Store 0 <--
-M_W L1_Replacement 0 <--
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 0 <--
-
-MM Load 0 <--
-MM Ifetch 0 <--
-MM Store 0 <--
-MM L1_Replacement 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 0 <--
-MM_W Ifetch 0 <--
-MM_W Store 0 <--
-MM_W L1_Replacement 0 <--
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 0 <--
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 0 <--
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 0 <--
-MI Ifetch 0 <--
-MI Store 0 <--
-MI L1_Replacement 0 <--
+M Fwd_GETX 153371
+M Inv 0 <--
+M Replacement 0 <--
+
MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
+MI Inv 0 <--
MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
+MII Fwd_GETX 0 <--
+
+IS Data 99782
+
+IM Data 53589
+
+Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 153372
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 153372
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_LD: 64.9434%
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_ST: 35.0566%
+
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153372 100%
+ system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153372 average: 1 | standard deviation: 0 | 0 153372 ]
--- L1Cache 7 ---
- Event Counts -
-Load 0
+Load 99605
Ifetch 0
-Store 0
-L1_Replacement 0
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
+Store 53767
+Data 153370
+Fwd_GETX 153370
Inv 0
-Ack 0
-Data 0
-Exclusive_Data 0
+Replacement 0
Writeback_Ack 0
-Writeback_Ack_Data 0
Writeback_Nack 0
-All_acks 0
-Use_Timeout 0
- Transitions -
-I Load 0 <--
+I Load 99605
I Ifetch 0 <--
-I Store 0 <--
-I L1_Replacement 0 <--
+I Store 53767
I Inv 0 <--
+I Replacement 0 <--
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
+II Writeback_Nack 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
-M L1_Replacement 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 0 <--
-M_W Ifetch 0 <--
-M_W Store 0 <--
-M_W L1_Replacement 0 <--
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 0 <--
-
-MM Load 0 <--
-MM Ifetch 0 <--
-MM Store 0 <--
-MM L1_Replacement 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 0 <--
-MM_W Ifetch 0 <--
-MM_W Store 0 <--
-MM_W L1_Replacement 0 <--
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 0 <--
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 0 <--
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 0 <--
-MI Ifetch 0 <--
-MI Store 0 <--
-MI L1_Replacement 0 <--
+M Fwd_GETX 153370
+M Inv 0 <--
+M Replacement 0 <--
+
MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
+MI Inv 0 <--
MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 0 <--
MI Writeback_Nack 0 <--
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
+MII Fwd_GETX 0 <--
- --- L2Cache 0 ---
- - Event Counts -
-L1_GETS 233916
-L1_GETX 125680
-L1_PUTO 0
-L1_PUTX 359416
-L1_PUTS_only 0
-L1_PUTS 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
-Own_GETX 0
-Inv 0
-IntAck 0
-ExtAck 0
-All_Acks 516
-Data 516
-Data_Exclusive 992
-L1_WBCLEANDATA 2649
-L1_WBDIRTYDATA 356765
-Writeback_Ack 0
-Writeback_Nack 0
-Unblock 0
-Exclusive_Unblock 359478
-L2_Replacement 0
+IS Data 99603
- - Transitions -
-NP L1_GETS 992
-NP L1_GETX 516
-NP L1_PUTO 0 <--
-NP L1_PUTX 0 <--
-NP L1_PUTS 0 <--
-NP Inv 0 <--
-
-I L1_GETS 0 <--
-I L1_GETX 0 <--
-I L1_PUTO 0 <--
-I L1_PUTX 0 <--
-I L1_PUTS 0 <--
-I Inv 0 <--
-I L2_Replacement 0 <--
-
-ILS L1_GETS 0 <--
-ILS L1_GETX 0 <--
-ILS L1_PUTO 0 <--
-ILS L1_PUTX 0 <--
-ILS L1_PUTS_only 0 <--
-ILS L1_PUTS 0 <--
-ILS Inv 0 <--
-ILS L2_Replacement 0 <--
-
-ILX L1_GETS 0 <--
-ILX L1_GETX 0 <--
-ILX L1_PUTO 0 <--
-ILX L1_PUTX 359416
-ILX L1_PUTS_only 0 <--
-ILX L1_PUTS 0 <--
-ILX Fwd_GETX 0 <--
-ILX Fwd_GETS 0 <--
-ILX Fwd_DMA 0 <--
-ILX Inv 0 <--
-ILX Data 0 <--
-ILX L2_Replacement 0 <--
-
-ILO L1_GETS 0 <--
-ILO L1_GETX 0 <--
-ILO L1_PUTO 0 <--
-ILO L1_PUTX 0 <--
-ILO L1_PUTS 0 <--
-ILO Fwd_GETX 0 <--
-ILO Fwd_GETS 0 <--
-ILO Fwd_DMA 0 <--
-ILO Inv 0 <--
-ILO Data 0 <--
-ILO L2_Replacement 0 <--
-
-ILOX L1_GETS 0 <--
-ILOX L1_GETX 0 <--
-ILOX L1_PUTO 0 <--
-ILOX L1_PUTX 0 <--
-ILOX L1_PUTS 0 <--
-ILOX Fwd_GETX 0 <--
-ILOX Fwd_GETS 0 <--
-ILOX Fwd_DMA 0 <--
-ILOX Data 0 <--
-
-ILOS L1_GETS 0 <--
-ILOS L1_GETX 0 <--
-ILOS L1_PUTO 0 <--
-ILOS L1_PUTX 0 <--
-ILOS L1_PUTS_only 0 <--
-ILOS L1_PUTS 0 <--
-ILOS Fwd_GETX 0 <--
-ILOS Fwd_GETS 0 <--
-ILOS Fwd_DMA 0 <--
-ILOS Data 0 <--
-ILOS L2_Replacement 0 <--
-
-ILOSX L1_GETS 0 <--
-ILOSX L1_GETX 0 <--
-ILOSX L1_PUTO 0 <--
-ILOSX L1_PUTX 0 <--
-ILOSX L1_PUTS_only 0 <--
-ILOSX L1_PUTS 0 <--
-ILOSX Fwd_GETX 0 <--
-ILOSX Fwd_GETS 0 <--
-ILOSX Fwd_DMA 0 <--
-ILOSX Data 0 <--
-
-S L1_GETS 0 <--
-S L1_GETX 0 <--
-S L1_PUTX 0 <--
-S L1_PUTS 0 <--
-S Inv 0 <--
-S L2_Replacement 0 <--
-
-O L1_GETS 0 <--
-O L1_GETX 0 <--
-O L1_PUTX 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
-O L2_Replacement 0 <--
-
-OLS L1_GETS 0 <--
-OLS L1_GETX 0 <--
-OLS L1_PUTX 0 <--
-OLS L1_PUTS_only 0 <--
-OLS L1_PUTS 0 <--
-OLS Fwd_GETX 0 <--
-OLS Fwd_GETS 0 <--
-OLS Fwd_DMA 0 <--
-OLS L2_Replacement 0 <--
-
-OLSX L1_GETS 0 <--
-OLSX L1_GETX 0 <--
-OLSX L1_PUTO 0 <--
-OLSX L1_PUTX 0 <--
-OLSX L1_PUTS_only 0 <--
-OLSX L1_PUTS 0 <--
-OLSX Fwd_GETX 0 <--
-OLSX Fwd_GETS 0 <--
-OLSX Fwd_DMA 0 <--
-OLSX L2_Replacement 0 <--
-
-SLS L1_GETS 0 <--
-SLS L1_GETX 0 <--
-SLS L1_PUTX 0 <--
-SLS L1_PUTS_only 0 <--
-SLS L1_PUTS 0 <--
-SLS Inv 0 <--
-SLS L2_Replacement 0 <--
-
-M L1_GETS 232846
-M L1_GETX 125126
-M L1_PUTO 0 <--
-M L1_PUTX 0 <--
-M L1_PUTS 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-M L2_Replacement 0 <--
-
-IFGX L1_GETS 0 <--
-IFGX L1_GETX 0 <--
-IFGX L1_PUTO 0 <--
-IFGX L1_PUTX 0 <--
-IFGX L1_PUTS_only 0 <--
-IFGX L1_PUTS 0 <--
-IFGX Fwd_GETX 0 <--
-IFGX Fwd_GETS 0 <--
-IFGX Fwd_DMA 0 <--
-IFGX Inv 0 <--
-IFGX Data 0 <--
-IFGX Data_Exclusive 0 <--
-IFGX L2_Replacement 0 <--
-
-IFGS L1_GETS 0 <--
-IFGS L1_GETX 0 <--
-IFGS L1_PUTO 0 <--
-IFGS L1_PUTX 0 <--
-IFGS L1_PUTS_only 0 <--
-IFGS L1_PUTS 0 <--
-IFGS Fwd_GETX 0 <--
-IFGS Fwd_GETS 0 <--
-IFGS Fwd_DMA 0 <--
-IFGS Inv 0 <--
-IFGS Data 0 <--
-IFGS Data_Exclusive 0 <--
-IFGS L2_Replacement 0 <--
-
-ISFGS L1_GETS 0 <--
-ISFGS L1_GETX 0 <--
-ISFGS L1_PUTO 0 <--
-ISFGS L1_PUTX 0 <--
-ISFGS L1_PUTS_only 0 <--
-ISFGS L1_PUTS 0 <--
-ISFGS Fwd_GETX 0 <--
-ISFGS Fwd_GETS 0 <--
-ISFGS Fwd_DMA 0 <--
-ISFGS Inv 0 <--
-ISFGS Data 0 <--
-ISFGS L2_Replacement 0 <--
-
-IFGXX L1_GETS 0 <--
-IFGXX L1_GETX 0 <--
-IFGXX L1_PUTO 0 <--
-IFGXX L1_PUTX 0 <--
-IFGXX L1_PUTS_only 0 <--
-IFGXX L1_PUTS 0 <--
-IFGXX Fwd_GETX 0 <--
-IFGXX Fwd_GETS 0 <--
-IFGXX Fwd_DMA 0 <--
-IFGXX Inv 0 <--
-IFGXX IntAck 0 <--
-IFGXX All_Acks 0 <--
-IFGXX Data_Exclusive 0 <--
-IFGXX L2_Replacement 0 <--
-
-OFGX L1_GETS 0 <--
-OFGX L1_GETX 0 <--
-OFGX L1_PUTO 0 <--
-OFGX L1_PUTX 0 <--
-OFGX L1_PUTS_only 0 <--
-OFGX L1_PUTS 0 <--
-OFGX Fwd_GETX 0 <--
-OFGX Fwd_GETS 0 <--
-OFGX Fwd_DMA 0 <--
-OFGX Inv 0 <--
-OFGX L2_Replacement 0 <--
-
-OLSF L1_GETS 0 <--
-OLSF L1_GETX 0 <--
-OLSF L1_PUTO 0 <--
-OLSF L1_PUTX 0 <--
-OLSF L1_PUTS_only 0 <--
-OLSF L1_PUTS 0 <--
-OLSF Fwd_GETX 0 <--
-OLSF Fwd_GETS 0 <--
-OLSF Fwd_DMA 0 <--
-OLSF Inv 0 <--
-OLSF IntAck 0 <--
-OLSF All_Acks 0 <--
-OLSF L2_Replacement 0 <--
-
-ILOW L1_GETS 0 <--
-ILOW L1_GETX 0 <--
-ILOW L1_PUTO 0 <--
-ILOW L1_PUTX 0 <--
-ILOW L1_PUTS_only 0 <--
-ILOW L1_PUTS 0 <--
-ILOW Fwd_GETX 0 <--
-ILOW Fwd_GETS 0 <--
-ILOW Fwd_DMA 0 <--
-ILOW Inv 0 <--
-ILOW L1_WBCLEANDATA 0 <--
-ILOW L1_WBDIRTYDATA 0 <--
-ILOW Unblock 0 <--
-ILOW L2_Replacement 0 <--
-
-ILOXW L1_GETS 0 <--
-ILOXW L1_GETX 0 <--
-ILOXW L1_PUTO 0 <--
-ILOXW L1_PUTX 0 <--
-ILOXW L1_PUTS_only 0 <--
-ILOXW L1_PUTS 0 <--
-ILOXW Fwd_GETX 0 <--
-ILOXW Fwd_GETS 0 <--
-ILOXW Fwd_DMA 0 <--
-ILOXW Inv 0 <--
-ILOXW L1_WBCLEANDATA 0 <--
-ILOXW L1_WBDIRTYDATA 0 <--
-ILOXW Unblock 0 <--
-ILOXW L2_Replacement 0 <--
-
-ILOSW L1_GETS 0 <--
-ILOSW L1_GETX 0 <--
-ILOSW L1_PUTO 0 <--
-ILOSW L1_PUTX 0 <--
-ILOSW L1_PUTS_only 0 <--
-ILOSW L1_PUTS 0 <--
-ILOSW Fwd_GETX 0 <--
-ILOSW Fwd_GETS 0 <--
-ILOSW Fwd_DMA 0 <--
-ILOSW Inv 0 <--
-ILOSW L1_WBCLEANDATA 0 <--
-ILOSW L1_WBDIRTYDATA 0 <--
-ILOSW Unblock 0 <--
-ILOSW L2_Replacement 0 <--
-
-ILOSXW L1_GETS 0 <--
-ILOSXW L1_GETX 0 <--
-ILOSXW L1_PUTO 0 <--
-ILOSXW L1_PUTX 0 <--
-ILOSXW L1_PUTS_only 0 <--
-ILOSXW L1_PUTS 0 <--
-ILOSXW Fwd_GETX 0 <--
-ILOSXW Fwd_GETS 0 <--
-ILOSXW Fwd_DMA 0 <--
-ILOSXW Inv 0 <--
-ILOSXW L1_WBCLEANDATA 0 <--
-ILOSXW L1_WBDIRTYDATA 0 <--
-ILOSXW Unblock 0 <--
-ILOSXW L2_Replacement 0 <--
-
-SLSW L1_GETS 0 <--
-SLSW L1_GETX 0 <--
-SLSW L1_PUTO 0 <--
-SLSW L1_PUTX 0 <--
-SLSW L1_PUTS_only 0 <--
-SLSW L1_PUTS 0 <--
-SLSW Fwd_GETX 0 <--
-SLSW Fwd_GETS 0 <--
-SLSW Fwd_DMA 0 <--
-SLSW Inv 0 <--
-SLSW Unblock 0 <--
-SLSW L2_Replacement 0 <--
-
-OLSW L1_GETS 0 <--
-OLSW L1_GETX 0 <--
-OLSW L1_PUTO 0 <--
-OLSW L1_PUTX 0 <--
-OLSW L1_PUTS_only 0 <--
-OLSW L1_PUTS 0 <--
-OLSW Fwd_GETX 0 <--
-OLSW Fwd_GETS 0 <--
-OLSW Fwd_DMA 0 <--
-OLSW Inv 0 <--
-OLSW Unblock 0 <--
-OLSW L2_Replacement 0 <--
-
-ILSW L1_GETS 0 <--
-ILSW L1_GETX 0 <--
-ILSW L1_PUTO 0 <--
-ILSW L1_PUTX 0 <--
-ILSW L1_PUTS_only 0 <--
-ILSW L1_PUTS 0 <--
-ILSW Fwd_GETX 0 <--
-ILSW Fwd_GETS 0 <--
-ILSW Fwd_DMA 0 <--
-ILSW Inv 0 <--
-ILSW L1_WBCLEANDATA 0 <--
-ILSW Unblock 0 <--
-ILSW L2_Replacement 0 <--
-
-IW L1_GETS 0 <--
-IW L1_GETX 0 <--
-IW L1_PUTO 0 <--
-IW L1_PUTX 0 <--
-IW L1_PUTS_only 0 <--
-IW L1_PUTS 0 <--
-IW Fwd_GETX 0 <--
-IW Fwd_GETS 0 <--
-IW Fwd_DMA 0 <--
-IW Inv 0 <--
-IW L1_WBCLEANDATA 0 <--
-IW L2_Replacement 0 <--
-
-OW L1_GETS 0 <--
-OW L1_GETX 0 <--
-OW L1_PUTO 0 <--
-OW L1_PUTX 0 <--
-OW L1_PUTS_only 0 <--
-OW L1_PUTS 0 <--
-OW Fwd_GETX 0 <--
-OW Fwd_GETS 0 <--
-OW Fwd_DMA 0 <--
-OW Inv 0 <--
-OW Unblock 0 <--
-OW L2_Replacement 0 <--
-
-SW L1_GETS 0 <--
-SW L1_GETX 0 <--
-SW L1_PUTO 0 <--
-SW L1_PUTX 0 <--
-SW L1_PUTS_only 0 <--
-SW L1_PUTS 0 <--
-SW Fwd_GETX 0 <--
-SW Fwd_GETS 0 <--
-SW Fwd_DMA 0 <--
-SW Inv 0 <--
-SW Unblock 0 <--
-SW L2_Replacement 0 <--
-
-OXW L1_GETS 0 <--
-OXW L1_GETX 0 <--
-OXW L1_PUTO 0 <--
-OXW L1_PUTX 0 <--
-OXW L1_PUTS_only 0 <--
-OXW L1_PUTS 0 <--
-OXW Fwd_GETX 0 <--
-OXW Fwd_GETS 0 <--
-OXW Fwd_DMA 0 <--
-OXW Inv 0 <--
-OXW Unblock 0 <--
-OXW L2_Replacement 0 <--
-
-OLSXW L1_GETS 0 <--
-OLSXW L1_GETX 0 <--
-OLSXW L1_PUTO 0 <--
-OLSXW L1_PUTX 0 <--
-OLSXW L1_PUTS_only 0 <--
-OLSXW L1_PUTS 0 <--
-OLSXW Fwd_GETX 0 <--
-OLSXW Fwd_GETS 0 <--
-OLSXW Fwd_DMA 0 <--
-OLSXW Inv 0 <--
-OLSXW Unblock 0 <--
-OLSXW L2_Replacement 0 <--
-
-ILXW L1_GETS 78
-ILXW L1_GETX 38
-ILXW L1_PUTO 0 <--
-ILXW L1_PUTX 0 <--
-ILXW L1_PUTS_only 0 <--
-ILXW L1_PUTS 0 <--
-ILXW Fwd_GETX 0 <--
-ILXW Fwd_GETS 0 <--
-ILXW Fwd_DMA 0 <--
-ILXW Inv 0 <--
-ILXW Data 0 <--
-ILXW L1_WBCLEANDATA 2649
-ILXW L1_WBDIRTYDATA 356765
-ILXW Unblock 0 <--
-ILXW L2_Replacement 0 <--
-
-IFLS L1_GETS 0 <--
-IFLS L1_GETX 0 <--
-IFLS L1_PUTO 0 <--
-IFLS L1_PUTX 0 <--
-IFLS L1_PUTS_only 0 <--
-IFLS L1_PUTS 0 <--
-IFLS Fwd_GETX 0 <--
-IFLS Fwd_GETS 0 <--
-IFLS Fwd_DMA 0 <--
-IFLS Inv 0 <--
-IFLS Unblock 0 <--
-IFLS L2_Replacement 0 <--
-
-IFLO L1_GETS 0 <--
-IFLO L1_GETX 0 <--
-IFLO L1_PUTO 0 <--
-IFLO L1_PUTX 0 <--
-IFLO L1_PUTS_only 0 <--
-IFLO L1_PUTS 0 <--
-IFLO Fwd_GETX 0 <--
-IFLO Fwd_GETS 0 <--
-IFLO Fwd_DMA 0 <--
-IFLO Inv 0 <--
-IFLO Unblock 0 <--
-IFLO L2_Replacement 0 <--
-
-IFLOX L1_GETS 0 <--
-IFLOX L1_GETX 0 <--
-IFLOX L1_PUTO 0 <--
-IFLOX L1_PUTX 0 <--
-IFLOX L1_PUTS_only 0 <--
-IFLOX L1_PUTS 0 <--
-IFLOX Fwd_GETX 0 <--
-IFLOX Fwd_GETS 0 <--
-IFLOX Fwd_DMA 0 <--
-IFLOX Inv 0 <--
-IFLOX Unblock 0 <--
-IFLOX Exclusive_Unblock 0 <--
-IFLOX L2_Replacement 0 <--
-
-IFLOXX L1_GETS 0 <--
-IFLOXX L1_GETX 0 <--
-IFLOXX L1_PUTO 0 <--
-IFLOXX L1_PUTX 0 <--
-IFLOXX L1_PUTS_only 0 <--
-IFLOXX L1_PUTS 0 <--
-IFLOXX Fwd_GETX 0 <--
-IFLOXX Fwd_GETS 0 <--
-IFLOXX Fwd_DMA 0 <--
-IFLOXX Inv 0 <--
-IFLOXX Unblock 0 <--
-IFLOXX Exclusive_Unblock 0 <--
-IFLOXX L2_Replacement 0 <--
-
-IFLOSX L1_GETS 0 <--
-IFLOSX L1_GETX 0 <--
-IFLOSX L1_PUTO 0 <--
-IFLOSX L1_PUTX 0 <--
-IFLOSX L1_PUTS_only 0 <--
-IFLOSX L1_PUTS 0 <--
-IFLOSX Fwd_GETX 0 <--
-IFLOSX Fwd_GETS 0 <--
-IFLOSX Fwd_DMA 0 <--
-IFLOSX Inv 0 <--
-IFLOSX Unblock 0 <--
-IFLOSX Exclusive_Unblock 0 <--
-IFLOSX L2_Replacement 0 <--
-
-IFLXO L1_GETS 0 <--
-IFLXO L1_GETX 0 <--
-IFLXO L1_PUTO 0 <--
-IFLXO L1_PUTX 0 <--
-IFLXO L1_PUTS_only 0 <--
-IFLXO L1_PUTS 0 <--
-IFLXO Fwd_GETX 0 <--
-IFLXO Fwd_GETS 0 <--
-IFLXO Fwd_DMA 0 <--
-IFLXO Inv 0 <--
-IFLXO Exclusive_Unblock 0 <--
-IFLXO L2_Replacement 0 <--
-
-IGS L1_GETS 0 <--
-IGS L1_GETX 0 <--
-IGS L1_PUTO 0 <--
-IGS L1_PUTX 0 <--
-IGS L1_PUTS_only 0 <--
-IGS L1_PUTS 0 <--
-IGS Fwd_GETX 0 <--
-IGS Fwd_GETS 0 <--
-IGS Fwd_DMA 0 <--
-IGS Own_GETX 0 <--
-IGS Inv 0 <--
-IGS Data 0 <--
-IGS Data_Exclusive 992
-IGS Unblock 0 <--
-IGS Exclusive_Unblock 992
-IGS L2_Replacement 0 <--
-
-IGM L1_GETS 0 <--
-IGM L1_GETX 0 <--
-IGM L1_PUTO 0 <--
-IGM L1_PUTX 0 <--
-IGM L1_PUTS_only 0 <--
-IGM L1_PUTS 0 <--
-IGM Fwd_GETX 0 <--
-IGM Fwd_GETS 0 <--
-IGM Fwd_DMA 0 <--
-IGM Own_GETX 0 <--
-IGM Inv 0 <--
-IGM ExtAck 0 <--
-IGM Data 516
-IGM Data_Exclusive 0 <--
-IGM L2_Replacement 0 <--
-
-IGMLS L1_GETS 0 <--
-IGMLS L1_GETX 0 <--
-IGMLS L1_PUTO 0 <--
-IGMLS L1_PUTX 0 <--
-IGMLS L1_PUTS_only 0 <--
-IGMLS L1_PUTS 0 <--
-IGMLS Inv 0 <--
-IGMLS IntAck 0 <--
-IGMLS ExtAck 0 <--
-IGMLS All_Acks 0 <--
-IGMLS Data 0 <--
-IGMLS Data_Exclusive 0 <--
-IGMLS L2_Replacement 0 <--
-
-IGMO L1_GETS 0 <--
-IGMO L1_GETX 0 <--
-IGMO L1_PUTO 0 <--
-IGMO L1_PUTX 0 <--
-IGMO L1_PUTS_only 0 <--
-IGMO L1_PUTS 0 <--
-IGMO Fwd_GETX 0 <--
-IGMO Fwd_GETS 0 <--
-IGMO Fwd_DMA 0 <--
-IGMO Own_GETX 0 <--
-IGMO ExtAck 0 <--
-IGMO All_Acks 516
-IGMO Exclusive_Unblock 516
-IGMO L2_Replacement 0 <--
-
-IGMIO L1_GETS 0 <--
-IGMIO L1_GETX 0 <--
-IGMIO L1_PUTO 0 <--
-IGMIO L1_PUTX 0 <--
-IGMIO L1_PUTS_only 0 <--
-IGMIO L1_PUTS 0 <--
-IGMIO Fwd_GETX 0 <--
-IGMIO Fwd_GETS 0 <--
-IGMIO Fwd_DMA 0 <--
-IGMIO Own_GETX 0 <--
-IGMIO ExtAck 0 <--
-IGMIO All_Acks 0 <--
-
-OGMIO L1_GETS 0 <--
-OGMIO L1_GETX 0 <--
-OGMIO L1_PUTO 0 <--
-OGMIO L1_PUTX 0 <--
-OGMIO L1_PUTS_only 0 <--
-OGMIO L1_PUTS 0 <--
-OGMIO Fwd_GETX 0 <--
-OGMIO Fwd_GETS 0 <--
-OGMIO Fwd_DMA 0 <--
-OGMIO Own_GETX 0 <--
-OGMIO ExtAck 0 <--
-OGMIO All_Acks 0 <--
-
-IGMIOF L1_GETS 0 <--
-IGMIOF L1_GETX 0 <--
-IGMIOF L1_PUTO 0 <--
-IGMIOF L1_PUTX 0 <--
-IGMIOF L1_PUTS_only 0 <--
-IGMIOF L1_PUTS 0 <--
-IGMIOF IntAck 0 <--
-IGMIOF All_Acks 0 <--
-IGMIOF Data_Exclusive 0 <--
-
-IGMIOFS L1_GETS 0 <--
-IGMIOFS L1_GETX 0 <--
-IGMIOFS L1_PUTO 0 <--
-IGMIOFS L1_PUTX 0 <--
-IGMIOFS L1_PUTS_only 0 <--
-IGMIOFS L1_PUTS 0 <--
-IGMIOFS Fwd_GETX 0 <--
-IGMIOFS Fwd_GETS 0 <--
-IGMIOFS Fwd_DMA 0 <--
-IGMIOFS Inv 0 <--
-IGMIOFS Data 0 <--
-IGMIOFS L2_Replacement 0 <--
-
-OGMIOF L1_GETS 0 <--
-OGMIOF L1_GETX 0 <--
-OGMIOF L1_PUTO 0 <--
-OGMIOF L1_PUTX 0 <--
-OGMIOF L1_PUTS_only 0 <--
-OGMIOF L1_PUTS 0 <--
-OGMIOF IntAck 0 <--
-OGMIOF All_Acks 0 <--
-
-II L1_GETS 0 <--
-II L1_GETX 0 <--
-II L1_PUTO 0 <--
-II L1_PUTX 0 <--
-II L1_PUTS_only 0 <--
-II L1_PUTS 0 <--
-II IntAck 0 <--
-II All_Acks 0 <--
-
-MM L1_GETS 0 <--
-MM L1_GETX 0 <--
-MM L1_PUTO 0 <--
-MM L1_PUTX 0 <--
-MM L1_PUTS_only 0 <--
-MM L1_PUTS 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-MM Inv 0 <--
-MM Exclusive_Unblock 125126
-MM L2_Replacement 0 <--
-
-SS L1_GETS 0 <--
-SS L1_GETX 0 <--
-SS L1_PUTO 0 <--
-SS L1_PUTX 0 <--
-SS L1_PUTS_only 0 <--
-SS L1_PUTS 0 <--
-SS Fwd_GETX 0 <--
-SS Fwd_GETS 0 <--
-SS Fwd_DMA 0 <--
-SS Inv 0 <--
-SS Unblock 0 <--
-SS L2_Replacement 0 <--
-
-OO L1_GETS 0 <--
-OO L1_GETX 0 <--
-OO L1_PUTO 0 <--
-OO L1_PUTX 0 <--
-OO L1_PUTS_only 0 <--
-OO L1_PUTS 0 <--
-OO Fwd_GETX 0 <--
-OO Fwd_GETS 0 <--
-OO Fwd_DMA 0 <--
-OO Inv 0 <--
-OO Unblock 0 <--
-OO Exclusive_Unblock 232844
-OO L2_Replacement 0 <--
-
-OLSS L1_GETS 0 <--
-OLSS L1_GETX 0 <--
-OLSS L1_PUTO 0 <--
-OLSS L1_PUTX 0 <--
-OLSS L1_PUTS_only 0 <--
-OLSS L1_PUTS 0 <--
-OLSS Fwd_GETX 0 <--
-OLSS Fwd_GETS 0 <--
-OLSS Fwd_DMA 0 <--
-OLSS Inv 0 <--
-OLSS Unblock 0 <--
-OLSS L2_Replacement 0 <--
-
-OLSXS L1_GETS 0 <--
-OLSXS L1_GETX 0 <--
-OLSXS L1_PUTO 0 <--
-OLSXS L1_PUTX 0 <--
-OLSXS L1_PUTS_only 0 <--
-OLSXS L1_PUTS 0 <--
-OLSXS Fwd_GETX 0 <--
-OLSXS Fwd_GETS 0 <--
-OLSXS Fwd_DMA 0 <--
-OLSXS Inv 0 <--
-OLSXS Unblock 0 <--
-OLSXS L2_Replacement 0 <--
-
-SLSS L1_GETS 0 <--
-SLSS L1_GETX 0 <--
-SLSS L1_PUTO 0 <--
-SLSS L1_PUTX 0 <--
-SLSS L1_PUTS_only 0 <--
-SLSS L1_PUTS 0 <--
-SLSS Fwd_GETX 0 <--
-SLSS Fwd_GETS 0 <--
-SLSS Fwd_DMA 0 <--
-SLSS Inv 0 <--
-SLSS Unblock 0 <--
-SLSS L2_Replacement 0 <--
-
-OI L1_GETS 0 <--
-OI L1_GETX 0 <--
-OI L1_PUTO 0 <--
-OI L1_PUTX 0 <--
-OI L1_PUTS_only 0 <--
-OI L1_PUTS 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Nack 0 <--
-OI L2_Replacement 0 <--
-
-MI L1_GETS 0 <--
-MI L1_GETX 0 <--
-MI L1_PUTO 0 <--
-MI L1_PUTX 0 <--
-MI L1_PUTS_only 0 <--
-MI L1_PUTS 0 <--
-MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
-MI Writeback_Ack 0 <--
-MI L2_Replacement 0 <--
-
-MII L1_GETS 0 <--
-MII L1_GETX 0 <--
-MII L1_PUTO 0 <--
-MII L1_PUTX 0 <--
-MII L1_PUTS_only 0 <--
-MII L1_PUTS 0 <--
-MII Writeback_Ack 0 <--
-MII Writeback_Nack 0 <--
-MII L2_Replacement 0 <--
-
-OLSI L1_GETS 0 <--
-OLSI L1_GETX 0 <--
-OLSI L1_PUTO 0 <--
-OLSI L1_PUTX 0 <--
-OLSI L1_PUTS_only 0 <--
-OLSI L1_PUTS 0 <--
-OLSI Fwd_GETX 0 <--
-OLSI Fwd_GETS 0 <--
-OLSI Fwd_DMA 0 <--
-OLSI Writeback_Ack 0 <--
-OLSI L2_Replacement 0 <--
-
-ILSI L1_GETS 0 <--
-ILSI L1_GETX 0 <--
-ILSI L1_PUTO 0 <--
-ILSI L1_PUTX 0 <--
-ILSI L1_PUTS_only 0 <--
-ILSI L1_PUTS 0 <--
-ILSI IntAck 0 <--
-ILSI All_Acks 0 <--
-ILSI Writeback_Ack 0 <--
-ILSI L2_Replacement 0 <--
-
- --- L2Cache 1 ---
+IM Data 53767
+
+Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer:
+ memory_total_requests: 2
+ memory_reads: 2
+ memory_writes: 0
+ memory_refreshes: 22
+ memory_total_request_delays: 31
+ memory_delays_per_request: 15.5
+ memory_delays_in_input_queue: 1
+ memory_delays_behind_head_of_bank_queue: 10
+ memory_delays_stalled_at_head_of_bank_queue: 20
+ memory_stalls_for_bank_busy: 20
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 0
+ memory_stalls_for_bus: 0
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 0
+ memory_stalls_for_read_read_turnaround: 0
+ accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+
+ --- Directory 0 ---
- Event Counts -
-L1_GETS 234483
-L1_GETX 126367
-L1_PUTO 0
-L1_PUTX 360682
-L1_PUTS_only 0
-L1_PUTS 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
-Own_GETX 0
-Inv 0
-IntAck 0
-ExtAck 0
-All_Acks 506
-Data 506
-Data_Exclusive 991
-L1_WBCLEANDATA 2626
-L1_WBDIRTYDATA 358053
-Writeback_Ack 0
-Writeback_Nack 0
-Unblock 0
-Exclusive_Unblock 360743
-L2_Replacement 0
+GETX 1227392
+GETS 0
+PUTX 0
+PUTX_NotOwner 0
+DMA_READ 0
+DMA_WRITE 0
+Memory_Data 2
+Memory_Ack 0
- Transitions -
-NP L1_GETS 991
-NP L1_GETX 506
-NP L1_PUTO 0 <--
-NP L1_PUTX 0 <--
-NP L1_PUTS 0 <--
-NP Inv 0 <--
-
-I L1_GETS 0 <--
-I L1_GETX 0 <--
-I L1_PUTO 0 <--
-I L1_PUTX 0 <--
-I L1_PUTS 0 <--
-I Inv 0 <--
-I L2_Replacement 0 <--
-
-ILS L1_GETS 0 <--
-ILS L1_GETX 0 <--
-ILS L1_PUTO 0 <--
-ILS L1_PUTX 0 <--
-ILS L1_PUTS_only 0 <--
-ILS L1_PUTS 0 <--
-ILS Inv 0 <--
-ILS L2_Replacement 0 <--
-
-ILX L1_GETS 0 <--
-ILX L1_GETX 0 <--
-ILX L1_PUTO 0 <--
-ILX L1_PUTX 360682
-ILX L1_PUTS_only 0 <--
-ILX L1_PUTS 0 <--
-ILX Fwd_GETX 0 <--
-ILX Fwd_GETS 0 <--
-ILX Fwd_DMA 0 <--
-ILX Inv 0 <--
-ILX Data 0 <--
-ILX L2_Replacement 0 <--
-
-ILO L1_GETS 0 <--
-ILO L1_GETX 0 <--
-ILO L1_PUTO 0 <--
-ILO L1_PUTX 0 <--
-ILO L1_PUTS 0 <--
-ILO Fwd_GETX 0 <--
-ILO Fwd_GETS 0 <--
-ILO Fwd_DMA 0 <--
-ILO Inv 0 <--
-ILO Data 0 <--
-ILO L2_Replacement 0 <--
-
-ILOX L1_GETS 0 <--
-ILOX L1_GETX 0 <--
-ILOX L1_PUTO 0 <--
-ILOX L1_PUTX 0 <--
-ILOX L1_PUTS 0 <--
-ILOX Fwd_GETX 0 <--
-ILOX Fwd_GETS 0 <--
-ILOX Fwd_DMA 0 <--
-ILOX Data 0 <--
-
-ILOS L1_GETS 0 <--
-ILOS L1_GETX 0 <--
-ILOS L1_PUTO 0 <--
-ILOS L1_PUTX 0 <--
-ILOS L1_PUTS_only 0 <--
-ILOS L1_PUTS 0 <--
-ILOS Fwd_GETX 0 <--
-ILOS Fwd_GETS 0 <--
-ILOS Fwd_DMA 0 <--
-ILOS Data 0 <--
-ILOS L2_Replacement 0 <--
-
-ILOSX L1_GETS 0 <--
-ILOSX L1_GETX 0 <--
-ILOSX L1_PUTO 0 <--
-ILOSX L1_PUTX 0 <--
-ILOSX L1_PUTS_only 0 <--
-ILOSX L1_PUTS 0 <--
-ILOSX Fwd_GETX 0 <--
-ILOSX Fwd_GETS 0 <--
-ILOSX Fwd_DMA 0 <--
-ILOSX Data 0 <--
-
-S L1_GETS 0 <--
-S L1_GETX 0 <--
-S L1_PUTX 0 <--
-S L1_PUTS 0 <--
-S Inv 0 <--
-S L2_Replacement 0 <--
-
-O L1_GETS 0 <--
-O L1_GETX 0 <--
-O L1_PUTX 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
-O L2_Replacement 0 <--
-
-OLS L1_GETS 0 <--
-OLS L1_GETX 0 <--
-OLS L1_PUTX 0 <--
-OLS L1_PUTS_only 0 <--
-OLS L1_PUTS 0 <--
-OLS Fwd_GETX 0 <--
-OLS Fwd_GETS 0 <--
-OLS Fwd_DMA 0 <--
-OLS L2_Replacement 0 <--
-
-OLSX L1_GETS 0 <--
-OLSX L1_GETX 0 <--
-OLSX L1_PUTO 0 <--
-OLSX L1_PUTX 0 <--
-OLSX L1_PUTS_only 0 <--
-OLSX L1_PUTS 0 <--
-OLSX Fwd_GETX 0 <--
-OLSX Fwd_GETS 0 <--
-OLSX Fwd_DMA 0 <--
-OLSX L2_Replacement 0 <--
-
-SLS L1_GETS 0 <--
-SLS L1_GETX 0 <--
-SLS L1_PUTX 0 <--
-SLS L1_PUTS_only 0 <--
-SLS L1_PUTS 0 <--
-SLS Inv 0 <--
-SLS L2_Replacement 0 <--
-
-M L1_GETS 233418
-M L1_GETX 125831
-M L1_PUTO 0 <--
-M L1_PUTX 0 <--
-M L1_PUTS 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-M L2_Replacement 0 <--
-
-IFGX L1_GETS 0 <--
-IFGX L1_GETX 0 <--
-IFGX L1_PUTO 0 <--
-IFGX L1_PUTX 0 <--
-IFGX L1_PUTS_only 0 <--
-IFGX L1_PUTS 0 <--
-IFGX Fwd_GETX 0 <--
-IFGX Fwd_GETS 0 <--
-IFGX Fwd_DMA 0 <--
-IFGX Inv 0 <--
-IFGX Data 0 <--
-IFGX Data_Exclusive 0 <--
-IFGX L2_Replacement 0 <--
-
-IFGS L1_GETS 0 <--
-IFGS L1_GETX 0 <--
-IFGS L1_PUTO 0 <--
-IFGS L1_PUTX 0 <--
-IFGS L1_PUTS_only 0 <--
-IFGS L1_PUTS 0 <--
-IFGS Fwd_GETX 0 <--
-IFGS Fwd_GETS 0 <--
-IFGS Fwd_DMA 0 <--
-IFGS Inv 0 <--
-IFGS Data 0 <--
-IFGS Data_Exclusive 0 <--
-IFGS L2_Replacement 0 <--
-
-ISFGS L1_GETS 0 <--
-ISFGS L1_GETX 0 <--
-ISFGS L1_PUTO 0 <--
-ISFGS L1_PUTX 0 <--
-ISFGS L1_PUTS_only 0 <--
-ISFGS L1_PUTS 0 <--
-ISFGS Fwd_GETX 0 <--
-ISFGS Fwd_GETS 0 <--
-ISFGS Fwd_DMA 0 <--
-ISFGS Inv 0 <--
-ISFGS Data 0 <--
-ISFGS L2_Replacement 0 <--
-
-IFGXX L1_GETS 0 <--
-IFGXX L1_GETX 0 <--
-IFGXX L1_PUTO 0 <--
-IFGXX L1_PUTX 0 <--
-IFGXX L1_PUTS_only 0 <--
-IFGXX L1_PUTS 0 <--
-IFGXX Fwd_GETX 0 <--
-IFGXX Fwd_GETS 0 <--
-IFGXX Fwd_DMA 0 <--
-IFGXX Inv 0 <--
-IFGXX IntAck 0 <--
-IFGXX All_Acks 0 <--
-IFGXX Data_Exclusive 0 <--
-IFGXX L2_Replacement 0 <--
-
-OFGX L1_GETS 0 <--
-OFGX L1_GETX 0 <--
-OFGX L1_PUTO 0 <--
-OFGX L1_PUTX 0 <--
-OFGX L1_PUTS_only 0 <--
-OFGX L1_PUTS 0 <--
-OFGX Fwd_GETX 0 <--
-OFGX Fwd_GETS 0 <--
-OFGX Fwd_DMA 0 <--
-OFGX Inv 0 <--
-OFGX L2_Replacement 0 <--
-
-OLSF L1_GETS 0 <--
-OLSF L1_GETX 0 <--
-OLSF L1_PUTO 0 <--
-OLSF L1_PUTX 0 <--
-OLSF L1_PUTS_only 0 <--
-OLSF L1_PUTS 0 <--
-OLSF Fwd_GETX 0 <--
-OLSF Fwd_GETS 0 <--
-OLSF Fwd_DMA 0 <--
-OLSF Inv 0 <--
-OLSF IntAck 0 <--
-OLSF All_Acks 0 <--
-OLSF L2_Replacement 0 <--
-
-ILOW L1_GETS 0 <--
-ILOW L1_GETX 0 <--
-ILOW L1_PUTO 0 <--
-ILOW L1_PUTX 0 <--
-ILOW L1_PUTS_only 0 <--
-ILOW L1_PUTS 0 <--
-ILOW Fwd_GETX 0 <--
-ILOW Fwd_GETS 0 <--
-ILOW Fwd_DMA 0 <--
-ILOW Inv 0 <--
-ILOW L1_WBCLEANDATA 0 <--
-ILOW L1_WBDIRTYDATA 0 <--
-ILOW Unblock 0 <--
-ILOW L2_Replacement 0 <--
-
-ILOXW L1_GETS 0 <--
-ILOXW L1_GETX 0 <--
-ILOXW L1_PUTO 0 <--
-ILOXW L1_PUTX 0 <--
-ILOXW L1_PUTS_only 0 <--
-ILOXW L1_PUTS 0 <--
-ILOXW Fwd_GETX 0 <--
-ILOXW Fwd_GETS 0 <--
-ILOXW Fwd_DMA 0 <--
-ILOXW Inv 0 <--
-ILOXW L1_WBCLEANDATA 0 <--
-ILOXW L1_WBDIRTYDATA 0 <--
-ILOXW Unblock 0 <--
-ILOXW L2_Replacement 0 <--
-
-ILOSW L1_GETS 0 <--
-ILOSW L1_GETX 0 <--
-ILOSW L1_PUTO 0 <--
-ILOSW L1_PUTX 0 <--
-ILOSW L1_PUTS_only 0 <--
-ILOSW L1_PUTS 0 <--
-ILOSW Fwd_GETX 0 <--
-ILOSW Fwd_GETS 0 <--
-ILOSW Fwd_DMA 0 <--
-ILOSW Inv 0 <--
-ILOSW L1_WBCLEANDATA 0 <--
-ILOSW L1_WBDIRTYDATA 0 <--
-ILOSW Unblock 0 <--
-ILOSW L2_Replacement 0 <--
-
-ILOSXW L1_GETS 0 <--
-ILOSXW L1_GETX 0 <--
-ILOSXW L1_PUTO 0 <--
-ILOSXW L1_PUTX 0 <--
-ILOSXW L1_PUTS_only 0 <--
-ILOSXW L1_PUTS 0 <--
-ILOSXW Fwd_GETX 0 <--
-ILOSXW Fwd_GETS 0 <--
-ILOSXW Fwd_DMA 0 <--
-ILOSXW Inv 0 <--
-ILOSXW L1_WBCLEANDATA 0 <--
-ILOSXW L1_WBDIRTYDATA 0 <--
-ILOSXW Unblock 0 <--
-ILOSXW L2_Replacement 0 <--
-
-SLSW L1_GETS 0 <--
-SLSW L1_GETX 0 <--
-SLSW L1_PUTO 0 <--
-SLSW L1_PUTX 0 <--
-SLSW L1_PUTS_only 0 <--
-SLSW L1_PUTS 0 <--
-SLSW Fwd_GETX 0 <--
-SLSW Fwd_GETS 0 <--
-SLSW Fwd_DMA 0 <--
-SLSW Inv 0 <--
-SLSW Unblock 0 <--
-SLSW L2_Replacement 0 <--
-
-OLSW L1_GETS 0 <--
-OLSW L1_GETX 0 <--
-OLSW L1_PUTO 0 <--
-OLSW L1_PUTX 0 <--
-OLSW L1_PUTS_only 0 <--
-OLSW L1_PUTS 0 <--
-OLSW Fwd_GETX 0 <--
-OLSW Fwd_GETS 0 <--
-OLSW Fwd_DMA 0 <--
-OLSW Inv 0 <--
-OLSW Unblock 0 <--
-OLSW L2_Replacement 0 <--
-
-ILSW L1_GETS 0 <--
-ILSW L1_GETX 0 <--
-ILSW L1_PUTO 0 <--
-ILSW L1_PUTX 0 <--
-ILSW L1_PUTS_only 0 <--
-ILSW L1_PUTS 0 <--
-ILSW Fwd_GETX 0 <--
-ILSW Fwd_GETS 0 <--
-ILSW Fwd_DMA 0 <--
-ILSW Inv 0 <--
-ILSW L1_WBCLEANDATA 0 <--
-ILSW Unblock 0 <--
-ILSW L2_Replacement 0 <--
-
-IW L1_GETS 0 <--
-IW L1_GETX 0 <--
-IW L1_PUTO 0 <--
-IW L1_PUTX 0 <--
-IW L1_PUTS_only 0 <--
-IW L1_PUTS 0 <--
-IW Fwd_GETX 0 <--
-IW Fwd_GETS 0 <--
-IW Fwd_DMA 0 <--
-IW Inv 0 <--
-IW L1_WBCLEANDATA 0 <--
-IW L2_Replacement 0 <--
-
-OW L1_GETS 0 <--
-OW L1_GETX 0 <--
-OW L1_PUTO 0 <--
-OW L1_PUTX 0 <--
-OW L1_PUTS_only 0 <--
-OW L1_PUTS 0 <--
-OW Fwd_GETX 0 <--
-OW Fwd_GETS 0 <--
-OW Fwd_DMA 0 <--
-OW Inv 0 <--
-OW Unblock 0 <--
-OW L2_Replacement 0 <--
-
-SW L1_GETS 0 <--
-SW L1_GETX 0 <--
-SW L1_PUTO 0 <--
-SW L1_PUTX 0 <--
-SW L1_PUTS_only 0 <--
-SW L1_PUTS 0 <--
-SW Fwd_GETX 0 <--
-SW Fwd_GETS 0 <--
-SW Fwd_DMA 0 <--
-SW Inv 0 <--
-SW Unblock 0 <--
-SW L2_Replacement 0 <--
-
-OXW L1_GETS 0 <--
-OXW L1_GETX 0 <--
-OXW L1_PUTO 0 <--
-OXW L1_PUTX 0 <--
-OXW L1_PUTS_only 0 <--
-OXW L1_PUTS 0 <--
-OXW Fwd_GETX 0 <--
-OXW Fwd_GETS 0 <--
-OXW Fwd_DMA 0 <--
-OXW Inv 0 <--
-OXW Unblock 0 <--
-OXW L2_Replacement 0 <--
-
-OLSXW L1_GETS 0 <--
-OLSXW L1_GETX 0 <--
-OLSXW L1_PUTO 0 <--
-OLSXW L1_PUTX 0 <--
-OLSXW L1_PUTS_only 0 <--
-OLSXW L1_PUTS 0 <--
-OLSXW Fwd_GETX 0 <--
-OLSXW Fwd_GETS 0 <--
-OLSXW Fwd_DMA 0 <--
-OLSXW Inv 0 <--
-OLSXW Unblock 0 <--
-OLSXW L2_Replacement 0 <--
-
-ILXW L1_GETS 74
-ILXW L1_GETX 30
-ILXW L1_PUTO 0 <--
-ILXW L1_PUTX 0 <--
-ILXW L1_PUTS_only 0 <--
-ILXW L1_PUTS 0 <--
-ILXW Fwd_GETX 0 <--
-ILXW Fwd_GETS 0 <--
-ILXW Fwd_DMA 0 <--
-ILXW Inv 0 <--
-ILXW Data 0 <--
-ILXW L1_WBCLEANDATA 2626
-ILXW L1_WBDIRTYDATA 358053
-ILXW Unblock 0 <--
-ILXW L2_Replacement 0 <--
-
-IFLS L1_GETS 0 <--
-IFLS L1_GETX 0 <--
-IFLS L1_PUTO 0 <--
-IFLS L1_PUTX 0 <--
-IFLS L1_PUTS_only 0 <--
-IFLS L1_PUTS 0 <--
-IFLS Fwd_GETX 0 <--
-IFLS Fwd_GETS 0 <--
-IFLS Fwd_DMA 0 <--
-IFLS Inv 0 <--
-IFLS Unblock 0 <--
-IFLS L2_Replacement 0 <--
-
-IFLO L1_GETS 0 <--
-IFLO L1_GETX 0 <--
-IFLO L1_PUTO 0 <--
-IFLO L1_PUTX 0 <--
-IFLO L1_PUTS_only 0 <--
-IFLO L1_PUTS 0 <--
-IFLO Fwd_GETX 0 <--
-IFLO Fwd_GETS 0 <--
-IFLO Fwd_DMA 0 <--
-IFLO Inv 0 <--
-IFLO Unblock 0 <--
-IFLO L2_Replacement 0 <--
-
-IFLOX L1_GETS 0 <--
-IFLOX L1_GETX 0 <--
-IFLOX L1_PUTO 0 <--
-IFLOX L1_PUTX 0 <--
-IFLOX L1_PUTS_only 0 <--
-IFLOX L1_PUTS 0 <--
-IFLOX Fwd_GETX 0 <--
-IFLOX Fwd_GETS 0 <--
-IFLOX Fwd_DMA 0 <--
-IFLOX Inv 0 <--
-IFLOX Unblock 0 <--
-IFLOX Exclusive_Unblock 0 <--
-IFLOX L2_Replacement 0 <--
-
-IFLOXX L1_GETS 0 <--
-IFLOXX L1_GETX 0 <--
-IFLOXX L1_PUTO 0 <--
-IFLOXX L1_PUTX 0 <--
-IFLOXX L1_PUTS_only 0 <--
-IFLOXX L1_PUTS 0 <--
-IFLOXX Fwd_GETX 0 <--
-IFLOXX Fwd_GETS 0 <--
-IFLOXX Fwd_DMA 0 <--
-IFLOXX Inv 0 <--
-IFLOXX Unblock 0 <--
-IFLOXX Exclusive_Unblock 0 <--
-IFLOXX L2_Replacement 0 <--
-
-IFLOSX L1_GETS 0 <--
-IFLOSX L1_GETX 0 <--
-IFLOSX L1_PUTO 0 <--
-IFLOSX L1_PUTX 0 <--
-IFLOSX L1_PUTS_only 0 <--
-IFLOSX L1_PUTS 0 <--
-IFLOSX Fwd_GETX 0 <--
-IFLOSX Fwd_GETS 0 <--
-IFLOSX Fwd_DMA 0 <--
-IFLOSX Inv 0 <--
-IFLOSX Unblock 0 <--
-IFLOSX Exclusive_Unblock 0 <--
-IFLOSX L2_Replacement 0 <--
-
-IFLXO L1_GETS 0 <--
-IFLXO L1_GETX 0 <--
-IFLXO L1_PUTO 0 <--
-IFLXO L1_PUTX 0 <--
-IFLXO L1_PUTS_only 0 <--
-IFLXO L1_PUTS 0 <--
-IFLXO Fwd_GETX 0 <--
-IFLXO Fwd_GETS 0 <--
-IFLXO Fwd_DMA 0 <--
-IFLXO Inv 0 <--
-IFLXO Exclusive_Unblock 0 <--
-IFLXO L2_Replacement 0 <--
-
-IGS L1_GETS 0 <--
-IGS L1_GETX 0 <--
-IGS L1_PUTO 0 <--
-IGS L1_PUTX 0 <--
-IGS L1_PUTS_only 0 <--
-IGS L1_PUTS 0 <--
-IGS Fwd_GETX 0 <--
-IGS Fwd_GETS 0 <--
-IGS Fwd_DMA 0 <--
-IGS Own_GETX 0 <--
-IGS Inv 0 <--
-IGS Data 0 <--
-IGS Data_Exclusive 991
-IGS Unblock 0 <--
-IGS Exclusive_Unblock 991
-IGS L2_Replacement 0 <--
-
-IGM L1_GETS 0 <--
-IGM L1_GETX 0 <--
-IGM L1_PUTO 0 <--
-IGM L1_PUTX 0 <--
-IGM L1_PUTS_only 0 <--
-IGM L1_PUTS 0 <--
-IGM Fwd_GETX 0 <--
-IGM Fwd_GETS 0 <--
-IGM Fwd_DMA 0 <--
-IGM Own_GETX 0 <--
-IGM Inv 0 <--
-IGM ExtAck 0 <--
-IGM Data 506
-IGM Data_Exclusive 0 <--
-IGM L2_Replacement 0 <--
-
-IGMLS L1_GETS 0 <--
-IGMLS L1_GETX 0 <--
-IGMLS L1_PUTO 0 <--
-IGMLS L1_PUTX 0 <--
-IGMLS L1_PUTS_only 0 <--
-IGMLS L1_PUTS 0 <--
-IGMLS Inv 0 <--
-IGMLS IntAck 0 <--
-IGMLS ExtAck 0 <--
-IGMLS All_Acks 0 <--
-IGMLS Data 0 <--
-IGMLS Data_Exclusive 0 <--
-IGMLS L2_Replacement 0 <--
-
-IGMO L1_GETS 0 <--
-IGMO L1_GETX 0 <--
-IGMO L1_PUTO 0 <--
-IGMO L1_PUTX 0 <--
-IGMO L1_PUTS_only 0 <--
-IGMO L1_PUTS 0 <--
-IGMO Fwd_GETX 0 <--
-IGMO Fwd_GETS 0 <--
-IGMO Fwd_DMA 0 <--
-IGMO Own_GETX 0 <--
-IGMO ExtAck 0 <--
-IGMO All_Acks 506
-IGMO Exclusive_Unblock 506
-IGMO L2_Replacement 0 <--
-
-IGMIO L1_GETS 0 <--
-IGMIO L1_GETX 0 <--
-IGMIO L1_PUTO 0 <--
-IGMIO L1_PUTX 0 <--
-IGMIO L1_PUTS_only 0 <--
-IGMIO L1_PUTS 0 <--
-IGMIO Fwd_GETX 0 <--
-IGMIO Fwd_GETS 0 <--
-IGMIO Fwd_DMA 0 <--
-IGMIO Own_GETX 0 <--
-IGMIO ExtAck 0 <--
-IGMIO All_Acks 0 <--
-
-OGMIO L1_GETS 0 <--
-OGMIO L1_GETX 0 <--
-OGMIO L1_PUTO 0 <--
-OGMIO L1_PUTX 0 <--
-OGMIO L1_PUTS_only 0 <--
-OGMIO L1_PUTS 0 <--
-OGMIO Fwd_GETX 0 <--
-OGMIO Fwd_GETS 0 <--
-OGMIO Fwd_DMA 0 <--
-OGMIO Own_GETX 0 <--
-OGMIO ExtAck 0 <--
-OGMIO All_Acks 0 <--
-
-IGMIOF L1_GETS 0 <--
-IGMIOF L1_GETX 0 <--
-IGMIOF L1_PUTO 0 <--
-IGMIOF L1_PUTX 0 <--
-IGMIOF L1_PUTS_only 0 <--
-IGMIOF L1_PUTS 0 <--
-IGMIOF IntAck 0 <--
-IGMIOF All_Acks 0 <--
-IGMIOF Data_Exclusive 0 <--
-
-IGMIOFS L1_GETS 0 <--
-IGMIOFS L1_GETX 0 <--
-IGMIOFS L1_PUTO 0 <--
-IGMIOFS L1_PUTX 0 <--
-IGMIOFS L1_PUTS_only 0 <--
-IGMIOFS L1_PUTS 0 <--
-IGMIOFS Fwd_GETX 0 <--
-IGMIOFS Fwd_GETS 0 <--
-IGMIOFS Fwd_DMA 0 <--
-IGMIOFS Inv 0 <--
-IGMIOFS Data 0 <--
-IGMIOFS L2_Replacement 0 <--
-
-OGMIOF L1_GETS 0 <--
-OGMIOF L1_GETX 0 <--
-OGMIOF L1_PUTO 0 <--
-OGMIOF L1_PUTX 0 <--
-OGMIOF L1_PUTS_only 0 <--
-OGMIOF L1_PUTS 0 <--
-OGMIOF IntAck 0 <--
-OGMIOF All_Acks 0 <--
-
-II L1_GETS 0 <--
-II L1_GETX 0 <--
-II L1_PUTO 0 <--
-II L1_PUTX 0 <--
-II L1_PUTS_only 0 <--
-II L1_PUTS 0 <--
-II IntAck 0 <--
-II All_Acks 0 <--
-
-MM L1_GETS 0 <--
-MM L1_GETX 0 <--
-MM L1_PUTO 0 <--
-MM L1_PUTX 0 <--
-MM L1_PUTS_only 0 <--
-MM L1_PUTS 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-MM Inv 0 <--
-MM Exclusive_Unblock 125831
-MM L2_Replacement 0 <--
-
-SS L1_GETS 0 <--
-SS L1_GETX 0 <--
-SS L1_PUTO 0 <--
-SS L1_PUTX 0 <--
-SS L1_PUTS_only 0 <--
-SS L1_PUTS 0 <--
-SS Fwd_GETX 0 <--
-SS Fwd_GETS 0 <--
-SS Fwd_DMA 0 <--
-SS Inv 0 <--
-SS Unblock 0 <--
-SS L2_Replacement 0 <--
-
-OO L1_GETS 0 <--
-OO L1_GETX 0 <--
-OO L1_PUTO 0 <--
-OO L1_PUTX 0 <--
-OO L1_PUTS_only 0 <--
-OO L1_PUTS 0 <--
-OO Fwd_GETX 0 <--
-OO Fwd_GETS 0 <--
-OO Fwd_DMA 0 <--
-OO Inv 0 <--
-OO Unblock 0 <--
-OO Exclusive_Unblock 233415
-OO L2_Replacement 0 <--
-
-OLSS L1_GETS 0 <--
-OLSS L1_GETX 0 <--
-OLSS L1_PUTO 0 <--
-OLSS L1_PUTX 0 <--
-OLSS L1_PUTS_only 0 <--
-OLSS L1_PUTS 0 <--
-OLSS Fwd_GETX 0 <--
-OLSS Fwd_GETS 0 <--
-OLSS Fwd_DMA 0 <--
-OLSS Inv 0 <--
-OLSS Unblock 0 <--
-OLSS L2_Replacement 0 <--
-
-OLSXS L1_GETS 0 <--
-OLSXS L1_GETX 0 <--
-OLSXS L1_PUTO 0 <--
-OLSXS L1_PUTX 0 <--
-OLSXS L1_PUTS_only 0 <--
-OLSXS L1_PUTS 0 <--
-OLSXS Fwd_GETX 0 <--
-OLSXS Fwd_GETS 0 <--
-OLSXS Fwd_DMA 0 <--
-OLSXS Inv 0 <--
-OLSXS Unblock 0 <--
-OLSXS L2_Replacement 0 <--
-
-SLSS L1_GETS 0 <--
-SLSS L1_GETX 0 <--
-SLSS L1_PUTO 0 <--
-SLSS L1_PUTX 0 <--
-SLSS L1_PUTS_only 0 <--
-SLSS L1_PUTS 0 <--
-SLSS Fwd_GETX 0 <--
-SLSS Fwd_GETS 0 <--
-SLSS Fwd_DMA 0 <--
-SLSS Inv 0 <--
-SLSS Unblock 0 <--
-SLSS L2_Replacement 0 <--
-
-OI L1_GETS 0 <--
-OI L1_GETX 0 <--
-OI L1_PUTO 0 <--
-OI L1_PUTX 0 <--
-OI L1_PUTS_only 0 <--
-OI L1_PUTS 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Nack 0 <--
-OI L2_Replacement 0 <--
-
-MI L1_GETS 0 <--
-MI L1_GETX 0 <--
-MI L1_PUTO 0 <--
-MI L1_PUTX 0 <--
-MI L1_PUTS_only 0 <--
-MI L1_PUTS 0 <--
-MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
-MI Writeback_Ack 0 <--
-MI L2_Replacement 0 <--
-
-MII L1_GETS 0 <--
-MII L1_GETX 0 <--
-MII L1_PUTO 0 <--
-MII L1_PUTX 0 <--
-MII L1_PUTS_only 0 <--
-MII L1_PUTS 0 <--
-MII Writeback_Ack 0 <--
-MII Writeback_Nack 0 <--
-MII L2_Replacement 0 <--
-
-OLSI L1_GETS 0 <--
-OLSI L1_GETX 0 <--
-OLSI L1_PUTO 0 <--
-OLSI L1_PUTX 0 <--
-OLSI L1_PUTS_only 0 <--
-OLSI L1_PUTS 0 <--
-OLSI Fwd_GETX 0 <--
-OLSI Fwd_GETS 0 <--
-OLSI Fwd_DMA 0 <--
-OLSI Writeback_Ack 0 <--
-OLSI L2_Replacement 0 <--
-
-ILSI L1_GETS 0 <--
-ILSI L1_GETX 0 <--
-ILSI L1_PUTO 0 <--
-ILSI L1_PUTX 0 <--
-ILSI L1_PUTS_only 0 <--
-ILSI L1_PUTS 0 <--
-ILSI IntAck 0 <--
-ILSI All_Acks 0 <--
-ILSI Writeback_Ack 0 <--
-ILSI L2_Replacement 0 <--
+I GETX 2
+I PUTX_NotOwner 0 <--
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+M GETX 1226979
+M PUTX 0 <--
+M PUTX_NotOwner 0 <--
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+
+M_DRD GETX 0 <--
+M_DRD PUTX 0 <--
+
+M_DWR GETX 0 <--
+M_DWR PUTX 0 <--
+
+M_DWRI GETX 0 <--
+M_DWRI Memory_Ack 0 <--
+
+M_DRDI GETX 0 <--
+M_DRDI Memory_Ack 0 <--
+
+IM GETX 411
+IM GETS 0 <--
+IM PUTX 0 <--
+IM PUTX_NotOwner 0 <--
+IM DMA_READ 0 <--
+IM DMA_WRITE 0 <--
+IM Memory_Data 2
+
+MI GETX 0 <--
+MI GETS 0 <--
+MI PUTX 0 <--
+MI PUTX_NotOwner 0 <--
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+MI Memory_Ack 0 <--
+
+ID GETX 0 <--
+ID GETS 0 <--
+ID PUTX 0 <--
+ID PUTX_NotOwner 0 <--
+ID DMA_READ 0 <--
+ID DMA_WRITE 0 <--
+ID Memory_Data 0 <--
+
+ID_W GETX 0 <--
+ID_W GETS 0 <--
+ID_W PUTX 0 <--
+ID_W PUTX_NotOwner 0 <--
+ID_W DMA_READ 0 <--
+ID_W DMA_WRITE 0 <--
+ID_W Memory_Ack 0 <--
-["-c", "MOESI_CMP_directory", "-r", "tests/configs/../../src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb", "-p", "8", "-m", "1", "-s", "1024", "-C", "32768", "-A", "8", "-D", "1"]
-system.cpu0: completed 10000 read accesses @449430
-system.cpu4: completed 10000 read accesses @459465
-system.cpu7: completed 10000 read accesses @472231
-system.cpu1: completed 10000 read accesses @477652
-system.cpu2: completed 10000 read accesses @477942
-system.cpu5: completed 10000 read accesses @490692
-system.cpu6: completed 10000 read accesses @490860
-system.cpu3: completed 10000 read accesses @498830
-system.cpu0: completed 20000 read accesses @902454
-system.cpu4: completed 20000 read accesses @921903
-system.cpu7: completed 20000 read accesses @943132
-system.cpu2: completed 20000 read accesses @963224
-system.cpu1: completed 20000 read accesses @974292
-system.cpu5: completed 20000 read accesses @979817
-system.cpu6: completed 20000 read accesses @985156
-system.cpu3: completed 20000 read accesses @1004197
-system.cpu0: completed 30000 read accesses @1354388
-system.cpu4: completed 30000 read accesses @1389321
-system.cpu7: completed 30000 read accesses @1410714
-system.cpu2: completed 30000 read accesses @1450104
-system.cpu5: completed 30000 read accesses @1465068
-system.cpu1: completed 30000 read accesses @1470940
-system.cpu6: completed 30000 read accesses @1477854
-system.cpu3: completed 30000 read accesses @1508078
-system.cpu0: completed 40000 read accesses @1811799
-system.cpu4: completed 40000 read accesses @1844299
-system.cpu7: completed 40000 read accesses @1889814
-system.cpu2: completed 40000 read accesses @1927073
-system.cpu1: completed 40000 read accesses @1953874
-system.cpu5: completed 40000 read accesses @1957168
-system.cpu6: completed 40000 read accesses @1970748
-system.cpu3: completed 40000 read accesses @2016002
-system.cpu0: completed 50000 read accesses @2262162
-system.cpu4: completed 50000 read accesses @2303172
-system.cpu7: completed 50000 read accesses @2354840
-system.cpu2: completed 50000 read accesses @2408362
-system.cpu1: completed 50000 read accesses @2441228
-system.cpu5: completed 50000 read accesses @2451414
-system.cpu6: completed 50000 read accesses @2467657
-system.cpu3: completed 50000 read accesses @2528058
-system.cpu0: completed 60000 read accesses @2711396
-system.cpu4: completed 60000 read accesses @2767668
-system.cpu7: completed 60000 read accesses @2817212
-system.cpu2: completed 60000 read accesses @2897042
-system.cpu1: completed 60000 read accesses @2926178
-system.cpu5: completed 60000 read accesses @2935676
-system.cpu6: completed 60000 read accesses @2963110
-system.cpu3: completed 60000 read accesses @3030360
-system.cpu0: completed 70000 read accesses @3162444
-system.cpu4: completed 70000 read accesses @3222154
-system.cpu7: completed 70000 read accesses @3277574
-system.cpu2: completed 70000 read accesses @3381865
-system.cpu1: completed 70000 read accesses @3415612
-system.cpu5: completed 70000 read accesses @3416504
-system.cpu6: completed 70000 read accesses @3460152
-system.cpu3: completed 70000 read accesses @3529552
-system.cpu0: completed 80000 read accesses @3611998
-system.cpu4: completed 80000 read accesses @3676108
-system.cpu7: completed 80000 read accesses @3736694
-system.cpu2: completed 80000 read accesses @3853296
-system.cpu5: completed 80000 read accesses @3905416
-system.cpu1: completed 80000 read accesses @3907045
-system.cpu6: completed 80000 read accesses @3947118
-system.cpu3: completed 80000 read accesses @4038186
-system.cpu0: completed 90000 read accesses @4055478
-system.cpu4: completed 90000 read accesses @4135882
-system.cpu7: completed 90000 read accesses @4192986
-system.cpu2: completed 90000 read accesses @4335194
-system.cpu5: completed 90000 read accesses @4388557
-system.cpu1: completed 90000 read accesses @4398614
-system.cpu6: completed 90000 read accesses @4430678
-system.cpu0: completed 100000 read accesses @4504972
+system.cpu0: completed 10000 read accesses @1103968
+system.cpu6: completed 10000 read accesses @1104382
+system.cpu5: completed 10000 read accesses @1104796
+system.cpu1: completed 10000 read accesses @1105498
+system.cpu2: completed 10000 read accesses @1106632
+system.cpu4: completed 10000 read accesses @1107712
+system.cpu7: completed 10000 read accesses @1111366
+system.cpu3: completed 10000 read accesses @1114786
+system.cpu6: completed 20000 read accesses @2206702
+system.cpu5: completed 20000 read accesses @2207332
+system.cpu4: completed 20000 read accesses @2213344
+system.cpu0: completed 20000 read accesses @2215108
+system.cpu3: completed 20000 read accesses @2216458
+system.cpu2: completed 20000 read accesses @2216584
+system.cpu1: completed 20000 read accesses @2217286
+system.cpu7: completed 20000 read accesses @2221534
+system.cpu6: completed 30000 read accesses @3313342
+system.cpu0: completed 30000 read accesses @3313972
+system.cpu2: completed 30000 read accesses @3321065
+system.cpu4: completed 30000 read accesses @3321964
+system.cpu5: completed 30000 read accesses @3324628
+system.cpu1: completed 30000 read accesses @3325258
+system.cpu3: completed 30000 read accesses @3325906
+system.cpu7: completed 30000 read accesses @3327526
+system.cpu0: completed 40000 read accesses @4414996
+system.cpu6: completed 40000 read accesses @4419838
+system.cpu4: completed 40000 read accesses @4423312
+system.cpu7: completed 40000 read accesses @4424446
+system.cpu3: completed 40000 read accesses @4428010
+system.cpu1: completed 40000 read accesses @4433050
+system.cpu2: completed 40000 read accesses @4433464
+system.cpu5: completed 40000 read accesses @4434796
+system.cpu0: completed 50000 read accesses @5511988
+system.cpu6: completed 50000 read accesses @5524786
+system.cpu3: completed 50000 read accesses @5528242
+system.cpu4: completed 50000 read accesses @5531104
+system.cpu5: completed 50000 read accesses @5534092
+system.cpu7: completed 50000 read accesses @5544478
+system.cpu2: completed 50000 read accesses @5545289
+system.cpu1: completed 50000 read accesses @5546278
+system.cpu0: completed 60000 read accesses @6613264
+system.cpu3: completed 60000 read accesses @6629122
+system.cpu5: completed 60000 read accesses @6630580
+system.cpu6: completed 60000 read accesses @6640498
+system.cpu4: completed 60000 read accesses @6648076
+system.cpu7: completed 60000 read accesses @6652270
+system.cpu2: completed 60000 read accesses @6660281
+system.cpu1: completed 60000 read accesses @6663286
+system.cpu0: completed 70000 read accesses @7721632
+system.cpu3: completed 70000 read accesses @7733602
+system.cpu6: completed 70000 read accesses @7744546
+system.cpu4: completed 70000 read accesses @7745248
+system.cpu5: completed 70000 read accesses @7745356
+system.cpu2: completed 70000 read accesses @7765913
+system.cpu1: completed 70000 read accesses @7768378
+system.cpu7: completed 70000 read accesses @7769926
+system.cpu0: completed 80000 read accesses @8821828
+system.cpu5: completed 80000 read accesses @8845300
+system.cpu3: completed 80000 read accesses @8848018
+system.cpu6: completed 80000 read accesses @8850754
+system.cpu4: completed 80000 read accesses @8854012
+system.cpu7: completed 80000 read accesses @8871886
+system.cpu1: completed 80000 read accesses @8880202
+system.cpu2: completed 80000 read accesses @8886377
+system.cpu0: completed 90000 read accesses @9929332
+system.cpu5: completed 90000 read accesses @9945316
+system.cpu3: completed 90000 read accesses @9955306
+system.cpu6: completed 90000 read accesses @9959554
+system.cpu4: completed 90000 read accesses @9962668
+system.cpu7: completed 90000 read accesses @9977536
+system.cpu1: completed 90000 read accesses @9979354
+system.cpu2: completed 90000 read accesses @10002520
+system.cpu0: completed 100000 read accesses @11043028
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Jan 19 2010 17:11:57
-M5 revision 21fbf0412e0d 6840 default tip
-M5 started Jan 19 2010 17:12:00
-M5 executing on bluedevil.cs.wisc.edu
+M5 compiled Jan 27 2010 22:23:20
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 11:09:16
+M5 executing on svvint07
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
-Global frequency set at 1000000000000 ticks per second
+Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 4504972 because maximum number of loads reached
+Exiting @ tick 11043028 because maximum number of loads reached
---------- Begin Simulation Statistics ----------
-host_mem_usage 1414304 # Number of bytes of host memory used
-host_seconds 219.48 # Real time elapsed on the host
-host_tick_rate 20525 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_seconds 0.000005 # Number of seconds simulated
-sim_ticks 4504972 # Number of ticks simulated
+host_mem_usage 344584 # Number of bytes of host memory used
+host_seconds 85.64 # Real time elapsed on the host
+host_tick_rate 128940 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.011043 # Number of seconds simulated
+sim_ticks 11043028 # Number of ticks simulated
system.cpu0.num_copies 0 # number of copy accesses completed
system.cpu0.num_reads 100000 # number of read accesses completed
-system.cpu0.num_writes 54115 # number of write accesses completed
+system.cpu0.num_writes 53371 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 92132 # number of read accesses completed
-system.cpu1.num_writes 49991 # number of write accesses completed
+system.cpu1.num_reads 99516 # number of read accesses completed
+system.cpu1.num_writes 53857 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 93521 # number of read accesses completed
-system.cpu2.num_writes 50418 # number of write accesses completed
+system.cpu2.num_reads 99479 # number of read accesses completed
+system.cpu2.num_writes 53903 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 89205 # number of read accesses completed
-system.cpu3.num_writes 48106 # number of write accesses completed
+system.cpu3.num_reads 99825 # number of read accesses completed
+system.cpu3.num_writes 53546 # number of write accesses completed
system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 97961 # number of read accesses completed
-system.cpu4.num_writes 52598 # number of write accesses completed
+system.cpu4.num_reads 99698 # number of read accesses completed
+system.cpu4.num_writes 53673 # number of write accesses completed
system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 92452 # number of read accesses completed
-system.cpu5.num_writes 49744 # number of write accesses completed
+system.cpu5.num_reads 99797 # number of read accesses completed
+system.cpu5.num_writes 53574 # number of write accesses completed
system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 91570 # number of read accesses completed
-system.cpu6.num_writes 49935 # number of write accesses completed
+system.cpu6.num_reads 99782 # number of read accesses completed
+system.cpu6.num_writes 53589 # number of write accesses completed
system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 96862 # number of read accesses completed
-system.cpu7.num_writes 51935 # number of write accesses completed
+system.cpu7.num_reads 99603 # number of read accesses completed
+system.cpu7.num_writes 53767 # number of write accesses completed
---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=true
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+num_int_nodes=4
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=root.cpuPort[0]
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+buffer_size=0
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+recycle_latency=10
+to_l1_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links2.ext_node.directory
+directory_latency=6
+memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+to_mem_ctrl_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=3
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 1
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/27/2010 22:07:37
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 2
+Elapsed_time_in_minutes: 0.0333333
+Elapsed_time_in_hours: 0.000555556
+Elapsed_time_in_days: 2.31481e-05
+
+Virtual_time_in_seconds: 1.4
+Virtual_time_in_minutes: 0.0233333
+Virtual_time_in_hours: 0.000388889
+Virtual_time_in_days: 1.62037e-05
+
+Ruby_current_time: 357031
+Ruby_start_time: 0
+Ruby_cycles: 357031
+
+mbytes_resident: 31.0938
+mbytes_total: 31.1016
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 357032 [ 357032 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 970 average: 15.8278 | standard deviation: 1.13986 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 48 908 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 256 max: 34787 count: 954 average: 5860.09 | standard deviation: 7881.77 | 94 12 70 81 75 77 58 51 39 26 24 21 14 6 9 8 5 4 5 6 9 4 5 3 5 4 2 1 1 5 1 2 1 0 0 1 1 1 1 0 0 2 3 5 3 1 1 1 2 2 2 1 5 1 4 6 2 2 5 8 1 6 6 4 2 3 8 3 1 3 5 8 3 5 4 1 5 6 6 4 6 3 6 2 3 5 2 1 3 1 4 2 1 1 4 2 2 2 3 3 1 2 4 3 0 1 0 2 3 0 1 0 1 0 1 1 0 0 1 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 256 max: 26521 count: 100 average: 5073.78 | standard deviation: 7357.14 | 10 1 5 11 11 3 3 4 7 6 6 4 3 0 1 0 2 1 0 2 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 256 max: 34787 count: 854 average: 5952.16 | standard deviation: 7939.9 | 84 11 65 70 64 74 55 47 32 20 18 17 11 6 8 8 3 3 5 4 9 4 5 3 3 4 2 1 1 5 1 2 1 0 0 1 1 1 1 0 0 1 3 5 3 1 1 1 2 2 2 1 5 1 3 5 2 1 5 8 1 5 6 4 2 3 8 3 1 2 5 8 2 5 4 0 5 5 6 4 6 1 6 2 2 4 2 1 3 1 4 2 1 1 3 2 2 2 2 3 1 1 3 2 0 1 0 2 3 0 1 0 1 0 1 1 0 0 1 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 32 max: 1590 count: 6452 average: 19.6141 | standard deviation: 106.746 | 6116 4 30 74 2 5 34 6 4 19 14 1 15 14 3 9 18 2 3 14 16 2 6 11 2 0 7 5 1 2 2 0 0 3 0 2 0 0 0 1 0 0 4 0 0 0 0 0 0 1 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 3918 average: 0 | standard deviation: 0 | 3918 ]
+ virtual_network_0_delay_cycles: [binsize: 32 max: 1590 count: 2534 average: 49.9408 | standard deviation: 165.845 | 2198 4 30 74 2 5 34 6 4 19 14 1 15 14 3 9 18 2 3 14 16 2 6 11 2 0 7 5 1 2 2 0 0 3 0 2 0 0 0 1 0 0 4 0 0 0 0 0 0 1 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 531 average: 0 | standard deviation: 0 | 531 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3387 average: 0 | standard deviation: 0 | 3387 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 1
+system_time: 0
+page_reclaims: 6770
+page_faults: 1936
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.106988
+ links_utilized_percent_switch_0_link_0: 0.0301689 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.183808 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Request_Control: 531 4248 [ 531 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 862 62064 [ 0 862 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 328 2624 [ 0 328 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 863 6904 [ 863 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Control: 866 6928 [ 0 4 862 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 1257 90504 [ 730 527 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 83 664 [ 83 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.151261
+ links_utilized_percent_switch_1_link_0: 0.0751615 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.227361 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Control: 862 6896 [ 862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 835 60120 [ 0 835 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Control: 1695 13560 [ 0 835 860 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 1257 90504 [ 730 527 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 83 664 [ 83 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Control: 835 6680 [ 835 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 531 4248 [ 531 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 1606 115632 [ 0 1606 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 415 3320 [ 0 415 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.071776
+ links_utilized_percent_switch_2_link_0: 0.0266714 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.116881 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 835 6680 [ 835 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Data: 744 53568 [ 0 744 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 835 60120 [ 0 835 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Control: 831 6648 [ 0 831 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 3
+switch_3_outlinks: 3
+links_utilized_percent_switch_3: 0.176007
+ links_utilized_percent_switch_3_link_0: 0.120676 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.30066 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.106685 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Request_Control: 531 4248 [ 531 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Data: 862 62064 [ 0 862 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 328 2624 [ 0 328 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Control: 863 6904 [ 863 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 835 60120 [ 0 835 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Control: 1695 13560 [ 0 835 860 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 1257 90504 [ 730 527 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Control: 83 664 [ 83 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Control: 835 6680 [ 835 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Response_Data: 744 53568 [ 0 744 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 100
+Ifetch 0
+Store 856
+Inv 531
+L1_Replacement 507964
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_GET_INSTR 0
+Data 0
+Data_Exclusive 90
+DataS_fromL1 0
+Data_all_Acks 772
+Ack 0
+Ack_all 0
+WB_Ack 328
+
+ - Transitions -
+NP Load 90
+NP Ifetch 0 <--
+NP Store 774
+NP Inv 0 <--
+NP L1_Replacement 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I Inv 0 <--
+I L1_Replacement 46
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S Inv 0 <--
+S L1_Replacement 0 <--
+
+E Load 0 <--
+E Ifetch 0 <--
+E Store 1
+E Inv 4
+E L1_Replacement 85
+E Fwd_GETX 0 <--
+E Fwd_GETS 0 <--
+E Fwd_GET_INSTR 0 <--
+
+M Load 10
+M Ifetch 0 <--
+M Store 81
+M Inv 42
+M L1_Replacement 730
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_GET_INSTR 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS Inv 0 <--
+IS L1_Replacement 54611
+IS Data_Exclusive 90
+IS DataS_fromL1 0 <--
+IS Data_all_Acks 0 <--
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM Inv 0 <--
+IM L1_Replacement 452492
+IM Data 0 <--
+IM Data_all_Acks 772
+IM Ack 0 <--
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM Inv 0 <--
+SM L1_Replacement 0 <--
+SM Ack 0 <--
+SM Ack_all 0 <--
+
+IS_I Load 0 <--
+IS_I Ifetch 0 <--
+IS_I Store 0 <--
+IS_I Inv 0 <--
+IS_I L1_Replacement 0 <--
+IS_I Data_Exclusive 0 <--
+IS_I DataS_fromL1 0 <--
+IS_I Data_all_Acks 0 <--
+
+M_I Load 0 <--
+M_I Ifetch 0 <--
+M_I Store 0 <--
+M_I Inv 485
+M_I L1_Replacement 0 <--
+M_I Fwd_GETX 0 <--
+M_I Fwd_GETS 0 <--
+M_I Fwd_GET_INSTR 0 <--
+M_I WB_Ack 328
+
+E_I Load 0 <--
+E_I Ifetch 0 <--
+E_I Store 0 <--
+E_I L1_Replacement 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GET_INSTR 0
+L1_GETS 102
+L1_GETX 773
+L1_UPGRADE 0
+L1_PUTX 513
+L1_PUTX_old 484
+Fwd_L1_GETX 0
+Fwd_L1_GETS 0
+Fwd_L1_GET_INSTR 0
+L2_Replacement 259
+L2_Replacement_clean 13081
+Mem_Data 835
+Mem_Ack 831
+WB_Data 485
+WB_Data_clean 42
+Ack 0
+Ack_all 4
+Unblock 0
+Unblock_Cancel 0
+Exclusive_Unblock 860
+MEM_Inv 0
+
+ - Transitions -
+NP L1_GET_INSTR 0 <--
+NP L1_GETS 89
+NP L1_GETX 746
+NP L1_PUTX 0 <--
+NP L1_PUTX_old 104
+
+SS L1_GET_INSTR 0 <--
+SS L1_GETS 0 <--
+SS L1_GETX 0 <--
+SS L1_UPGRADE 0 <--
+SS L1_PUTX 0 <--
+SS L1_PUTX_old 0 <--
+SS L2_Replacement 0 <--
+SS L2_Replacement_clean 0 <--
+SS MEM_Inv 0 <--
+
+M L1_GET_INSTR 0 <--
+M L1_GETS 1
+M L1_GETX 26
+M L1_PUTX 0 <--
+M L1_PUTX_old 0 <--
+M L2_Replacement 259
+M L2_Replacement_clean 41
+M MEM_Inv 0 <--
+
+MT L1_GET_INSTR 0 <--
+MT L1_GETS 0 <--
+MT L1_GETX 0 <--
+MT L1_PUTX 328
+MT L1_PUTX_old 0 <--
+MT L2_Replacement 0 <--
+MT L2_Replacement_clean 531
+MT MEM_Inv 0 <--
+
+M_I L1_GET_INSTR 0 <--
+M_I L1_GETS 12
+M_I L1_GETX 1
+M_I L1_UPGRADE 0 <--
+M_I L1_PUTX 0 <--
+M_I L1_PUTX_old 107
+M_I Mem_Ack 831
+M_I MEM_Inv 0 <--
+
+MT_I L1_GET_INSTR 0 <--
+MT_I L1_GETS 0 <--
+MT_I L1_GETX 0 <--
+MT_I L1_UPGRADE 0 <--
+MT_I L1_PUTX 0 <--
+MT_I L1_PUTX_old 0 <--
+MT_I WB_Data 0 <--
+MT_I WB_Data_clean 0 <--
+MT_I Ack_all 0 <--
+MT_I MEM_Inv 0 <--
+
+MCT_I L1_GET_INSTR 0 <--
+MCT_I L1_GETS 0 <--
+MCT_I L1_GETX 0 <--
+MCT_I L1_UPGRADE 0 <--
+MCT_I L1_PUTX 0 <--
+MCT_I L1_PUTX_old 135
+MCT_I WB_Data 485
+MCT_I WB_Data_clean 42
+MCT_I Ack_all 4
+
+I_I L1_GET_INSTR 0 <--
+I_I L1_GETS 0 <--
+I_I L1_GETX 0 <--
+I_I L1_UPGRADE 0 <--
+I_I L1_PUTX 0 <--
+I_I L1_PUTX_old 0 <--
+I_I Ack 0 <--
+I_I Ack_all 0 <--
+
+S_I L1_GET_INSTR 0 <--
+S_I L1_GETS 0 <--
+S_I L1_GETX 0 <--
+S_I L1_UPGRADE 0 <--
+S_I L1_PUTX 0 <--
+S_I L1_PUTX_old 0 <--
+S_I Ack 0 <--
+S_I Ack_all 0 <--
+S_I MEM_Inv 0 <--
+
+ISS L1_GET_INSTR 0 <--
+ISS L1_GETS 0 <--
+ISS L1_GETX 0 <--
+ISS L1_PUTX 0 <--
+ISS L1_PUTX_old 0 <--
+ISS L2_Replacement 0 <--
+ISS L2_Replacement_clean 708
+ISS Mem_Data 89
+ISS MEM_Inv 0 <--
+
+IS L1_GET_INSTR 0 <--
+IS L1_GETS 0 <--
+IS L1_GETX 0 <--
+IS L1_PUTX 0 <--
+IS L1_PUTX_old 0 <--
+IS L2_Replacement 0 <--
+IS L2_Replacement_clean 0 <--
+IS Mem_Data 0 <--
+IS MEM_Inv 0 <--
+
+IM L1_GET_INSTR 0 <--
+IM L1_GETS 0 <--
+IM L1_GETX 0 <--
+IM L1_PUTX 0 <--
+IM L1_PUTX_old 0 <--
+IM L2_Replacement 0 <--
+IM L2_Replacement_clean 4762
+IM Mem_Data 746
+IM MEM_Inv 0 <--
+
+SS_MB L1_GET_INSTR 0 <--
+SS_MB L1_GETS 0 <--
+SS_MB L1_GETX 0 <--
+SS_MB L1_UPGRADE 0 <--
+SS_MB L1_PUTX 0 <--
+SS_MB L1_PUTX_old 0 <--
+SS_MB L2_Replacement 0 <--
+SS_MB L2_Replacement_clean 0 <--
+SS_MB Unblock_Cancel 0 <--
+SS_MB Exclusive_Unblock 0 <--
+SS_MB MEM_Inv 0 <--
+
+MT_MB L1_GET_INSTR 0 <--
+MT_MB L1_GETS 0 <--
+MT_MB L1_GETX 0 <--
+MT_MB L1_UPGRADE 0 <--
+MT_MB L1_PUTX 185
+MT_MB L1_PUTX_old 138
+MT_MB L2_Replacement 0 <--
+MT_MB L2_Replacement_clean 7039
+MT_MB Unblock_Cancel 0 <--
+MT_MB Exclusive_Unblock 860
+MT_MB MEM_Inv 0 <--
+
+M_MB L1_GET_INSTR 0 <--
+M_MB L1_GETS 0 <--
+M_MB L1_GETX 0 <--
+M_MB L1_UPGRADE 0 <--
+M_MB L1_PUTX 0 <--
+M_MB L1_PUTX_old 0 <--
+M_MB L2_Replacement 0 <--
+M_MB L2_Replacement_clean 0 <--
+M_MB Exclusive_Unblock 0 <--
+M_MB MEM_Inv 0 <--
+
+MT_IIB L1_GET_INSTR 0 <--
+MT_IIB L1_GETS 0 <--
+MT_IIB L1_GETX 0 <--
+MT_IIB L1_UPGRADE 0 <--
+MT_IIB L1_PUTX 0 <--
+MT_IIB L1_PUTX_old 0 <--
+MT_IIB L2_Replacement 0 <--
+MT_IIB L2_Replacement_clean 0 <--
+MT_IIB WB_Data 0 <--
+MT_IIB WB_Data_clean 0 <--
+MT_IIB Unblock 0 <--
+MT_IIB MEM_Inv 0 <--
+
+MT_IB L1_GET_INSTR 0 <--
+MT_IB L1_GETS 0 <--
+MT_IB L1_GETX 0 <--
+MT_IB L1_UPGRADE 0 <--
+MT_IB L1_PUTX 0 <--
+MT_IB L1_PUTX_old 0 <--
+MT_IB L2_Replacement 0 <--
+MT_IB L2_Replacement_clean 0 <--
+MT_IB WB_Data 0 <--
+MT_IB WB_Data_clean 0 <--
+MT_IB Unblock_Cancel 0 <--
+MT_IB MEM_Inv 0 <--
+
+MT_SB L1_GET_INSTR 0 <--
+MT_SB L1_GETS 0 <--
+MT_SB L1_GETX 0 <--
+MT_SB L1_UPGRADE 0 <--
+MT_SB L1_PUTX 0 <--
+MT_SB L1_PUTX_old 0 <--
+MT_SB L2_Replacement 0 <--
+MT_SB L2_Replacement_clean 0 <--
+MT_SB Unblock 0 <--
+MT_SB MEM_Inv 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+ memory_total_requests: 1579
+ memory_reads: 835
+ memory_writes: 744
+ memory_refreshes: 744
+ memory_total_request_delays: 998
+ memory_delays_per_request: 0.632046
+ memory_delays_in_input_queue: 152
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 846
+ memory_stalls_for_bank_busy: 106
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 69
+ memory_stalls_for_bus: 344
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 255
+ memory_stalls_for_read_read_turnaround: 72
+ accesses_per_bank: 40 45 45 84 59 65 66 49 45 40 57 49 59 54 41 43 42 38 40 46 45 41 27 34 60 52 50 44 60 42 64 53
+
+ --- Directory 0 ---
+ - Event Counts -
+Fetch 835
+Data 744
+Memory_Data 835
+Memory_Ack 744
+DMA_READ 0
+DMA_WRITE 0
+CleanReplacement 87
+
+ - Transitions -
+I Fetch 835
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+ID Fetch 0 <--
+ID Data 0 <--
+ID Memory_Data 0 <--
+ID DMA_READ 0 <--
+ID DMA_WRITE 0 <--
+
+ID_W Fetch 0 <--
+ID_W Data 0 <--
+ID_W Memory_Ack 0 <--
+ID_W DMA_READ 0 <--
+ID_W DMA_WRITE 0 <--
+
+M Data 744
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+M CleanReplacement 87
+
+IM Fetch 0 <--
+IM Data 0 <--
+IM Memory_Data 835
+IM DMA_READ 0 <--
+IM DMA_WRITE 0 <--
+
+MI Fetch 0 <--
+MI Data 0 <--
+MI Memory_Ack 744
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+
+M_DRD Data 0 <--
+M_DRD DMA_READ 0 <--
+M_DRD DMA_WRITE 0 <--
+
+M_DRDI Fetch 0 <--
+M_DRDI Data 0 <--
+M_DRDI Memory_Ack 0 <--
+M_DRDI DMA_READ 0 <--
+M_DRDI DMA_WRITE 0 <--
+
+M_DWR Data 0 <--
+M_DWR DMA_READ 0 <--
+M_DWR DMA_WRITE 0 <--
+
+M_DWRI Fetch 0 <--
+M_DWRI Data 0 <--
+M_DWRI Memory_Ack 0 <--
+M_DWRI DMA_READ 0 <--
+M_DWRI DMA_WRITE 0 <--
+
--- /dev/null
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 27 2010 22:06:07
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 27 2010 22:07:35
+M5 executing on svvint03
+command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 357031 because Ruby Tester completed
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 213500 # Number of bytes of host memory used
+host_seconds 0.94 # Real time elapsed on the host
+host_tick_rate 379801 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.000357 # Number of seconds simulated
+sim_ticks 357031 # Number of ticks simulated
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=true
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+num_int_nodes=4
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=root.cpuPort[0]
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+buffer_size=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+response_latency=2
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links2.ext_node.directory
+directory_latency=6
+memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=3
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 1
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/27/2010 22:10:04
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 2
+Elapsed_time_in_minutes: 0.0333333
+Elapsed_time_in_hours: 0.000555556
+Elapsed_time_in_days: 2.31481e-05
+
+Virtual_time_in_seconds: 1.56
+Virtual_time_in_minutes: 0.026
+Virtual_time_in_hours: 0.000433333
+Virtual_time_in_days: 1.80556e-05
+
+Ruby_current_time: 392461
+Ruby_start_time: 0
+Ruby_cycles: 392461
+
+mbytes_resident: 31.2344
+mbytes_total: 31.2422
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 392462 [ 392462 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L2Cache-0:0
+L1Cache-0:0
+
+Directory-0:0
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1019 average: 15.8302 | standard deviation: 1.11429 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 54 951 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 256 max: 40198 count: 1004 average: 6102.55 | standard deviation: 8115.6 | 95 26 84 110 62 53 51 39 30 22 26 14 13 18 16 6 8 10 9 11 7 8 9 7 5 0 4 3 6 3 2 4 3 2 6 2 2 0 1 2 1 0 0 0 1 0 1 1 1 0 2 3 3 2 7 2 6 5 2 3 5 5 6 1 6 4 4 10 5 1 2 3 5 6 7 0 4 3 3 7 5 2 3 1 4 6 7 2 2 5 1 1 3 2 4 3 1 6 2 4 4 4 2 2 0 2 1 3 0 3 2 2 2 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 256 max: 40198 count: 100 average: 5910.08 | standard deviation: 7764.39 | 9 3 10 6 6 2 6 4 3 4 5 2 0 3 3 0 0 0 1 1 2 0 1 1 2 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 2 0 2 1 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 256 max: 33879 count: 904 average: 6123.85 | standard deviation: 8157.38 | 86 23 74 104 56 51 45 35 27 18 21 12 13 15 13 6 8 10 8 10 5 8 8 6 3 0 4 3 5 3 2 2 3 2 6 2 2 0 1 2 1 0 0 0 1 0 1 1 1 0 1 1 2 2 5 2 4 4 1 3 4 4 6 1 6 3 4 9 5 1 1 3 5 6 6 0 4 3 3 6 4 2 3 1 4 6 6 2 2 5 1 1 3 2 4 3 1 6 2 4 3 4 2 1 0 2 1 3 0 2 2 2 2 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 1
+system_time: 0
+page_reclaims: 6770
+page_faults: 1970
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.0840147
+ links_utilized_percent_switch_0_link_0: 0.0290093 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.13902 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 885 63720 [ 0 0 885 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 26 1872 [ 0 0 26 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 909 7272 [ 909 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 912 7296 [ 912 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 909 65448 [ 0 0 909 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 909 7272 [ 909 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 910 7280 [ 0 0 910 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.15235
+ links_utilized_percent_switch_1_link_0: 0.0629553 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.241744 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 912 7296 [ 912 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 909 65448 [ 0 0 909 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 1789 14312 [ 909 880 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Unblock_Control: 910 7280 [ 0 0 910 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 886 7088 [ 0 886 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 26 1872 [ 0 0 26 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 791 56952 [ 0 0 791 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 1878 15024 [ 909 880 89 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Unblock_Control: 884 7072 [ 0 0 884 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.0720995
+ links_utilized_percent_switch_2_link_0: 0.031398 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.112801 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Request_Control: 886 7088 [ 0 886 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 791 56952 [ 0 0 791 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 969 7752 [ 0 880 89 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Unblock_Control: 884 7072 [ 0 0 884 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Control: 880 7040 [ 0 880 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 3
+switch_3_outlinks: 3
+links_utilized_percent_switch_3: 0.164522
+ links_utilized_percent_switch_3_link_0: 0.116152 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.251821 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.125592 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 26 1872 [ 0 0 26 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Writeback_Control: 909 7272 [ 909 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 912 7296 [ 912 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 909 65448 [ 0 0 909 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Control: 1789 14312 [ 909 880 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Unblock_Control: 910 7280 [ 0 0 910 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Request_Control: 886 7088 [ 0 886 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Data: 791 56952 [ 0 0 791 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Control: 969 7752 [ 0 880 89 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Unblock_Control: 884 7072 [ 0 0 884 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 100
+Ifetch 0
+Store 905
+L1_Replacement 561824
+Own_GETX 0
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_DMA 0
+Inv 0
+Ack 0
+Data 0
+Exclusive_Data 911
+Writeback_Ack 0
+Writeback_Ack_Data 909
+Writeback_Nack 0
+All_acks 820
+Use_Timeout 910
+
+ - Transitions -
+I Load 91
+I Ifetch 0 <--
+I Store 821
+I L1_Replacement 0 <--
+I Inv 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L1_Replacement 0 <--
+S Fwd_GETS 0 <--
+S Fwd_DMA 0 <--
+S Inv 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_Replacement 0 <--
+O Fwd_GETX 0 <--
+O Fwd_GETS 0 <--
+O Fwd_DMA 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_Replacement 89
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_DMA 0 <--
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 1
+M_W L1_Replacement 3128
+M_W Own_GETX 0 <--
+M_W Fwd_GETX 0 <--
+M_W Fwd_GETS 0 <--
+M_W Fwd_DMA 0 <--
+M_W Inv 0 <--
+M_W Use_Timeout 89
+
+MM Load 9
+MM Ifetch 0 <--
+MM Store 73
+MM L1_Replacement 820
+MM Fwd_GETX 0 <--
+MM Fwd_GETS 0 <--
+MM Fwd_DMA 0 <--
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 10
+MM_W L1_Replacement 30537
+MM_W Own_GETX 0 <--
+MM_W Fwd_GETX 0 <--
+MM_W Fwd_GETS 0 <--
+MM_W Fwd_DMA 0 <--
+MM_W Inv 0 <--
+MM_W Use_Timeout 821
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 456440
+IM Inv 0 <--
+IM Ack 0 <--
+IM Data 0 <--
+IM Exclusive_Data 820
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Fwd_GETS 0 <--
+SM Fwd_DMA 0 <--
+SM Inv 0 <--
+SM Ack 0 <--
+SM Data 0 <--
+SM Exclusive_Data 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 16198
+OM Own_GETX 0 <--
+OM Fwd_GETX 0 <--
+OM Fwd_GETS 0 <--
+OM Fwd_DMA 0 <--
+OM Ack 0 <--
+OM All_acks 820
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 54612
+IS Inv 0 <--
+IS Data 0 <--
+IS Exclusive_Data 91
+
+SI Load 0 <--
+SI Ifetch 0 <--
+SI Store 0 <--
+SI L1_Replacement 0 <--
+SI Fwd_GETS 0 <--
+SI Fwd_DMA 0 <--
+SI Inv 0 <--
+SI Writeback_Ack 0 <--
+SI Writeback_Ack_Data 0 <--
+SI Writeback_Nack 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L1_Replacement 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Ack_Data 0 <--
+OI Writeback_Nack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 0 <--
+MI L1_Replacement 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 0 <--
+MI Writeback_Ack_Data 909
+MI Writeback_Nack 0 <--
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L1_Replacement 0 <--
+II Inv 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Ack_Data 0 <--
+II Writeback_Nack 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GETS 91
+L1_GETX 821
+L1_PUTO 0
+L1_PUTX 2498
+L1_PUTS_only 0
+L1_PUTS 0
+Fwd_GETX 0
+Fwd_GETS 0
+Fwd_DMA 0
+Own_GETX 0
+Inv 0
+IntAck 0
+ExtAck 0
+All_Acks 795
+Data 795
+Data_Exclusive 91
+L1_WBCLEANDATA 89
+L1_WBDIRTYDATA 820
+Writeback_Ack 880
+Writeback_Nack 0
+Unblock 0
+Exclusive_Unblock 910
+L2_Replacement 880
+
+ - Transitions -
+NP L1_GETS 91
+NP L1_GETX 795
+NP L1_PUTO 0 <--
+NP L1_PUTX 0 <--
+NP L1_PUTS 0 <--
+NP Inv 0 <--
+
+I L1_GETS 0 <--
+I L1_GETX 0 <--
+I L1_PUTO 0 <--
+I L1_PUTX 0 <--
+I L1_PUTS 0 <--
+I Inv 0 <--
+I L2_Replacement 0 <--
+
+ILS L1_GETS 0 <--
+ILS L1_GETX 0 <--
+ILS L1_PUTO 0 <--
+ILS L1_PUTX 0 <--
+ILS L1_PUTS_only 0 <--
+ILS L1_PUTS 0 <--
+ILS Inv 0 <--
+ILS L2_Replacement 0 <--
+
+ILX L1_GETS 0 <--
+ILX L1_GETX 0 <--
+ILX L1_PUTO 0 <--
+ILX L1_PUTX 909
+ILX L1_PUTS_only 0 <--
+ILX L1_PUTS 0 <--
+ILX Fwd_GETX 0 <--
+ILX Fwd_GETS 0 <--
+ILX Fwd_DMA 0 <--
+ILX Inv 0 <--
+ILX Data 0 <--
+ILX L2_Replacement 0 <--
+
+ILO L1_GETS 0 <--
+ILO L1_GETX 0 <--
+ILO L1_PUTO 0 <--
+ILO L1_PUTX 0 <--
+ILO L1_PUTS 0 <--
+ILO Fwd_GETX 0 <--
+ILO Fwd_GETS 0 <--
+ILO Fwd_DMA 0 <--
+ILO Inv 0 <--
+ILO Data 0 <--
+ILO L2_Replacement 0 <--
+
+ILOX L1_GETS 0 <--
+ILOX L1_GETX 0 <--
+ILOX L1_PUTO 0 <--
+ILOX L1_PUTX 0 <--
+ILOX L1_PUTS 0 <--
+ILOX Fwd_GETX 0 <--
+ILOX Fwd_GETS 0 <--
+ILOX Fwd_DMA 0 <--
+ILOX Data 0 <--
+
+ILOS L1_GETS 0 <--
+ILOS L1_GETX 0 <--
+ILOS L1_PUTO 0 <--
+ILOS L1_PUTX 0 <--
+ILOS L1_PUTS_only 0 <--
+ILOS L1_PUTS 0 <--
+ILOS Fwd_GETX 0 <--
+ILOS Fwd_GETS 0 <--
+ILOS Fwd_DMA 0 <--
+ILOS Data 0 <--
+ILOS L2_Replacement 0 <--
+
+ILOSX L1_GETS 0 <--
+ILOSX L1_GETX 0 <--
+ILOSX L1_PUTO 0 <--
+ILOSX L1_PUTX 0 <--
+ILOSX L1_PUTS_only 0 <--
+ILOSX L1_PUTS 0 <--
+ILOSX Fwd_GETX 0 <--
+ILOSX Fwd_GETS 0 <--
+ILOSX Fwd_DMA 0 <--
+ILOSX Data 0 <--
+
+S L1_GETS 0 <--
+S L1_GETX 0 <--
+S L1_PUTX 0 <--
+S L1_PUTS 0 <--
+S Inv 0 <--
+S L2_Replacement 0 <--
+
+O L1_GETS 0 <--
+O L1_GETX 0 <--
+O L1_PUTX 0 <--
+O Fwd_GETX 0 <--
+O Fwd_GETS 0 <--
+O Fwd_DMA 0 <--
+O L2_Replacement 0 <--
+
+OLS L1_GETS 0 <--
+OLS L1_GETX 0 <--
+OLS L1_PUTX 0 <--
+OLS L1_PUTS_only 0 <--
+OLS L1_PUTS 0 <--
+OLS Fwd_GETX 0 <--
+OLS Fwd_GETS 0 <--
+OLS Fwd_DMA 0 <--
+OLS L2_Replacement 0 <--
+
+OLSX L1_GETS 0 <--
+OLSX L1_GETX 0 <--
+OLSX L1_PUTO 0 <--
+OLSX L1_PUTX 0 <--
+OLSX L1_PUTS_only 0 <--
+OLSX L1_PUTS 0 <--
+OLSX Fwd_GETX 0 <--
+OLSX Fwd_GETS 0 <--
+OLSX Fwd_DMA 0 <--
+OLSX L2_Replacement 0 <--
+
+SLS L1_GETS 0 <--
+SLS L1_GETX 0 <--
+SLS L1_PUTX 0 <--
+SLS L1_PUTS_only 0 <--
+SLS L1_PUTS 0 <--
+SLS Inv 0 <--
+SLS L2_Replacement 0 <--
+
+M L1_GETS 0 <--
+M L1_GETX 26
+M L1_PUTO 0 <--
+M L1_PUTX 0 <--
+M L1_PUTS 0 <--
+M Fwd_GETX 0 <--
+M Fwd_GETS 0 <--
+M Fwd_DMA 0 <--
+M L2_Replacement 880
+
+IFGX L1_GETS 0 <--
+IFGX L1_GETX 0 <--
+IFGX L1_PUTO 0 <--
+IFGX L1_PUTX 0 <--
+IFGX L1_PUTS_only 0 <--
+IFGX L1_PUTS 0 <--
+IFGX Fwd_GETX 0 <--
+IFGX Fwd_GETS 0 <--
+IFGX Fwd_DMA 0 <--
+IFGX Inv 0 <--
+IFGX Data 0 <--
+IFGX Data_Exclusive 0 <--
+IFGX L2_Replacement 0 <--
+
+IFGS L1_GETS 0 <--
+IFGS L1_GETX 0 <--
+IFGS L1_PUTO 0 <--
+IFGS L1_PUTX 0 <--
+IFGS L1_PUTS_only 0 <--
+IFGS L1_PUTS 0 <--
+IFGS Fwd_GETX 0 <--
+IFGS Fwd_GETS 0 <--
+IFGS Fwd_DMA 0 <--
+IFGS Inv 0 <--
+IFGS Data 0 <--
+IFGS Data_Exclusive 0 <--
+IFGS L2_Replacement 0 <--
+
+ISFGS L1_GETS 0 <--
+ISFGS L1_GETX 0 <--
+ISFGS L1_PUTO 0 <--
+ISFGS L1_PUTX 0 <--
+ISFGS L1_PUTS_only 0 <--
+ISFGS L1_PUTS 0 <--
+ISFGS Fwd_GETX 0 <--
+ISFGS Fwd_GETS 0 <--
+ISFGS Fwd_DMA 0 <--
+ISFGS Inv 0 <--
+ISFGS Data 0 <--
+ISFGS L2_Replacement 0 <--
+
+IFGXX L1_GETS 0 <--
+IFGXX L1_GETX 0 <--
+IFGXX L1_PUTO 0 <--
+IFGXX L1_PUTX 0 <--
+IFGXX L1_PUTS_only 0 <--
+IFGXX L1_PUTS 0 <--
+IFGXX Fwd_GETX 0 <--
+IFGXX Fwd_GETS 0 <--
+IFGXX Fwd_DMA 0 <--
+IFGXX Inv 0 <--
+IFGXX IntAck 0 <--
+IFGXX All_Acks 0 <--
+IFGXX Data_Exclusive 0 <--
+IFGXX L2_Replacement 0 <--
+
+OFGX L1_GETS 0 <--
+OFGX L1_GETX 0 <--
+OFGX L1_PUTO 0 <--
+OFGX L1_PUTX 0 <--
+OFGX L1_PUTS_only 0 <--
+OFGX L1_PUTS 0 <--
+OFGX Fwd_GETX 0 <--
+OFGX Fwd_GETS 0 <--
+OFGX Fwd_DMA 0 <--
+OFGX Inv 0 <--
+OFGX L2_Replacement 0 <--
+
+OLSF L1_GETS 0 <--
+OLSF L1_GETX 0 <--
+OLSF L1_PUTO 0 <--
+OLSF L1_PUTX 0 <--
+OLSF L1_PUTS_only 0 <--
+OLSF L1_PUTS 0 <--
+OLSF Fwd_GETX 0 <--
+OLSF Fwd_GETS 0 <--
+OLSF Fwd_DMA 0 <--
+OLSF Inv 0 <--
+OLSF IntAck 0 <--
+OLSF All_Acks 0 <--
+OLSF L2_Replacement 0 <--
+
+ILOW L1_GETS 0 <--
+ILOW L1_GETX 0 <--
+ILOW L1_PUTO 0 <--
+ILOW L1_PUTX 0 <--
+ILOW L1_PUTS_only 0 <--
+ILOW L1_PUTS 0 <--
+ILOW Fwd_GETX 0 <--
+ILOW Fwd_GETS 0 <--
+ILOW Fwd_DMA 0 <--
+ILOW Inv 0 <--
+ILOW L1_WBCLEANDATA 0 <--
+ILOW L1_WBDIRTYDATA 0 <--
+ILOW Unblock 0 <--
+ILOW L2_Replacement 0 <--
+
+ILOXW L1_GETS 0 <--
+ILOXW L1_GETX 0 <--
+ILOXW L1_PUTO 0 <--
+ILOXW L1_PUTX 0 <--
+ILOXW L1_PUTS_only 0 <--
+ILOXW L1_PUTS 0 <--
+ILOXW Fwd_GETX 0 <--
+ILOXW Fwd_GETS 0 <--
+ILOXW Fwd_DMA 0 <--
+ILOXW Inv 0 <--
+ILOXW L1_WBCLEANDATA 0 <--
+ILOXW L1_WBDIRTYDATA 0 <--
+ILOXW Unblock 0 <--
+ILOXW L2_Replacement 0 <--
+
+ILOSW L1_GETS 0 <--
+ILOSW L1_GETX 0 <--
+ILOSW L1_PUTO 0 <--
+ILOSW L1_PUTX 0 <--
+ILOSW L1_PUTS_only 0 <--
+ILOSW L1_PUTS 0 <--
+ILOSW Fwd_GETX 0 <--
+ILOSW Fwd_GETS 0 <--
+ILOSW Fwd_DMA 0 <--
+ILOSW Inv 0 <--
+ILOSW L1_WBCLEANDATA 0 <--
+ILOSW L1_WBDIRTYDATA 0 <--
+ILOSW Unblock 0 <--
+ILOSW L2_Replacement 0 <--
+
+ILOSXW L1_GETS 0 <--
+ILOSXW L1_GETX 0 <--
+ILOSXW L1_PUTO 0 <--
+ILOSXW L1_PUTX 0 <--
+ILOSXW L1_PUTS_only 0 <--
+ILOSXW L1_PUTS 0 <--
+ILOSXW Fwd_GETX 0 <--
+ILOSXW Fwd_GETS 0 <--
+ILOSXW Fwd_DMA 0 <--
+ILOSXW Inv 0 <--
+ILOSXW L1_WBCLEANDATA 0 <--
+ILOSXW L1_WBDIRTYDATA 0 <--
+ILOSXW Unblock 0 <--
+ILOSXW L2_Replacement 0 <--
+
+SLSW L1_GETS 0 <--
+SLSW L1_GETX 0 <--
+SLSW L1_PUTO 0 <--
+SLSW L1_PUTX 0 <--
+SLSW L1_PUTS_only 0 <--
+SLSW L1_PUTS 0 <--
+SLSW Fwd_GETX 0 <--
+SLSW Fwd_GETS 0 <--
+SLSW Fwd_DMA 0 <--
+SLSW Inv 0 <--
+SLSW Unblock 0 <--
+SLSW L2_Replacement 0 <--
+
+OLSW L1_GETS 0 <--
+OLSW L1_GETX 0 <--
+OLSW L1_PUTO 0 <--
+OLSW L1_PUTX 0 <--
+OLSW L1_PUTS_only 0 <--
+OLSW L1_PUTS 0 <--
+OLSW Fwd_GETX 0 <--
+OLSW Fwd_GETS 0 <--
+OLSW Fwd_DMA 0 <--
+OLSW Inv 0 <--
+OLSW Unblock 0 <--
+OLSW L2_Replacement 0 <--
+
+ILSW L1_GETS 0 <--
+ILSW L1_GETX 0 <--
+ILSW L1_PUTO 0 <--
+ILSW L1_PUTX 0 <--
+ILSW L1_PUTS_only 0 <--
+ILSW L1_PUTS 0 <--
+ILSW Fwd_GETX 0 <--
+ILSW Fwd_GETS 0 <--
+ILSW Fwd_DMA 0 <--
+ILSW Inv 0 <--
+ILSW L1_WBCLEANDATA 0 <--
+ILSW Unblock 0 <--
+ILSW L2_Replacement 0 <--
+
+IW L1_GETS 0 <--
+IW L1_GETX 0 <--
+IW L1_PUTO 0 <--
+IW L1_PUTX 0 <--
+IW L1_PUTS_only 0 <--
+IW L1_PUTS 0 <--
+IW Fwd_GETX 0 <--
+IW Fwd_GETS 0 <--
+IW Fwd_DMA 0 <--
+IW Inv 0 <--
+IW L1_WBCLEANDATA 0 <--
+IW L2_Replacement 0 <--
+
+OW L1_GETS 0 <--
+OW L1_GETX 0 <--
+OW L1_PUTO 0 <--
+OW L1_PUTX 0 <--
+OW L1_PUTS_only 0 <--
+OW L1_PUTS 0 <--
+OW Fwd_GETX 0 <--
+OW Fwd_GETS 0 <--
+OW Fwd_DMA 0 <--
+OW Inv 0 <--
+OW Unblock 0 <--
+OW L2_Replacement 0 <--
+
+SW L1_GETS 0 <--
+SW L1_GETX 0 <--
+SW L1_PUTO 0 <--
+SW L1_PUTX 0 <--
+SW L1_PUTS_only 0 <--
+SW L1_PUTS 0 <--
+SW Fwd_GETX 0 <--
+SW Fwd_GETS 0 <--
+SW Fwd_DMA 0 <--
+SW Inv 0 <--
+SW Unblock 0 <--
+SW L2_Replacement 0 <--
+
+OXW L1_GETS 0 <--
+OXW L1_GETX 0 <--
+OXW L1_PUTO 0 <--
+OXW L1_PUTX 0 <--
+OXW L1_PUTS_only 0 <--
+OXW L1_PUTS 0 <--
+OXW Fwd_GETX 0 <--
+OXW Fwd_GETS 0 <--
+OXW Fwd_DMA 0 <--
+OXW Inv 0 <--
+OXW Unblock 0 <--
+OXW L2_Replacement 0 <--
+
+OLSXW L1_GETS 0 <--
+OLSXW L1_GETX 0 <--
+OLSXW L1_PUTO 0 <--
+OLSXW L1_PUTX 0 <--
+OLSXW L1_PUTS_only 0 <--
+OLSXW L1_PUTS 0 <--
+OLSXW Fwd_GETX 0 <--
+OLSXW Fwd_GETS 0 <--
+OLSXW Fwd_DMA 0 <--
+OLSXW Inv 0 <--
+OLSXW Unblock 0 <--
+OLSXW L2_Replacement 0 <--
+
+ILXW L1_GETS 0 <--
+ILXW L1_GETX 0 <--
+ILXW L1_PUTO 0 <--
+ILXW L1_PUTX 0 <--
+ILXW L1_PUTS_only 0 <--
+ILXW L1_PUTS 0 <--
+ILXW Fwd_GETX 0 <--
+ILXW Fwd_GETS 0 <--
+ILXW Fwd_DMA 0 <--
+ILXW Inv 0 <--
+ILXW Data 0 <--
+ILXW L1_WBCLEANDATA 89
+ILXW L1_WBDIRTYDATA 820
+ILXW Unblock 0 <--
+ILXW L2_Replacement 0 <--
+
+IFLS L1_GETS 0 <--
+IFLS L1_GETX 0 <--
+IFLS L1_PUTO 0 <--
+IFLS L1_PUTX 0 <--
+IFLS L1_PUTS_only 0 <--
+IFLS L1_PUTS 0 <--
+IFLS Fwd_GETX 0 <--
+IFLS Fwd_GETS 0 <--
+IFLS Fwd_DMA 0 <--
+IFLS Inv 0 <--
+IFLS Unblock 0 <--
+IFLS L2_Replacement 0 <--
+
+IFLO L1_GETS 0 <--
+IFLO L1_GETX 0 <--
+IFLO L1_PUTO 0 <--
+IFLO L1_PUTX 0 <--
+IFLO L1_PUTS_only 0 <--
+IFLO L1_PUTS 0 <--
+IFLO Fwd_GETX 0 <--
+IFLO Fwd_GETS 0 <--
+IFLO Fwd_DMA 0 <--
+IFLO Inv 0 <--
+IFLO Unblock 0 <--
+IFLO L2_Replacement 0 <--
+
+IFLOX L1_GETS 0 <--
+IFLOX L1_GETX 0 <--
+IFLOX L1_PUTO 0 <--
+IFLOX L1_PUTX 0 <--
+IFLOX L1_PUTS_only 0 <--
+IFLOX L1_PUTS 0 <--
+IFLOX Fwd_GETX 0 <--
+IFLOX Fwd_GETS 0 <--
+IFLOX Fwd_DMA 0 <--
+IFLOX Inv 0 <--
+IFLOX Unblock 0 <--
+IFLOX Exclusive_Unblock 0 <--
+IFLOX L2_Replacement 0 <--
+
+IFLOXX L1_GETS 0 <--
+IFLOXX L1_GETX 0 <--
+IFLOXX L1_PUTO 0 <--
+IFLOXX L1_PUTX 0 <--
+IFLOXX L1_PUTS_only 0 <--
+IFLOXX L1_PUTS 0 <--
+IFLOXX Fwd_GETX 0 <--
+IFLOXX Fwd_GETS 0 <--
+IFLOXX Fwd_DMA 0 <--
+IFLOXX Inv 0 <--
+IFLOXX Unblock 0 <--
+IFLOXX Exclusive_Unblock 0 <--
+IFLOXX L2_Replacement 0 <--
+
+IFLOSX L1_GETS 0 <--
+IFLOSX L1_GETX 0 <--
+IFLOSX L1_PUTO 0 <--
+IFLOSX L1_PUTX 0 <--
+IFLOSX L1_PUTS_only 0 <--
+IFLOSX L1_PUTS 0 <--
+IFLOSX Fwd_GETX 0 <--
+IFLOSX Fwd_GETS 0 <--
+IFLOSX Fwd_DMA 0 <--
+IFLOSX Inv 0 <--
+IFLOSX Unblock 0 <--
+IFLOSX Exclusive_Unblock 0 <--
+IFLOSX L2_Replacement 0 <--
+
+IFLXO L1_GETS 0 <--
+IFLXO L1_GETX 0 <--
+IFLXO L1_PUTO 0 <--
+IFLXO L1_PUTX 0 <--
+IFLXO L1_PUTS_only 0 <--
+IFLXO L1_PUTS 0 <--
+IFLXO Fwd_GETX 0 <--
+IFLXO Fwd_GETS 0 <--
+IFLXO Fwd_DMA 0 <--
+IFLXO Inv 0 <--
+IFLXO Exclusive_Unblock 0 <--
+IFLXO L2_Replacement 0 <--
+
+IGS L1_GETS 0 <--
+IGS L1_GETX 0 <--
+IGS L1_PUTO 0 <--
+IGS L1_PUTX 136
+IGS L1_PUTS_only 0 <--
+IGS L1_PUTS 0 <--
+IGS Fwd_GETX 0 <--
+IGS Fwd_GETS 0 <--
+IGS Fwd_DMA 0 <--
+IGS Own_GETX 0 <--
+IGS Inv 0 <--
+IGS Data 0 <--
+IGS Data_Exclusive 91
+IGS Unblock 0 <--
+IGS Exclusive_Unblock 90
+IGS L2_Replacement 0 <--
+
+IGM L1_GETS 0 <--
+IGM L1_GETX 0 <--
+IGM L1_PUTO 0 <--
+IGM L1_PUTX 0 <--
+IGM L1_PUTS_only 0 <--
+IGM L1_PUTS 0 <--
+IGM Fwd_GETX 0 <--
+IGM Fwd_GETS 0 <--
+IGM Fwd_DMA 0 <--
+IGM Own_GETX 0 <--
+IGM Inv 0 <--
+IGM ExtAck 0 <--
+IGM Data 795
+IGM Data_Exclusive 0 <--
+IGM L2_Replacement 0 <--
+
+IGMLS L1_GETS 0 <--
+IGMLS L1_GETX 0 <--
+IGMLS L1_PUTO 0 <--
+IGMLS L1_PUTX 0 <--
+IGMLS L1_PUTS_only 0 <--
+IGMLS L1_PUTS 0 <--
+IGMLS Inv 0 <--
+IGMLS IntAck 0 <--
+IGMLS ExtAck 0 <--
+IGMLS All_Acks 0 <--
+IGMLS Data 0 <--
+IGMLS Data_Exclusive 0 <--
+IGMLS L2_Replacement 0 <--
+
+IGMO L1_GETS 0 <--
+IGMO L1_GETX 0 <--
+IGMO L1_PUTO 0 <--
+IGMO L1_PUTX 1443
+IGMO L1_PUTS_only 0 <--
+IGMO L1_PUTS 0 <--
+IGMO Fwd_GETX 0 <--
+IGMO Fwd_GETS 0 <--
+IGMO Fwd_DMA 0 <--
+IGMO Own_GETX 0 <--
+IGMO ExtAck 0 <--
+IGMO All_Acks 795
+IGMO Exclusive_Unblock 794
+IGMO L2_Replacement 0 <--
+
+IGMIO L1_GETS 0 <--
+IGMIO L1_GETX 0 <--
+IGMIO L1_PUTO 0 <--
+IGMIO L1_PUTX 0 <--
+IGMIO L1_PUTS_only 0 <--
+IGMIO L1_PUTS 0 <--
+IGMIO Fwd_GETX 0 <--
+IGMIO Fwd_GETS 0 <--
+IGMIO Fwd_DMA 0 <--
+IGMIO Own_GETX 0 <--
+IGMIO ExtAck 0 <--
+IGMIO All_Acks 0 <--
+
+OGMIO L1_GETS 0 <--
+OGMIO L1_GETX 0 <--
+OGMIO L1_PUTO 0 <--
+OGMIO L1_PUTX 0 <--
+OGMIO L1_PUTS_only 0 <--
+OGMIO L1_PUTS 0 <--
+OGMIO Fwd_GETX 0 <--
+OGMIO Fwd_GETS 0 <--
+OGMIO Fwd_DMA 0 <--
+OGMIO Own_GETX 0 <--
+OGMIO ExtAck 0 <--
+OGMIO All_Acks 0 <--
+
+IGMIOF L1_GETS 0 <--
+IGMIOF L1_GETX 0 <--
+IGMIOF L1_PUTO 0 <--
+IGMIOF L1_PUTX 0 <--
+IGMIOF L1_PUTS_only 0 <--
+IGMIOF L1_PUTS 0 <--
+IGMIOF IntAck 0 <--
+IGMIOF All_Acks 0 <--
+IGMIOF Data_Exclusive 0 <--
+
+IGMIOFS L1_GETS 0 <--
+IGMIOFS L1_GETX 0 <--
+IGMIOFS L1_PUTO 0 <--
+IGMIOFS L1_PUTX 0 <--
+IGMIOFS L1_PUTS_only 0 <--
+IGMIOFS L1_PUTS 0 <--
+IGMIOFS Fwd_GETX 0 <--
+IGMIOFS Fwd_GETS 0 <--
+IGMIOFS Fwd_DMA 0 <--
+IGMIOFS Inv 0 <--
+IGMIOFS Data 0 <--
+IGMIOFS L2_Replacement 0 <--
+
+OGMIOF L1_GETS 0 <--
+OGMIOF L1_GETX 0 <--
+OGMIOF L1_PUTO 0 <--
+OGMIOF L1_PUTX 0 <--
+OGMIOF L1_PUTS_only 0 <--
+OGMIOF L1_PUTS 0 <--
+OGMIOF IntAck 0 <--
+OGMIOF All_Acks 0 <--
+
+II L1_GETS 0 <--
+II L1_GETX 0 <--
+II L1_PUTO 0 <--
+II L1_PUTX 0 <--
+II L1_PUTS_only 0 <--
+II L1_PUTS 0 <--
+II IntAck 0 <--
+II All_Acks 0 <--
+
+MM L1_GETS 0 <--
+MM L1_GETX 0 <--
+MM L1_PUTO 0 <--
+MM L1_PUTX 10
+MM L1_PUTS_only 0 <--
+MM L1_PUTS 0 <--
+MM Fwd_GETX 0 <--
+MM Fwd_GETS 0 <--
+MM Fwd_DMA 0 <--
+MM Inv 0 <--
+MM Exclusive_Unblock 26
+MM L2_Replacement 0 <--
+
+SS L1_GETS 0 <--
+SS L1_GETX 0 <--
+SS L1_PUTO 0 <--
+SS L1_PUTX 0 <--
+SS L1_PUTS_only 0 <--
+SS L1_PUTS 0 <--
+SS Fwd_GETX 0 <--
+SS Fwd_GETS 0 <--
+SS Fwd_DMA 0 <--
+SS Inv 0 <--
+SS Unblock 0 <--
+SS L2_Replacement 0 <--
+
+OO L1_GETS 0 <--
+OO L1_GETX 0 <--
+OO L1_PUTO 0 <--
+OO L1_PUTX 0 <--
+OO L1_PUTS_only 0 <--
+OO L1_PUTS 0 <--
+OO Fwd_GETX 0 <--
+OO Fwd_GETS 0 <--
+OO Fwd_DMA 0 <--
+OO Inv 0 <--
+OO Unblock 0 <--
+OO Exclusive_Unblock 0 <--
+OO L2_Replacement 0 <--
+
+OLSS L1_GETS 0 <--
+OLSS L1_GETX 0 <--
+OLSS L1_PUTO 0 <--
+OLSS L1_PUTX 0 <--
+OLSS L1_PUTS_only 0 <--
+OLSS L1_PUTS 0 <--
+OLSS Fwd_GETX 0 <--
+OLSS Fwd_GETS 0 <--
+OLSS Fwd_DMA 0 <--
+OLSS Inv 0 <--
+OLSS Unblock 0 <--
+OLSS L2_Replacement 0 <--
+
+OLSXS L1_GETS 0 <--
+OLSXS L1_GETX 0 <--
+OLSXS L1_PUTO 0 <--
+OLSXS L1_PUTX 0 <--
+OLSXS L1_PUTS_only 0 <--
+OLSXS L1_PUTS 0 <--
+OLSXS Fwd_GETX 0 <--
+OLSXS Fwd_GETS 0 <--
+OLSXS Fwd_DMA 0 <--
+OLSXS Inv 0 <--
+OLSXS Unblock 0 <--
+OLSXS L2_Replacement 0 <--
+
+SLSS L1_GETS 0 <--
+SLSS L1_GETX 0 <--
+SLSS L1_PUTO 0 <--
+SLSS L1_PUTX 0 <--
+SLSS L1_PUTS_only 0 <--
+SLSS L1_PUTS 0 <--
+SLSS Fwd_GETX 0 <--
+SLSS Fwd_GETS 0 <--
+SLSS Fwd_DMA 0 <--
+SLSS Inv 0 <--
+SLSS Unblock 0 <--
+SLSS L2_Replacement 0 <--
+
+OI L1_GETS 0 <--
+OI L1_GETX 0 <--
+OI L1_PUTO 0 <--
+OI L1_PUTX 0 <--
+OI L1_PUTS_only 0 <--
+OI L1_PUTS 0 <--
+OI Fwd_GETX 0 <--
+OI Fwd_GETS 0 <--
+OI Fwd_DMA 0 <--
+OI Writeback_Ack 0 <--
+OI Writeback_Nack 0 <--
+OI L2_Replacement 0 <--
+
+MI L1_GETS 0 <--
+MI L1_GETX 0 <--
+MI L1_PUTO 0 <--
+MI L1_PUTX 0 <--
+MI L1_PUTS_only 0 <--
+MI L1_PUTS 0 <--
+MI Fwd_GETX 0 <--
+MI Fwd_GETS 0 <--
+MI Fwd_DMA 0 <--
+MI Writeback_Ack 880
+MI L2_Replacement 0 <--
+
+MII L1_GETS 0 <--
+MII L1_GETX 0 <--
+MII L1_PUTO 0 <--
+MII L1_PUTX 0 <--
+MII L1_PUTS_only 0 <--
+MII L1_PUTS 0 <--
+MII Writeback_Ack 0 <--
+MII Writeback_Nack 0 <--
+MII L2_Replacement 0 <--
+
+OLSI L1_GETS 0 <--
+OLSI L1_GETX 0 <--
+OLSI L1_PUTO 0 <--
+OLSI L1_PUTX 0 <--
+OLSI L1_PUTS_only 0 <--
+OLSI L1_PUTS 0 <--
+OLSI Fwd_GETX 0 <--
+OLSI Fwd_GETS 0 <--
+OLSI Fwd_DMA 0 <--
+OLSI Writeback_Ack 0 <--
+OLSI L2_Replacement 0 <--
+
+ILSI L1_GETS 0 <--
+ILSI L1_GETX 0 <--
+ILSI L1_PUTO 0 <--
+ILSI L1_PUTX 0 <--
+ILSI L1_PUTS_only 0 <--
+ILSI L1_PUTS 0 <--
+ILSI IntAck 0 <--
+ILSI All_Acks 0 <--
+ILSI Writeback_Ack 0 <--
+ILSI L2_Replacement 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+ memory_total_requests: 1677
+ memory_reads: 886
+ memory_writes: 790
+ memory_refreshes: 818
+ memory_total_request_delays: 692
+ memory_delays_per_request: 0.412642
+ memory_delays_in_input_queue: 87
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 605
+ memory_stalls_for_bank_busy: 167
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 43
+ memory_stalls_for_bus: 243
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 87
+ memory_stalls_for_read_read_turnaround: 65
+ accesses_per_bank: 42 41 55 101 73 61 50 48 47 43 39 61 48 55 46 42 57 58 54 52 60 39 57 54 37 53 55 57 48 45 60 39
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 795
+GETS 91
+PUTX 880
+PUTO 0
+PUTO_SHARERS 0
+Unblock 0
+Last_Unblock 0
+Exclusive_Unblock 884
+Clean_Writeback 89
+Dirty_Writeback 791
+Memory_Data 886
+Memory_Ack 790
+DMA_READ 0
+DMA_WRITE 0
+Data 0
+
+ - Transitions -
+I GETX 795
+I GETS 91
+I PUTX 0 <--
+I PUTO 0 <--
+I Memory_Data 0 <--
+I Memory_Ack 790
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+S GETX 0 <--
+S GETS 0 <--
+S PUTX 0 <--
+S PUTO 0 <--
+S Memory_Data 0 <--
+S Memory_Ack 0 <--
+S DMA_READ 0 <--
+S DMA_WRITE 0 <--
+
+O GETX 0 <--
+O GETS 0 <--
+O PUTX 0 <--
+O PUTO 0 <--
+O PUTO_SHARERS 0 <--
+O Memory_Data 0 <--
+O Memory_Ack 0 <--
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+
+M GETX 0 <--
+M GETS 0 <--
+M PUTX 880
+M PUTO 0 <--
+M PUTO_SHARERS 0 <--
+M Memory_Data 0 <--
+M Memory_Ack 0 <--
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+
+IS GETX 0 <--
+IS GETS 0 <--
+IS PUTX 0 <--
+IS PUTO 0 <--
+IS PUTO_SHARERS 0 <--
+IS Unblock 0 <--
+IS Exclusive_Unblock 90
+IS Memory_Data 91
+IS Memory_Ack 0 <--
+IS DMA_READ 0 <--
+IS DMA_WRITE 0 <--
+
+SS GETX 0 <--
+SS GETS 0 <--
+SS PUTX 0 <--
+SS PUTO 0 <--
+SS PUTO_SHARERS 0 <--
+SS Unblock 0 <--
+SS Last_Unblock 0 <--
+SS Memory_Data 0 <--
+SS Memory_Ack 0 <--
+SS DMA_READ 0 <--
+SS DMA_WRITE 0 <--
+
+OO GETX 0 <--
+OO GETS 0 <--
+OO PUTX 0 <--
+OO PUTO 0 <--
+OO PUTO_SHARERS 0 <--
+OO Unblock 0 <--
+OO Last_Unblock 0 <--
+OO Memory_Data 0 <--
+OO Memory_Ack 0 <--
+OO DMA_READ 0 <--
+OO DMA_WRITE 0 <--
+
+MO GETX 0 <--
+MO GETS 0 <--
+MO PUTX 0 <--
+MO PUTO 0 <--
+MO PUTO_SHARERS 0 <--
+MO Unblock 0 <--
+MO Exclusive_Unblock 0 <--
+MO Memory_Data 0 <--
+MO Memory_Ack 0 <--
+MO DMA_READ 0 <--
+MO DMA_WRITE 0 <--
+
+MM GETX 0 <--
+MM GETS 0 <--
+MM PUTX 0 <--
+MM PUTO 0 <--
+MM PUTO_SHARERS 0 <--
+MM Exclusive_Unblock 794
+MM Memory_Data 795
+MM Memory_Ack 0 <--
+MM DMA_READ 0 <--
+MM DMA_WRITE 0 <--
+
+
+MI GETX 0 <--
+MI GETS 0 <--
+MI PUTX 0 <--
+MI PUTO 0 <--
+MI PUTO_SHARERS 0 <--
+MI Unblock 0 <--
+MI Clean_Writeback 89
+MI Dirty_Writeback 791
+MI Memory_Data 0 <--
+MI Memory_Ack 0 <--
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+
+MIS GETX 0 <--
+MIS GETS 0 <--
+MIS PUTX 0 <--
+MIS PUTO 0 <--
+MIS PUTO_SHARERS 0 <--
+MIS Unblock 0 <--
+MIS Clean_Writeback 0 <--
+MIS Dirty_Writeback 0 <--
+MIS Memory_Data 0 <--
+MIS Memory_Ack 0 <--
+MIS DMA_READ 0 <--
+MIS DMA_WRITE 0 <--
+
+OS GETX 0 <--
+OS GETS 0 <--
+OS PUTX 0 <--
+OS PUTO 0 <--
+OS PUTO_SHARERS 0 <--
+OS Unblock 0 <--
+OS Clean_Writeback 0 <--
+OS Dirty_Writeback 0 <--
+OS Memory_Data 0 <--
+OS Memory_Ack 0 <--
+OS DMA_READ 0 <--
+OS DMA_WRITE 0 <--
+
+OSS GETX 0 <--
+OSS GETS 0 <--
+OSS PUTX 0 <--
+OSS PUTO 0 <--
+OSS PUTO_SHARERS 0 <--
+OSS Unblock 0 <--
+OSS Clean_Writeback 0 <--
+OSS Dirty_Writeback 0 <--
+OSS Memory_Data 0 <--
+OSS Memory_Ack 0 <--
+OSS DMA_READ 0 <--
+OSS DMA_WRITE 0 <--
+
+XI_M GETX 0 <--
+XI_M GETS 0 <--
+XI_M PUTX 0 <--
+XI_M PUTO 0 <--
+XI_M PUTO_SHARERS 0 <--
+XI_M Memory_Data 0 <--
+XI_M Memory_Ack 0 <--
+XI_M DMA_READ 0 <--
+XI_M DMA_WRITE 0 <--
+
+XI_U GETX 0 <--
+XI_U GETS 0 <--
+XI_U PUTX 0 <--
+XI_U PUTO 0 <--
+XI_U PUTO_SHARERS 0 <--
+XI_U Exclusive_Unblock 0 <--
+XI_U Memory_Ack 0 <--
+XI_U DMA_READ 0 <--
+XI_U DMA_WRITE 0 <--
+
+OI_D GETX 0 <--
+OI_D GETS 0 <--
+OI_D PUTX 0 <--
+OI_D PUTO 0 <--
+OI_D PUTO_SHARERS 0 <--
+OI_D DMA_READ 0 <--
+OI_D DMA_WRITE 0 <--
+OI_D Data 0 <--
+
--- /dev/null
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 27 2010 22:09:32
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 27 2010 22:10:02
+M5 executing on svvint05
+command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 392461 because Ruby Tester completed
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 213656 # Number of bytes of host memory used
+host_seconds 1.32 # Real time elapsed on the host
+host_tick_rate 297317 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.000392 # Number of seconds simulated
+sim_ticks 392461 # Number of ticks simulated
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=true
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+num_int_nodes=4
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+N_tokens=2
+buffer_size=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=root.cpuPort[0]
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+N_tokens=2
+buffer_size=0
+filtering_enabled=true
+l2_request_latency=10
+l2_response_latency=10
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links2]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links2.ext_node
+int_node=2
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links2.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links2.ext_node.directory
+directory_latency=6
+distributed_persistent=true
+fixed_timeout_latency=300
+l2_select_num_bits=0
+memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=3
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=2
+node_b=3
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 1
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: active, ordered
+virtual_net_3: active, unordered
+virtual_net_4: active, unordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/27/2010 22:01:59
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.6
+Virtual_time_in_minutes: 0.01
+Virtual_time_in_hours: 0.000166667
+Virtual_time_in_days: 6.94444e-06
+
+Ruby_current_time: 282171
+Ruby_start_time: 0
+Ruby_cycles: 282171
+
+mbytes_resident: 31.1484
+mbytes_total: 31.1562
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 282172 [ 282172 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1009 average: 15.8355 | standard deviation: 1.11759 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 47 948 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 256 max: 28196 count: 994 average: 4457.39 | standard deviation: 6147.87 | 100 90 146 90 76 63 38 29 21 17 11 10 8 10 15 7 4 1 2 1 1 0 0 4 1 1 5 2 1 7 5 4 0 1 3 1 0 3 1 4 3 5 4 5 5 7 6 4 6 8 11 7 5 8 5 9 7 6 5 0 4 4 5 5 5 3 3 10 7 7 2 4 4 4 3 2 1 6 1 1 0 2 0 0 1 0 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 256 max: 26957 count: 100 average: 4118.53 | standard deviation: 6450.59 | 11 9 15 11 8 7 5 4 1 3 2 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 1 1 1 0 2 0 0 0 0 1 1 0 0 0 0 1 0 0 0 3 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 256 max: 28196 count: 894 average: 4495.3 | standard deviation: 6115.67 | 89 81 131 79 68 56 33 25 20 14 9 9 8 10 13 6 4 1 2 1 1 0 0 4 1 1 5 2 1 7 5 4 0 1 3 1 0 3 1 4 2 5 3 5 5 7 6 4 5 7 10 7 4 7 4 9 5 6 5 0 4 3 4 5 5 3 3 9 7 7 2 1 4 3 3 1 1 6 1 1 0 2 0 0 1 0 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 6756
+page_faults: 1961
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.108507
+ links_utilized_percent_switch_0_link_0: 0.0403656 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.176648 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 36 2592 [ 0 36 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Data: 55 3960 [ 0 55 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 907 7256 [ 0 0 0 0 907 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Data: 13 936 [ 0 13 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 955 68760 [ 0 955 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 4 32 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.095051
+ links_utilized_percent_switch_1_link_0: 0.0414509 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.148651 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 907 7256 [ 0 0 0 0 907 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 900 64800 [ 0 900 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 4 32 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 871 6968 [ 0 0 0 871 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 12 864 [ 0 12 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 36 2592 [ 0 36 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 779 56088 [ 0 779 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 75 600 [ 0 75 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.0888003
+ links_utilized_percent_switch_2_link_0: 0.0375792 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.140021 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Request_Control: 871 6968 [ 0 0 0 871 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Data: 13 936 [ 0 13 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 786 56592 [ 0 786 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 75 600 [ 0 75 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 871 62712 [ 0 871 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Data: 7 504 [ 0 7 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 3
+switch_3_outlinks: 3
+links_utilized_percent_switch_3: 0.157151
+ links_utilized_percent_switch_3_link_0: 0.155331 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.165804 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.150317 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 36 2592 [ 0 36 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Writeback_Data: 55 3960 [ 0 55 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 907 7256 [ 0 0 0 0 907 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 900 64800 [ 0 900 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Control: 4 32 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Request_Control: 871 6968 [ 0 0 0 871 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Response_Data: 13 936 [ 0 13 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Data: 786 56592 [ 0 786 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Control: 75 600 [ 0 75 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 100
+Ifetch 0
+Store 895
+L1_Replacement 404448
+Data_Shared 4
+Data_Owner 0
+Data_All_Tokens 970
+Ack 0
+Ack_All_Tokens 0
+Transient_GETX 0
+Transient_Local_GETX 0
+Transient_GETS 0
+Transient_Local_GETS 0
+Transient_GETS_Last_Token 0
+Transient_Local_GETS_Last_Token 0
+Persistent_GETX 0
+Persistent_GETS 0
+Own_Lock_or_Unlock 346
+Request_Timeout 644
+Use_TimeoutStarverX 0
+Use_TimeoutStarverS 0
+Use_TimeoutNoStarvers 901
+
+ - Transitions -
+NP Load 90
+NP Ifetch 0 <--
+NP Store 817
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 68
+NP Ack 0 <--
+NP Transient_GETX 0 <--
+NP Transient_Local_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Transient_Local_GETS 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 175
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_Replacement 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Transient_GETX 0 <--
+I Transient_Local_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_Local_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I Transient_Local_GETS_Last_Token 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L1_Replacement 4
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Transient_GETX 0 <--
+S Transient_Local_GETX 0 <--
+S Transient_GETS 0 <--
+S Transient_Local_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S Transient_Local_GETS_Last_Token 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_Replacement 0 <--
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Transient_GETX 0 <--
+O Transient_Local_GETX 0 <--
+O Transient_GETS 0 <--
+O Transient_Local_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O Transient_Local_GETS_Last_Token 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_Replacement 85
+M Transient_GETX 0 <--
+M Transient_Local_GETX 0 <--
+M Transient_GETS 0 <--
+M Transient_Local_GETS 0 <--
+M Persistent_GETX 0 <--
+M Persistent_GETS 0 <--
+M Own_Lock_or_Unlock 0 <--
+
+MM Load 8
+MM Ifetch 0 <--
+MM Store 66
+MM L1_Replacement 815
+MM Transient_GETX 0 <--
+MM Transient_Local_GETX 0 <--
+MM Transient_GETS 0 <--
+MM Transient_Local_GETS 0 <--
+MM Persistent_GETX 0 <--
+MM Persistent_GETS 0 <--
+MM Own_Lock_or_Unlock 24
+
+M_W Load 1
+M_W Ifetch 0 <--
+M_W Store 0 <--
+M_W L1_Replacement 3682
+M_W Transient_GETX 0 <--
+M_W Transient_Local_GETX 0 <--
+M_W Transient_GETS 0 <--
+M_W Transient_Local_GETS 0 <--
+M_W Persistent_GETX 0 <--
+M_W Persistent_GETS 0 <--
+M_W Own_Lock_or_Unlock 3
+M_W Use_TimeoutStarverX 0 <--
+M_W Use_TimeoutStarverS 0 <--
+M_W Use_TimeoutNoStarvers 85
+
+MM_W Load 1
+MM_W Ifetch 0 <--
+MM_W Store 12
+MM_W L1_Replacement 29932
+MM_W Transient_GETX 0 <--
+MM_W Transient_Local_GETX 0 <--
+MM_W Transient_GETS 0 <--
+MM_W Transient_Local_GETS 0 <--
+MM_W Persistent_GETX 0 <--
+MM_W Persistent_GETS 0 <--
+MM_W Own_Lock_or_Unlock 21
+MM_W Use_TimeoutStarverX 0 <--
+MM_W Use_TimeoutStarverS 0 <--
+MM_W Use_TimeoutNoStarvers 816
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L1_Replacement 334259
+IM Data_Shared 0 <--
+IM Data_Owner 0 <--
+IM Data_All_Tokens 816
+IM Ack 0 <--
+IM Transient_GETX 0 <--
+IM Transient_Local_GETX 0 <--
+IM Transient_GETS 0 <--
+IM Transient_Local_GETS 0 <--
+IM Transient_GETS_Last_Token 0 <--
+IM Transient_Local_GETS_Last_Token 0 <--
+IM Persistent_GETX 0 <--
+IM Persistent_GETS 0 <--
+IM Own_Lock_or_Unlock 109
+IM Request_Timeout 597
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L1_Replacement 0 <--
+SM Data_Shared 0 <--
+SM Data_Owner 0 <--
+SM Data_All_Tokens 0 <--
+SM Ack 0 <--
+SM Transient_GETX 0 <--
+SM Transient_Local_GETX 0 <--
+SM Transient_GETS 0 <--
+SM Transient_Local_GETS 0 <--
+SM Transient_GETS_Last_Token 0 <--
+SM Transient_Local_GETS_Last_Token 0 <--
+SM Persistent_GETX 0 <--
+SM Persistent_GETS 0 <--
+SM Own_Lock_or_Unlock 0 <--
+SM Request_Timeout 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L1_Replacement 0 <--
+OM Data_Shared 0 <--
+OM Data_All_Tokens 0 <--
+OM Ack 0 <--
+OM Ack_All_Tokens 0 <--
+OM Transient_GETX 0 <--
+OM Transient_Local_GETX 0 <--
+OM Transient_GETS 0 <--
+OM Transient_Local_GETS 0 <--
+OM Transient_GETS_Last_Token 0 <--
+OM Transient_Local_GETS_Last_Token 0 <--
+OM Persistent_GETX 0 <--
+OM Persistent_GETS 0 <--
+OM Own_Lock_or_Unlock 0 <--
+OM Request_Timeout 0 <--
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L1_Replacement 35671
+IS Data_Shared 4
+IS Data_Owner 0 <--
+IS Data_All_Tokens 86
+IS Ack 0 <--
+IS Transient_GETX 0 <--
+IS Transient_Local_GETX 0 <--
+IS Transient_GETS 0 <--
+IS Transient_Local_GETS 0 <--
+IS Transient_GETS_Last_Token 0 <--
+IS Transient_Local_GETS_Last_Token 0 <--
+IS Persistent_GETX 0 <--
+IS Persistent_GETS 0 <--
+IS Own_Lock_or_Unlock 14
+IS Request_Timeout 47
+
+I_L Load 0 <--
+I_L Ifetch 0 <--
+I_L Store 0 <--
+I_L L1_Replacement 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_Local_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_Local_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L Transient_Local_GETS_Last_Token 0 <--
+I_L Persistent_GETX 0 <--
+I_L Persistent_GETS 0 <--
+I_L Own_Lock_or_Unlock 0 <--
+
+S_L Load 0 <--
+S_L Ifetch 0 <--
+S_L Store 0 <--
+S_L L1_Replacement 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_Local_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_Local_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L Transient_Local_GETS_Last_Token 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 0 <--
+
+IM_L Load 0 <--
+IM_L Ifetch 0 <--
+IM_L Store 0 <--
+IM_L L1_Replacement 0 <--
+IM_L Data_Shared 0 <--
+IM_L Data_Owner 0 <--
+IM_L Data_All_Tokens 0 <--
+IM_L Ack 0 <--
+IM_L Transient_GETX 0 <--
+IM_L Transient_Local_GETX 0 <--
+IM_L Transient_GETS 0 <--
+IM_L Transient_Local_GETS 0 <--
+IM_L Transient_GETS_Last_Token 0 <--
+IM_L Transient_Local_GETS_Last_Token 0 <--
+IM_L Persistent_GETX 0 <--
+IM_L Persistent_GETS 0 <--
+IM_L Own_Lock_or_Unlock 0 <--
+IM_L Request_Timeout 0 <--
+
+SM_L Load 0 <--
+SM_L Ifetch 0 <--
+SM_L Store 0 <--
+SM_L L1_Replacement 0 <--
+SM_L Data_Shared 0 <--
+SM_L Data_Owner 0 <--
+SM_L Data_All_Tokens 0 <--
+SM_L Ack 0 <--
+SM_L Transient_GETX 0 <--
+SM_L Transient_Local_GETX 0 <--
+SM_L Transient_GETS 0 <--
+SM_L Transient_Local_GETS 0 <--
+SM_L Transient_GETS_Last_Token 0 <--
+SM_L Transient_Local_GETS_Last_Token 0 <--
+SM_L Persistent_GETX 0 <--
+SM_L Persistent_GETS 0 <--
+SM_L Own_Lock_or_Unlock 0 <--
+SM_L Request_Timeout 0 <--
+
+IS_L Load 0 <--
+IS_L Ifetch 0 <--
+IS_L Store 0 <--
+IS_L L1_Replacement 0 <--
+IS_L Data_Shared 0 <--
+IS_L Data_Owner 0 <--
+IS_L Data_All_Tokens 0 <--
+IS_L Ack 0 <--
+IS_L Transient_GETX 0 <--
+IS_L Transient_Local_GETX 0 <--
+IS_L Transient_GETS 0 <--
+IS_L Transient_Local_GETS 0 <--
+IS_L Transient_GETS_Last_Token 0 <--
+IS_L Transient_Local_GETS_Last_Token 0 <--
+IS_L Persistent_GETX 0 <--
+IS_L Persistent_GETS 0 <--
+IS_L Own_Lock_or_Unlock 0 <--
+IS_L Request_Timeout 0 <--
+
+Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L2Cache 0 ---
+ - Event Counts -
+L1_GETS 90
+L1_GETS_Last_Token 0
+L1_GETX 817
+L1_INV 0
+Transient_GETX 0
+Transient_GETS 0
+Transient_GETS_Last_Token 0
+L2_Replacement 821
+Writeback_Tokens 1
+Writeback_Shared_Data 0
+Writeback_All_Tokens 903
+Writeback_Owned 0
+Data_Shared 0
+Data_Owner 0
+Data_All_Tokens 0
+Ack 0
+Ack_All_Tokens 0
+Persistent_GETX 155
+Persistent_GETS 18
+Own_Lock_or_Unlock 173
+
+ - Transitions -
+NP L1_GETS 86
+NP L1_GETX 785
+NP L1_INV 0 <--
+NP Transient_GETX 0 <--
+NP Transient_GETS 0 <--
+NP Writeback_Tokens 1
+NP Writeback_Shared_Data 0 <--
+NP Writeback_All_Tokens 823
+NP Writeback_Owned 0 <--
+NP Data_Shared 0 <--
+NP Data_Owner 0 <--
+NP Data_All_Tokens 0 <--
+NP Ack 0 <--
+NP Persistent_GETX 0 <--
+NP Persistent_GETS 0 <--
+NP Own_Lock_or_Unlock 161
+
+I L1_GETS 0 <--
+I L1_GETS_Last_Token 0 <--
+I L1_GETX 0 <--
+I L1_INV 0 <--
+I Transient_GETX 0 <--
+I Transient_GETS 0 <--
+I Transient_GETS_Last_Token 0 <--
+I L2_Replacement 16
+I Writeback_Tokens 0 <--
+I Writeback_Shared_Data 0 <--
+I Writeback_All_Tokens 29
+I Writeback_Owned 0 <--
+I Data_Shared 0 <--
+I Data_Owner 0 <--
+I Data_All_Tokens 0 <--
+I Ack 0 <--
+I Persistent_GETX 0 <--
+I Persistent_GETS 0 <--
+I Own_Lock_or_Unlock 0 <--
+
+S L1_GETS 0 <--
+S L1_GETS_Last_Token 0 <--
+S L1_GETX 0 <--
+S L1_INV 0 <--
+S Transient_GETX 0 <--
+S Transient_GETS 0 <--
+S Transient_GETS_Last_Token 0 <--
+S L2_Replacement 0 <--
+S Writeback_Tokens 0 <--
+S Writeback_Shared_Data 0 <--
+S Writeback_All_Tokens 0 <--
+S Writeback_Owned 0 <--
+S Data_Shared 0 <--
+S Data_Owner 0 <--
+S Data_All_Tokens 0 <--
+S Ack 0 <--
+S Persistent_GETX 0 <--
+S Persistent_GETS 0 <--
+S Own_Lock_or_Unlock 0 <--
+
+O L1_GETS 0 <--
+O L1_GETS_Last_Token 0 <--
+O L1_GETX 0 <--
+O L1_INV 0 <--
+O Transient_GETX 0 <--
+O Transient_GETS 0 <--
+O Transient_GETS_Last_Token 0 <--
+O L2_Replacement 1
+O Writeback_Tokens 0 <--
+O Writeback_Shared_Data 0 <--
+O Writeback_All_Tokens 3
+O Data_Shared 0 <--
+O Data_All_Tokens 0 <--
+O Ack 0 <--
+O Ack_All_Tokens 0 <--
+O Persistent_GETX 0 <--
+O Persistent_GETS 0 <--
+O Own_Lock_or_Unlock 0 <--
+
+M L1_GETS 4
+M L1_GETX 32
+M L1_INV 0 <--
+M Transient_GETX 0 <--
+M Transient_GETS 0 <--
+M L2_Replacement 804
+M Persistent_GETX 9
+M Persistent_GETS 3
+M Own_Lock_or_Unlock 0 <--
+
+I_L L1_GETS 0 <--
+I_L L1_GETX 0 <--
+I_L L1_INV 0 <--
+I_L Transient_GETX 0 <--
+I_L Transient_GETS 0 <--
+I_L Transient_GETS_Last_Token 0 <--
+I_L L2_Replacement 0 <--
+I_L Writeback_Tokens 0 <--
+I_L Writeback_Shared_Data 0 <--
+I_L Writeback_All_Tokens 48
+I_L Writeback_Owned 0 <--
+I_L Data_Shared 0 <--
+I_L Data_Owner 0 <--
+I_L Data_All_Tokens 0 <--
+I_L Ack 0 <--
+I_L Persistent_GETX 146
+I_L Persistent_GETS 15
+I_L Own_Lock_or_Unlock 12
+
+S_L L1_GETS 0 <--
+S_L L1_GETS_Last_Token 0 <--
+S_L L1_GETX 0 <--
+S_L L1_INV 0 <--
+S_L Transient_GETX 0 <--
+S_L Transient_GETS 0 <--
+S_L Transient_GETS_Last_Token 0 <--
+S_L L2_Replacement 0 <--
+S_L Writeback_Tokens 0 <--
+S_L Writeback_Shared_Data 0 <--
+S_L Writeback_All_Tokens 0 <--
+S_L Writeback_Owned 0 <--
+S_L Data_Shared 0 <--
+S_L Data_Owner 0 <--
+S_L Data_All_Tokens 0 <--
+S_L Ack 0 <--
+S_L Persistent_GETX 0 <--
+S_L Persistent_GETS 0 <--
+S_L Own_Lock_or_Unlock 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+ memory_total_requests: 1662
+ memory_reads: 871
+ memory_writes: 791
+ memory_refreshes: 588
+ memory_total_request_delays: 1142
+ memory_delays_per_request: 0.687124
+ memory_delays_in_input_queue: 162
+ memory_delays_behind_head_of_bank_queue: 4
+ memory_delays_stalled_at_head_of_bank_queue: 976
+ memory_stalls_for_bank_busy: 236
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 70
+ memory_stalls_for_bus: 373
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 222
+ memory_stalls_for_read_read_turnaround: 75
+ accesses_per_bank: 61 57 44 91 60 64 57 46 59 42 55 67 56 38 38 46 42 46 55 49 45 45 38 58 35 54 39 48 56 43 72 56
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 844
+GETS 86
+Lockdown 173
+Unlockdown 173
+Own_Lock_or_Unlock 0
+Data_Owner 1
+Data_All_Tokens 798
+Ack_Owner 0
+Ack_Owner_All_Tokens 74
+Tokens 0
+Ack_All_Tokens 1
+Request_Timeout 0
+Memory_Data 870
+Memory_Ack 790
+DMA_READ 0
+DMA_WRITE 0
+DMA_WRITE_All_Tokens 0
+
+ - Transitions -
+O GETX 782
+O GETS 86
+O Lockdown 3
+O Own_Lock_or_Unlock 0 <--
+O Data_Owner 0 <--
+O Data_All_Tokens 0 <--
+O Tokens 0 <--
+O Ack_All_Tokens 1
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+O DMA_WRITE_All_Tokens 0 <--
+
+NO GETX 0 <--
+NO GETS 0 <--
+NO Lockdown 154
+NO Own_Lock_or_Unlock 0 <--
+NO Data_Owner 1
+NO Data_All_Tokens 790
+NO Ack_Owner 0 <--
+NO Ack_Owner_All_Tokens 74
+NO Tokens 0 <--
+NO DMA_READ 0 <--
+NO DMA_WRITE 0 <--
+
+L GETX 3
+L GETS 0 <--
+L Lockdown 0 <--
+L Unlockdown 173
+L Own_Lock_or_Unlock 0 <--
+L Data_Owner 0 <--
+L Data_All_Tokens 8
+L Ack_Owner 0 <--
+L Ack_Owner_All_Tokens 0 <--
+L Tokens 0 <--
+L DMA_READ 0 <--
+L DMA_WRITE 0 <--
+
+O_W GETX 21
+O_W GETS 0 <--
+O_W Lockdown 0 <--
+O_W Unlockdown 0 <--
+O_W Own_Lock_or_Unlock 0 <--
+O_W Data_Owner 0 <--
+O_W Ack_Owner 0 <--
+O_W Tokens 0 <--
+O_W Ack_All_Tokens 0 <--
+O_W Memory_Data 0 <--
+O_W Memory_Ack 790
+O_W DMA_READ 0 <--
+O_W DMA_WRITE 0 <--
+
+L_O_W GETX 38
+L_O_W GETS 0 <--
+L_O_W Lockdown 0 <--
+L_O_W Unlockdown 0 <--
+L_O_W Own_Lock_or_Unlock 0 <--
+L_O_W Data_Owner 0 <--
+L_O_W Ack_Owner 0 <--
+L_O_W Tokens 0 <--
+L_O_W Ack_All_Tokens 0 <--
+L_O_W Memory_Data 3
+L_O_W Memory_Ack 0 <--
+L_O_W DMA_READ 0 <--
+L_O_W DMA_WRITE 0 <--
+
+L_NO_W GETX 0 <--
+L_NO_W GETS 0 <--
+L_NO_W Lockdown 0 <--
+L_NO_W Unlockdown 0 <--
+L_NO_W Own_Lock_or_Unlock 0 <--
+L_NO_W Data_Owner 0 <--
+L_NO_W Ack_Owner 0 <--
+L_NO_W Tokens 0 <--
+L_NO_W Ack_All_Tokens 0 <--
+L_NO_W Memory_Data 16
+L_NO_W DMA_READ 0 <--
+L_NO_W DMA_WRITE 0 <--
+
+DR_L_W GETX 0 <--
+DR_L_W GETS 0 <--
+DR_L_W Lockdown 0 <--
+DR_L_W Unlockdown 0 <--
+DR_L_W Own_Lock_or_Unlock 0 <--
+DR_L_W Data_Owner 0 <--
+DR_L_W Ack_Owner 0 <--
+DR_L_W Tokens 0 <--
+DR_L_W Ack_All_Tokens 0 <--
+DR_L_W Request_Timeout 0 <--
+DR_L_W Memory_Data 0 <--
+DR_L_W DMA_READ 0 <--
+DR_L_W DMA_WRITE 0 <--
+
+NO_W GETX 0 <--
+NO_W GETS 0 <--
+NO_W Lockdown 16
+NO_W Unlockdown 0 <--
+NO_W Own_Lock_or_Unlock 0 <--
+NO_W Data_Owner 0 <--
+NO_W Ack_Owner 0 <--
+NO_W Tokens 0 <--
+NO_W Ack_All_Tokens 0 <--
+NO_W Memory_Data 851
+NO_W DMA_READ 0 <--
+NO_W DMA_WRITE 0 <--
+
+O_DW_W GETX 0 <--
+O_DW_W GETS 0 <--
+O_DW_W Data_Owner 0 <--
+O_DW_W Ack_Owner 0 <--
+O_DW_W Tokens 0 <--
+O_DW_W Ack_All_Tokens 0 <--
+O_DW_W Memory_Ack 0 <--
+O_DW_W DMA_READ 0 <--
+O_DW_W DMA_WRITE 0 <--
+
+O_DR_W GETX 0 <--
+O_DR_W GETS 0 <--
+O_DR_W Lockdown 0 <--
+O_DR_W Unlockdown 0 <--
+O_DR_W Own_Lock_or_Unlock 0 <--
+O_DR_W Data_Owner 0 <--
+O_DR_W Ack_Owner 0 <--
+O_DR_W Tokens 0 <--
+O_DR_W Ack_All_Tokens 0 <--
+O_DR_W Memory_Data 0 <--
+O_DR_W DMA_READ 0 <--
+O_DR_W DMA_WRITE 0 <--
+
+O_DW GETX 0 <--
+O_DW GETS 0 <--
+O_DW Lockdown 0 <--
+O_DW Own_Lock_or_Unlock 0 <--
+O_DW Data_Owner 0 <--
+O_DW Data_All_Tokens 0 <--
+O_DW Ack_Owner 0 <--
+O_DW Ack_Owner_All_Tokens 0 <--
+O_DW Tokens 0 <--
+O_DW Ack_All_Tokens 0 <--
+O_DW DMA_READ 0 <--
+O_DW DMA_WRITE 0 <--
+
+NO_DW GETX 0 <--
+NO_DW GETS 0 <--
+NO_DW Lockdown 0 <--
+NO_DW Own_Lock_or_Unlock 0 <--
+NO_DW Data_Owner 0 <--
+NO_DW Data_All_Tokens 0 <--
+NO_DW Tokens 0 <--
+NO_DW Request_Timeout 0 <--
+NO_DW DMA_READ 0 <--
+NO_DW DMA_WRITE 0 <--
+
+NO_DR GETX 0 <--
+NO_DR GETS 0 <--
+NO_DR Lockdown 0 <--
+NO_DR Own_Lock_or_Unlock 0 <--
+NO_DR Data_Owner 0 <--
+NO_DR Data_All_Tokens 0 <--
+NO_DR Tokens 0 <--
+NO_DR Request_Timeout 0 <--
+NO_DR DMA_READ 0 <--
+NO_DR DMA_WRITE 0 <--
+
+DW_L GETX 0 <--
+DW_L GETS 0 <--
+DW_L Lockdown 0 <--
+DW_L Unlockdown 0 <--
+DW_L Own_Lock_or_Unlock 0 <--
+DW_L Data_Owner 0 <--
+DW_L Data_All_Tokens 0 <--
+DW_L Ack_Owner 0 <--
+DW_L Ack_Owner_All_Tokens 0 <--
+DW_L Tokens 0 <--
+DW_L Request_Timeout 0 <--
+DW_L DMA_READ 0 <--
+DW_L DMA_WRITE 0 <--
+
+DR_L GETX 0 <--
+DR_L GETS 0 <--
+DR_L Lockdown 0 <--
+DR_L Unlockdown 0 <--
+DR_L Own_Lock_or_Unlock 0 <--
+DR_L Data_Owner 0 <--
+DR_L Data_All_Tokens 0 <--
+DR_L Ack_Owner 0 <--
+DR_L Ack_Owner_All_Tokens 0 <--
+DR_L Tokens 0 <--
+DR_L Request_Timeout 0 <--
+DR_L DMA_READ 0 <--
+DR_L DMA_WRITE 0 <--
+
--- /dev/null
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 27 2010 22:01:26
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 27 2010 22:01:59
+M5 executing on svvint04
+command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 282171 because Ruby Tester completed
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 213472 # Number of bytes of host memory used
+host_seconds 0.43 # Real time elapsed on the host
+host_tick_rate 656167 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.000282 # Number of seconds simulated
+sim_ticks 282171 # Number of ticks simulated
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=true
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
+buffer_size=0
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=root.cpuPort[0]
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+memory_controller_latency=12
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 1
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: active, unordered
+virtual_net_4: active, ordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/27/2010 22:06:46
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
+
+Virtual_time_in_seconds: 0.52
+Virtual_time_in_minutes: 0.00866667
+Virtual_time_in_hours: 0.000144444
+Virtual_time_in_days: 6.01852e-06
+
+Ruby_current_time: 225461
+Ruby_start_time: 0
+Ruby_cycles: 225461
+
+mbytes_resident: 29.9023
+mbytes_total: 29.9102
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 225462 [ 225462 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1003 average: 15.7986 | standard deviation: 1.13201 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 81 907 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 128 max: 18718 count: 988 average: 3556.09 | standard deviation: 5195.8 | 86 11 48 73 73 53 86 67 49 36 30 35 19 12 10 8 6 12 9 7 3 4 7 1 5 3 4 2 4 1 4 1 3 3 1 1 3 4 1 2 1 0 1 0 0 0 0 2 0 1 2 2 0 0 0 2 0 0 0 0 0 0 0 2 1 2 0 0 0 1 0 1 1 0 1 5 2 1 0 0 3 2 3 0 2 2 1 2 2 2 2 1 2 4 3 0 1 4 6 6 2 2 3 7 4 3 5 3 2 2 3 6 4 1 5 3 3 6 6 2 4 4 4 3 4 4 6 4 0 1 0 1 0 4 1 1 1 0 0 0 2 2 3 1 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 128 max: 17088 count: 100 average: 3614.25 | standard deviation: 5411.44 | 9 2 4 7 8 6 10 6 5 4 2 4 3 2 0 0 0 3 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 0 2 0 0 0 1 0 2 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 128 max: 18718 count: 888 average: 3549.54 | standard deviation: 5174.08 | 77 9 44 66 65 47 76 61 44 32 28 31 16 10 10 8 6 9 9 6 2 4 6 1 5 3 4 2 4 1 4 1 3 2 1 0 3 4 1 2 1 0 1 0 0 0 0 2 0 1 2 2 0 0 0 2 0 0 0 0 0 0 0 2 1 2 0 0 0 1 0 1 1 0 1 5 2 1 0 0 2 2 3 0 2 1 1 2 2 2 2 1 2 4 3 0 1 3 6 5 1 1 3 6 3 3 5 2 2 2 3 4 4 1 5 2 3 4 5 2 3 3 4 3 4 4 6 4 0 1 0 0 0 2 1 1 1 0 0 0 2 2 3 1 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 6560
+page_faults: 1853
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.133285
+ links_utilized_percent_switch_0_link_0: 0.0488166 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.217754 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 881 63432 [ 0 881 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 876 7008 [ 0 0 876 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 882 7056 [ 0 0 0 882 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 788 56736 [ 788 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 965 7720 [ 88 0 0 877 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 880 7040 [ 880 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.124828
+ links_utilized_percent_switch_1_link_0: 0.0543886 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.195267 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 882 7056 [ 0 0 0 882 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 787 56664 [ 787 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 965 7720 [ 88 0 0 877 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Unblock_Control: 880 7040 [ 880 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 881 63432 [ 0 881 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 876 7008 [ 0 0 876 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.20641
+ links_utilized_percent_switch_2_link_0: 0.195267 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.217554 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 881 63432 [ 0 881 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 876 7008 [ 0 0 876 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 882 7056 [ 0 0 0 882 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Data: 787 56664 [ 787 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Control: 965 7720 [ 88 0 0 877 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Unblock_Control: 880 7040 [ 880 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 882
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 882
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 10.3175%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 89.6825%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 882 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 4 count: 882 average: 1.30952 | standard deviation: 0.913389 | 0 791 0 0 91 ]
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan
+
+ system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 101
+Ifetch 0
+Store 891
+L2_Replacement 877
+L1_to_L2 322098
+L2_to_L1D 26
+L2_to_L1I 0
+Other_GETX 0
+Other_GETS 0
+Ack 0
+Shared_Ack 0
+Data 0
+Shared_Data 0
+Exclusive_Data 881
+Writeback_Ack 876
+Writeback_Nack 0
+All_acks 0
+All_acks_no_sharers 881
+
+ - Transitions -
+I Load 91
+I Ifetch 0 <--
+I Store 791
+I L2_Replacement 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I Other_GETX 0 <--
+I Other_GETS 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L2_Replacement 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S Other_GETX 0 <--
+S Other_GETS 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L2_Replacement 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O Other_GETX 0 <--
+O Other_GETS 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L2_Replacement 88
+M L1_to_L2 88
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M Other_GETX 0 <--
+M Other_GETS 0 <--
+
+MM Load 10
+MM Ifetch 0 <--
+MM Store 95
+MM L2_Replacement 789
+MM L1_to_L2 817
+MM L2_to_L1D 26
+MM L2_to_L1I 0 <--
+MM Other_GETX 0 <--
+MM Other_GETS 0 <--
+
+IM Load 0 <--
+IM Ifetch 0 <--
+IM Store 0 <--
+IM L2_Replacement 0 <--
+IM L1_to_L2 282750
+IM Other_GETX 0 <--
+IM Other_GETS 0 <--
+IM Ack 0 <--
+IM Data 0 <--
+IM Exclusive_Data 791
+
+SM Load 0 <--
+SM Ifetch 0 <--
+SM Store 0 <--
+SM L2_Replacement 0 <--
+SM L1_to_L2 0 <--
+SM Other_GETX 0 <--
+SM Other_GETS 0 <--
+SM Ack 0 <--
+SM Data 0 <--
+
+OM Load 0 <--
+OM Ifetch 0 <--
+OM Store 0 <--
+OM L2_Replacement 0 <--
+OM L1_to_L2 0 <--
+OM Other_GETX 0 <--
+OM Other_GETS 0 <--
+OM Ack 0 <--
+OM All_acks 0 <--
+OM All_acks_no_sharers 0 <--
+
+ISM Load 0 <--
+ISM Ifetch 0 <--
+ISM Store 0 <--
+ISM L2_Replacement 0 <--
+ISM L1_to_L2 0 <--
+ISM Ack 0 <--
+ISM All_acks_no_sharers 0 <--
+
+M_W Load 0 <--
+M_W Ifetch 0 <--
+M_W Store 1
+M_W L2_Replacement 0 <--
+M_W L1_to_L2 975
+M_W Ack 0 <--
+M_W All_acks_no_sharers 89
+
+MM_W Load 0 <--
+MM_W Ifetch 0 <--
+MM_W Store 1
+MM_W L2_Replacement 0 <--
+MM_W L1_to_L2 10999
+MM_W Ack 0 <--
+MM_W All_acks_no_sharers 792
+
+IS Load 0 <--
+IS Ifetch 0 <--
+IS Store 0 <--
+IS L2_Replacement 0 <--
+IS L1_to_L2 26469
+IS Other_GETX 0 <--
+IS Other_GETS 0 <--
+IS Ack 0 <--
+IS Shared_Ack 0 <--
+IS Data 0 <--
+IS Shared_Data 0 <--
+IS Exclusive_Data 90
+
+SS Load 0 <--
+SS Ifetch 0 <--
+SS Store 0 <--
+SS L2_Replacement 0 <--
+SS L1_to_L2 0 <--
+SS Ack 0 <--
+SS Shared_Ack 0 <--
+SS All_acks 0 <--
+SS All_acks_no_sharers 0 <--
+
+OI Load 0 <--
+OI Ifetch 0 <--
+OI Store 0 <--
+OI L2_Replacement 0 <--
+OI L1_to_L2 0 <--
+OI Other_GETX 0 <--
+OI Other_GETS 0 <--
+OI Writeback_Ack 0 <--
+
+MI Load 0 <--
+MI Ifetch 0 <--
+MI Store 3
+MI L2_Replacement 0 <--
+MI L1_to_L2 0 <--
+MI Other_GETX 0 <--
+MI Other_GETS 0 <--
+MI Writeback_Ack 876
+
+II Load 0 <--
+II Ifetch 0 <--
+II Store 0 <--
+II L2_Replacement 0 <--
+II L1_to_L2 0 <--
+II Other_GETX 0 <--
+II Other_GETS 0 <--
+II Writeback_Ack 0 <--
+II Writeback_Nack 0 <--
+
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+ memory_total_requests: 1668
+ memory_reads: 881
+ memory_writes: 787
+ memory_refreshes: 470
+ memory_total_request_delays: 1066
+ memory_delays_per_request: 0.639089
+ memory_delays_in_input_queue: 148
+ memory_delays_behind_head_of_bank_queue: 0
+ memory_delays_stalled_at_head_of_bank_queue: 918
+ memory_stalls_for_bank_busy: 195
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 77
+ memory_stalls_for_bus: 376
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 154
+ memory_stalls_for_read_read_turnaround: 116
+ accesses_per_bank: 46 46 48 83 76 73 83 52 38 57 51 55 52 49 41 48 49 44 44 60 51 41 58 49 42 38 55 47 50 52 39 51
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 895
+GETS 90
+PUT 1525
+Unblock 878
+Writeback_Clean 0
+Writeback_Dirty 0
+Writeback_Exclusive_Clean 88
+Writeback_Exclusive_Dirty 787
+DMA_READ 0
+DMA_WRITE 0
+Memory_Data 881
+Memory_Ack 787
+Ack 0
+Shared_Ack 0
+Shared_Data 0
+Exclusive_Data 0
+All_acks_and_data 0
+All_acks_and_data_no_sharers 0
+
+ - Transitions -
+NO GETX 0 <--
+NO GETS 0 <--
+NO PUT 876
+NO DMA_READ 0 <--
+NO DMA_WRITE 0 <--
+
+O GETX 0 <--
+O GETS 0 <--
+O PUT 0 <--
+O DMA_READ 0 <--
+O DMA_WRITE 0 <--
+
+E GETX 791
+E GETS 90
+E PUT 0 <--
+E DMA_READ 0 <--
+E DMA_WRITE 0 <--
+
+NO_B GETX 0 <--
+NO_B GETS 0 <--
+NO_B PUT 649
+NO_B Unblock 878
+NO_B DMA_READ 0 <--
+NO_B DMA_WRITE 0 <--
+
+O_B GETX 0 <--
+O_B GETS 0 <--
+O_B PUT 0 <--
+O_B Unblock 0 <--
+O_B DMA_READ 0 <--
+O_B DMA_WRITE 0 <--
+
+NO_B_W GETX 0 <--
+NO_B_W GETS 0 <--
+NO_B_W PUT 0 <--
+NO_B_W Unblock 0 <--
+NO_B_W DMA_READ 0 <--
+NO_B_W DMA_WRITE 0 <--
+NO_B_W Memory_Data 881
+
+O_B_W GETX 0 <--
+O_B_W GETS 0 <--
+O_B_W PUT 0 <--
+O_B_W Unblock 0 <--
+O_B_W DMA_READ 0 <--
+O_B_W DMA_WRITE 0 <--
+O_B_W Memory_Data 0 <--
+
+NO_W GETX 0 <--
+NO_W GETS 0 <--
+NO_W PUT 0 <--
+NO_W DMA_READ 0 <--
+NO_W DMA_WRITE 0 <--
+NO_W Memory_Data 0 <--
+
+O_W GETX 0 <--
+O_W GETS 0 <--
+O_W PUT 0 <--
+O_W DMA_READ 0 <--
+O_W DMA_WRITE 0 <--
+O_W Memory_Data 0 <--
+
+NO_DW_B_W GETX 0 <--
+NO_DW_B_W GETS 0 <--
+NO_DW_B_W PUT 0 <--
+NO_DW_B_W DMA_READ 0 <--
+NO_DW_B_W DMA_WRITE 0 <--
+NO_DW_B_W Ack 0 <--
+NO_DW_B_W Exclusive_Data 0 <--
+NO_DW_B_W All_acks_and_data_no_sharers 0 <--
+
+NO_DR_B_W GETX 0 <--
+NO_DR_B_W GETS 0 <--
+NO_DR_B_W PUT 0 <--
+NO_DR_B_W DMA_READ 0 <--
+NO_DR_B_W DMA_WRITE 0 <--
+NO_DR_B_W Memory_Data 0 <--
+NO_DR_B_W Ack 0 <--
+NO_DR_B_W Shared_Ack 0 <--
+NO_DR_B_W Shared_Data 0 <--
+NO_DR_B_W Exclusive_Data 0 <--
+
+NO_DR_B_D GETX 0 <--
+NO_DR_B_D GETS 0 <--
+NO_DR_B_D PUT 0 <--
+NO_DR_B_D DMA_READ 0 <--
+NO_DR_B_D DMA_WRITE 0 <--
+NO_DR_B_D Ack 0 <--
+NO_DR_B_D Shared_Ack 0 <--
+NO_DR_B_D Shared_Data 0 <--
+NO_DR_B_D Exclusive_Data 0 <--
+NO_DR_B_D All_acks_and_data 0 <--
+NO_DR_B_D All_acks_and_data_no_sharers 0 <--
+
+NO_DR_B GETX 0 <--
+NO_DR_B GETS 0 <--
+NO_DR_B PUT 0 <--
+NO_DR_B DMA_READ 0 <--
+NO_DR_B DMA_WRITE 0 <--
+NO_DR_B Ack 0 <--
+NO_DR_B Shared_Ack 0 <--
+NO_DR_B Shared_Data 0 <--
+NO_DR_B Exclusive_Data 0 <--
+NO_DR_B All_acks_and_data 0 <--
+NO_DR_B All_acks_and_data_no_sharers 0 <--
+
+NO_DW_W GETX 0 <--
+NO_DW_W GETS 0 <--
+NO_DW_W PUT 0 <--
+NO_DW_W DMA_READ 0 <--
+NO_DW_W DMA_WRITE 0 <--
+NO_DW_W Memory_Ack 0 <--
+
+O_DR_B_W GETX 0 <--
+O_DR_B_W GETS 0 <--
+O_DR_B_W PUT 0 <--
+O_DR_B_W DMA_READ 0 <--
+O_DR_B_W DMA_WRITE 0 <--
+O_DR_B_W Memory_Data 0 <--
+
+O_DR_B GETX 0 <--
+O_DR_B GETS 0 <--
+O_DR_B PUT 0 <--
+O_DR_B DMA_READ 0 <--
+O_DR_B DMA_WRITE 0 <--
+O_DR_B Ack 0 <--
+O_DR_B All_acks_and_data_no_sharers 0 <--
+
+WB GETX 35
+WB GETS 0 <--
+WB PUT 0 <--
+WB Unblock 0 <--
+WB Writeback_Clean 0 <--
+WB Writeback_Dirty 0 <--
+WB Writeback_Exclusive_Clean 88
+WB Writeback_Exclusive_Dirty 787
+WB DMA_READ 0 <--
+WB DMA_WRITE 0 <--
+
+WB_O_W GETX 0 <--
+WB_O_W GETS 0 <--
+WB_O_W PUT 0 <--
+WB_O_W DMA_READ 0 <--
+WB_O_W DMA_WRITE 0 <--
+WB_O_W Memory_Ack 0 <--
+
+WB_E_W GETX 69
+WB_E_W GETS 0 <--
+WB_E_W PUT 0 <--
+WB_E_W DMA_READ 0 <--
+WB_E_W DMA_WRITE 0 <--
+WB_E_W Memory_Ack 787
+
--- /dev/null
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 27 2010 22:05:53
+M5 revision 6068d4fc30d3 6931 default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 27 2010 22:06:45
+M5 executing on svvint06
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 225461 because Ruby Tester completed
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 210820 # Number of bytes of host memory used
+host_seconds 0.44 # Real time elapsed on the host
+host_tick_rate 512394 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.000225 # Number of seconds simulated
+sim_ticks 225461 # Number of ticks simulated
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=physmem ruby
+mem_mode=timing
+physmem=system.physmem
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=true
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=root.cpuPort[0]
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
+
--- /dev/null
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+ random_seed: 1234
+ randomization: 1
+ cycle_period: 1
+ block_size_bytes: 64
+ block_size_bits: 6
+ memory_size_bytes: 134217728
+ memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology:
+
+virtual_net_0: active, ordered
+virtual_net_1: active, ordered
+virtual_net_2: active, ordered
+virtual_net_3: inactive
+virtual_net_4: active, ordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/27/2010 21:57:17
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
+
+Virtual_time_in_seconds: 0.23
+Virtual_time_in_minutes: 0.00383333
+Virtual_time_in_hours: 6.38889e-05
+Virtual_time_in_days: 2.66204e-06
+
+Ruby_current_time: 271191
+Ruby_start_time: 0
+Ruby_cycles: 271191
+
+mbytes_resident: 30.8242
+mbytes_total: 30.832
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 271192 [ 271192 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 971 average: 15.7848 | standard deviation: 1.15276 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 86 869 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 32 max: 5966 count: 956 average: 4491.48 | standard deviation: 635.733 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 1 0 0 0 0 2 1 0 1 4 1 0 3 1 0 1 2 2 1 2 4 3 6 6 2 5 14 5 6 8 6 7 6 10 8 13 14 13 7 15 9 17 24 19 17 14 19 25 18 19 19 20 24 15 27 24 21 30 29 21 20 22 15 23 16 24 17 22 12 11 14 15 10 13 12 7 13 7 11 11 3 7 10 3 5 7 0 2 5 3 0 3 3 1 1 3 0 0 1 1 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 32 max: 5629 count: 100 average: 4532.09 | standard deviation: 502.331 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 2 1 0 1 1 0 0 0 1 2 1 1 0 1 3 1 2 0 2 2 2 1 2 2 2 1 2 2 3 1 1 5 3 1 2 4 4 2 5 1 2 2 4 2 3 3 1 3 0 0 1 1 0 2 0 2 1 0 0 2 0 0 0 0 1 1 ]
+miss_latency_3: [binsize: 32 max: 5966 count: 856 average: 4486.74 | standard deviation: 649.61 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 1 0 0 0 0 2 1 0 1 4 1 0 3 0 0 0 2 2 1 2 4 3 6 4 1 5 13 4 6 8 6 6 4 9 7 13 13 10 6 13 9 15 22 17 16 12 17 23 17 17 17 17 23 14 22 21 20 28 25 17 18 17 14 21 14 20 15 19 9 10 11 15 10 12 11 7 11 7 9 10 3 7 8 3 5 7 0 1 4 3 0 3 3 1 1 3 0 0 1 1 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 1839 average: 0 | standard deviation: 0 | 1839 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1839 average: 0 | standard deviation: 0 | 1839 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 921 average: 0 | standard deviation: 0 | 921 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 918 average: 0 | standard deviation: 0 | 918 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 6767
+page_faults: 1920
+swaps: 0
+block_inputs: 0
+block_outputs: 0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 0.105956
+ links_utilized_percent_switch_0_link_0: 0.0424378 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.169475 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Response_Data: 921 66312 [ 0 921 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 918 7344 [ 0 0 918 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 921 7368 [ 921 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Data: 919 66168 [ 919 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 0.106039
+ links_utilized_percent_switch_1_link_0: 0.0423272 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.169751 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Control: 921 7368 [ 921 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Data: 918 66096 [ 918 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 921 66312 [ 0 921 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 918 7344 [ 0 0 918 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.16953
+ links_utilized_percent_switch_2_link_0: 0.169751 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.169309 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 921 66312 [ 0 921 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 918 7344 [ 0 0 918 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 921 7368 [ 921 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Data: 918 66096 [ 918 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 923
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 923
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 10.9426%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 89.0574%
+
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 923 100%
+ system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 923 average: 1.32828 | standard deviation: 0.937297 | 0 822 0 0 101 ]
+
+ --- L1Cache 0 ---
+ - Event Counts -
+Load 101
+Ifetch 0
+Store 857
+Data 921
+Fwd_GETX 0
+Inv 0
+Replacement 920
+Writeback_Ack 918
+Writeback_Nack 0
+
+ - Transitions -
+I Load 101
+I Ifetch 0 <--
+I Store 822
+I Inv 0 <--
+I Replacement 0 <--
+
+II Writeback_Nack 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 35
+M Fwd_GETX 0 <--
+M Inv 0 <--
+M Replacement 920
+
+MI Fwd_GETX 0 <--
+MI Inv 0 <--
+MI Writeback_Ack 918
+MI Writeback_Nack 0 <--
+
+MII Fwd_GETX 0 <--
+
+IS Data 100
+
+IM Data 821
+
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+ memory_total_requests: 1839
+ memory_reads: 921
+ memory_writes: 918
+ memory_refreshes: 565
+ memory_total_request_delays: 2859
+ memory_delays_per_request: 1.55465
+ memory_delays_in_input_queue: 719
+ memory_delays_behind_head_of_bank_queue: 15
+ memory_delays_stalled_at_head_of_bank_queue: 2125
+ memory_stalls_for_bank_busy: 289
+ memory_stalls_for_random_busy: 0
+ memory_stalls_for_anti_starvation: 0
+ memory_stalls_for_arbitration: 280
+ memory_stalls_for_bus: 928
+ memory_stalls_for_tfaw: 0
+ memory_stalls_for_read_write_turnaround: 519
+ memory_stalls_for_read_read_turnaround: 109
+ accesses_per_bank: 62 46 62 86 113 64 68 60 64 64 56 62 48 40 46 38 62 50 52 52 58 61 56 54 52 58 58 56 51 54 52 34
+
+ --- Directory 0 ---
+ - Event Counts -
+GETX 921
+GETS 0
+PUTX 918
+PUTX_NotOwner 0
+DMA_READ 0
+DMA_WRITE 0
+Memory_Data 921
+Memory_Ack 918
+
+ - Transitions -
+I GETX 921
+I PUTX_NotOwner 0 <--
+I DMA_READ 0 <--
+I DMA_WRITE 0 <--
+
+M GETX 0 <--
+M PUTX 918
+M PUTX_NotOwner 0 <--
+M DMA_READ 0 <--
+M DMA_WRITE 0 <--
+
+M_DRD GETX 0 <--
+M_DRD PUTX 0 <--
+
+M_DWR GETX 0 <--
+M_DWR PUTX 0 <--
+
+M_DWRI GETX 0 <--
+M_DWRI Memory_Ack 0 <--
+
+M_DRDI GETX 0 <--
+M_DRDI Memory_Ack 0 <--
+
+IM GETX 0 <--
+IM GETS 0 <--
+IM PUTX 0 <--
+IM PUTX_NotOwner 0 <--
+IM DMA_READ 0 <--
+IM DMA_WRITE 0 <--
+IM Memory_Data 921
+
+MI GETX 0 <--
+MI GETS 0 <--
+MI PUTX 0 <--
+MI PUTX_NotOwner 0 <--
+MI DMA_READ 0 <--
+MI DMA_WRITE 0 <--
+MI Memory_Ack 918
+
+ID GETX 0 <--
+ID GETS 0 <--
+ID PUTX 0 <--
+ID PUTX_NotOwner 0 <--
+ID DMA_READ 0 <--
+ID DMA_WRITE 0 <--
+ID Memory_Data 0 <--
+
+ID_W GETX 0 <--
+ID_W GETS 0 <--
+ID_W PUTX 0 <--
+ID_W PUTX_NotOwner 0 <--
+ID_W DMA_READ 0 <--
+ID_W DMA_WRITE 0 <--
+ID_W Memory_Ack 0 <--
+
--- /dev/null
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 27 2010 17:26:29
+M5 revision 6068d4fc30d3 6931 default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 27 2010 21:57:16
+M5 executing on svvint07
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 271191 because Ruby Tester completed
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 213104 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 3873825 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.000271 # Number of seconds simulated
+sim_ticks 271191 # Number of ticks simulated
+
+---------- End Simulation Statistics ----------
--- /dev/null
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+
import os
import sys
+import re
+import string
from os.path import join as joinpath
# build configuration
sys.path.append(joinpath(tests_root, 'configs'))
-execfile(joinpath(tests_root, 'configs', config + '.py'))
+test_filename = config
+# for ruby configurations, remove the protocol name from the test filename
+if re.search('-ruby', test_filename):
+ test_filename = test_filename.split('-ruby')[0]+'-ruby'
+execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
# set default maxtick... script can override
# -1 means run forever
default=False,
help='echo commands before executing')
optparser.add_option('--builds', dest='builds',
- default='ALPHA_SE,ALPHA_FS,MIPS_SE,' + \
+ default='ALPHA_SE,ALPHA_SE_MOESI_hammer,' \
+ 'ALPHA_SE_MESI_CMP_directory,' \
+ 'ALPHA_SE_MOESI_CMP_directory,' \
+ 'ALPHA_SE_MOESI_CMP_token,' \
+ 'ALPHA_FS,MIPS_SE,' \
'POWER_SE,SPARC_SE,SPARC_FS,X86_SE,ARM_SE',
help='comma-separated list of build targets to test '
" (default: '%default')" )
projects / gem5.git / commitdiff