# Sequencer -------------------------------------------------------
cycles = Signal(8)
first = Signal()
+ nfirst = Signal() # not-first
count_inc = Signal()
dbg_cyc = Signal(8)
+ comb += nfirst.eq(~first) # convenience
# when not idle run a cycles counter
with m.If(count_inc):
sync += cycles.eq(0)
# On last state, see if we can continue the burst
# or if we should end it.
- with m.If(n == (states - 1)):
+ if n == states - 1:
sync += first.eq(0)
# Continue burst when consecutive access ready.
with m.If(bus.stb & bus.cyc &
# Early Write Ack (to allow bursting).
comb += bus.ack.eq(bus.we)
# Else end the burst.
- with m.Elif(bus_we | ~first):
+ with m.Elif(bus_we | nfirst):
m.next = "IDLE"
sync += cycles.eq(0)
# Read Ack (when dat_r ready).
- with m.If((n == 0) & ~first):
- comb += bus.ack.eq(~bus_we)
+ if n == 0:
+ comb += bus.ack.eq(nfirst & ~bus_we)
return m