imported patch pagewalker.patch

--HG--
extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 691f92e2ec33cfc674a12f159ce760b6a43df23f..ee5ed0774b1e72e777106345e9caf8617a3b722e 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -101,6 +101,8 @@ class BaseCPU(SimObject):
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
     _mem_ports = []
+    if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
+        _mem_ports = ["itb.walker.port", "dtb.walker.port"]
 
     def connectMemPorts(self, bus):
         for p in self._mem_ports:
@@ -108,12 +110,14 @@ class BaseCPU(SimObject):
                 exec('self.%s = bus.port' % p)
 
     def addPrivateSplitL1Caches(self, ic, dc):
-        assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
+        assert(len(self._mem_ports) < 6)
         self.icache = ic
         self.dcache = dc
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+        if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
+            self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
         self.addPrivateSplitL1Caches(ic, dc)

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 010c21e4a1dccb80a2de00a20c92cfe7033d0e9e..ad7b14be30ad5e7faab66f77b6bbe0dfed27ca08 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -466,9 +466,9 @@ BaseSimpleCPU::advancePC(Fault fault)
     if (fault != NoFault) {
         curMacroStaticInst = StaticInst::nullStaticInstPtr;
         predecoder.reset();
-        fault->invoke(tc);
         thread->setMicroPC(0);
         thread->setNextMicroPC(1);
+        fault->invoke(tc);
     } else {
         //If we're at the last micro op for this instruction
         if (curStaticInst && curStaticInst->isLastMicroop()) {