* Github Profile: [[https://github.com/Sanjay-A-Menon]]
* LinkedIn Profile: [[https://www.linkedin.com/in/sanjay-menon-91791815a]]
* Availability: ~6hrs/week
+
+## Samuel Falvo
+
+* Experience in amateur HDL projects (Kestrel-3 homebrew computer
+ concept; VDC-II core), Verilog (but not System Verilog), newbie at PCB
+ design. Extensive experience with test-driven development, Python, RISC-V
+ assembly language, and Forth. Very comfortable with nMigen, but still
+ learning things.
+* Interests: Forth, Common Lisp, Scheme, assembly language,
+ {Astro|Semiconductor-}physics, astronomy, martial arts, furry
+* Websites:
+ - https://hackaday.io/project/170581-vdc-ii ,
+ - https://kestrelcomputer.github.io/kestrel/ ,
+ - http://chiselapp.com/user/kc5tja/repository/kestrel-3/index
+* Public Repositories:
+ - https://github.com/sam-falvo ,
+ - https://github.com/kestrelcomputer
+* Availability: approximately 20 hrs/wk, circumstances permitting.
+