intel/isl: Support HIZ_CCS in emit_depth_stencil_hiz

v2. Remove undocumented CCS_E-only mode for depth. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 382c0ce22f555f6eb8f1ec75dee735513459f47c..e28ec836255f74d0bd35306ce4130f7b6a8443e0 100644 (file)
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -109,6 +109,11 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
       db.SurfaceQPitch =
          isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
 #endif
+
+#if GEN_GEN >= 12
+      db.DepthBufferCompressionEnable =
+         info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS;
+#endif
    }
 
 #if GEN_GEN == 5 || GEN_GEN == 6
@@ -177,8 +182,11 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
    };
 
    assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
-          info->hiz_usage == ISL_AUX_USAGE_HIZ);
-   if (info->hiz_usage == ISL_AUX_USAGE_HIZ) {
+          info->hiz_usage == ISL_AUX_USAGE_HIZ ||
+          info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS);
+   if (info->hiz_usage == ISL_AUX_USAGE_HIZ ||
+       info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS) {
+      assert(GEN_GEN >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ);
       db.HierarchicalDepthBufferEnable = true;
 
       hiz.SurfaceBaseAddress = info->hiz_address;