previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid
dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions
that were run, the sims are about 2x speedup from changeset 7726 which is the last change
since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
All Rights Reserved
-M5 compiled Feb 7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:47:38
-M5 executing on burrito
+M5 compiled Feb 18 2011 15:40:30
+M5 revision Unknown
+M5 started Feb 18 2011 18:53:22
+M5 executing on m55-001.pool
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 43686968500 because halt instruction encountered
+Exiting @ tick 43687852500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 106274 # Simulator instruction rate (inst/s)
-host_mem_usage 1642336 # Number of bytes of host memory used
-host_seconds 831.26 # Real time elapsed on the host
-host_tick_rate 52555245 # Simulator tick rate (ticks/s)
+host_inst_rate 140237 # Simulator instruction rate (inst/s)
+host_mem_usage 237028 # Number of bytes of host memory used
+host_seconds 629.94 # Real time elapsed on the host
+host_tick_rate 69352666 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 88340674 # Number of instructions simulated
-sim_seconds 0.043687 # Number of seconds simulated
-sim_ticks 43686968500 # Number of ticks simulated
+sim_insts 88340673 # Number of instructions simulated
+sim_seconds 0.043688 # Number of seconds simulated
+sim_ticks 43687852500 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 35033051 # Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct 40.125175 # BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits 4678518 # Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups 11659807 # Number of BTB lookups
+system.cpu.Branch-Predictor.BTBHitPct 40.125186 # BTB Hit Percentage
+system.cpu.Branch-Predictor.BTBHits 4678520 # Number of BTB hits
+system.cpu.Branch-Predictor.BTBLookups 11659809 # Number of BTB lookups
system.cpu.Branch-Predictor.RASInCorrect 1539 # Number of incorrect RAS predictions.
system.cpu.Branch-Predictor.condIncorrect 753993 # Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted 9173158 # Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups 14237669 # Number of BP lookups
+system.cpu.Branch-Predictor.condPredicted 9173160 # Number of conditional branches predicted
+system.cpu.Branch-Predictor.lookups 14237671 # Number of BP lookups
system.cpu.Branch-Predictor.predictedNotTaken 6139595 # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken 8098074 # Number of Branches Predicted As Taken (True).
+system.cpu.Branch-Predictor.predictedTaken 8098076 # Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS 1660495 # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions 53620617 # Number of Instructions Executed.
+system.cpu.Execution-Unit.executions 44841137 # Number of Instructions Executed.
system.cpu.Execution-Unit.mispredictPct 5.481801 # Percentage of Incorrect Branches Predicts
system.cpu.Execution-Unit.mispredicted 753993 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted 13000484 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predictedTakenIncorrect 203091 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 145605016 # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 93058135 # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 145605009 # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 93058128 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards 13517269 # Number of Registers Read Through Forwarding Logic
-system.cpu.activity 70.714707 # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards 13517276 # Number of Registers Read Through Forwarding Logic
+system.cpu.activity 70.715162 # Percentage of cycles cpu is active
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
system.cpu.comInts 30791227 # Number of Integer instructions committed
system.cpu.comLoads 20276638 # Number of Load instructions committed
-system.cpu.comNonSpec 4584 # Number of Non-Speculative instructions committed
+system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
system.cpu.comNops 8748916 # Number of Nop instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
-system.cpu.committedInsts 88340674 # Number of Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 88340674 # Number of Instructions Simulated (Total)
+system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.cpi 0.989057 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 0.989057 # CPI: Total CPI of All Threads
+system.cpu.cpi 0.989077 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 0.989077 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 43413.349504 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34421.543297 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34421.526841 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20182230 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4098567500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004656 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 94408 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 33642 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2091659500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2091658500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 50157.670646 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49503.458051 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 50157.576620 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49503.360543 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14405989 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 10402099000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 10402079500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.014192 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 207388 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 63810 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 7107607500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 7107593500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2727000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 48047.908190 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 45018.532475 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 48047.843576 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 45018.459069 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34588219 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 14500666500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 14500647000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.008650 # miss rate for demand accesses
system.cpu.dcache.demand_misses 301796 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 97452 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9199267000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 9199252000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.994103 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4071.844776 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 4071.844772 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 48047.908190 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 45018.532475 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 48047.843576 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 45018.459069 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34588219 # number of overall hits
-system.cpu.dcache.overall_miss_latency 14500666500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 14500647000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.008650 # miss rate for overall accesses
system.cpu.dcache.overall_misses 301796 # number of overall misses
system.cpu.dcache.overall_mshr_hits 97452 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 9199267000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 9199252000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4071.844776 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4071.844772 # Cycle average of tags in use
system.cpu.dcache.total_refs 34588219 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 497786000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 497796000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 161214 # number of writebacks
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
-system.cpu.icache.ReadReq_accesses 11384473 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18619.899316 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.624423 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 11286741 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1819760000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 11384439 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 18620.927639 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.720286 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 11286707 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1819860500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.008585 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 97732 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 9063 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1379479000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 1379487500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.007789 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 88669 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 18115.384615 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 127.292157 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 127.291774 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 39 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 706500 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 11384473 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 18619.899316 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15557.624423 # average overall mshr miss latency
-system.cpu.icache.demand_hits 11286741 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1819760000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 11384439 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 18620.927639 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15557.720286 # average overall mshr miss latency
+system.cpu.icache.demand_hits 11286707 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1819860500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.008585 # miss rate for demand accesses
system.cpu.icache.demand_misses 97732 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 9063 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1379479000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 1379487500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.007789 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 88669 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.918761 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1881.622790 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 11384473 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18619.899316 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15557.624423 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.918759 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1881.619179 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 11384439 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 18620.927639 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15557.720286 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 11286741 # number of overall hits
-system.cpu.icache.overall_miss_latency 1819760000 # number of overall miss cycles
+system.cpu.icache.overall_hits 11286707 # number of overall hits
+system.cpu.icache.overall_miss_latency 1819860500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.008585 # miss rate for overall accesses
system.cpu.icache.overall_misses 97732 # number of overall misses
system.cpu.icache.overall_mshr_hits 9063 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1379479000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 1379487500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.007789 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 88669 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 86622 # number of replacements
system.cpu.icache.sampled_refs 88668 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1881.622790 # Cycle average of tags in use
-system.cpu.icache.total_refs 11286741 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1881.619179 # Cycle average of tags in use
+system.cpu.icache.total_refs 11286707 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 25587714 # Number of cycles cpu's stages were not processed
-system.cpu.ipc 1.011064 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 1.011064 # IPC: Total IPC of All Threads
+system.cpu.idleCycles 25587834 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 1.011044 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 1.011044 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 11389750 # ITB accesses
+system.cpu.itb.fetch_accesses 11389716 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 11384494 # ITB hits
+system.cpu.itb.fetch_hits 11384460 # ITB hits
system.cpu.itb.fetch_misses 5256 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143582 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52040.936228 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.851808 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52040.829752 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.848005 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12097 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 6842602500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 6842588500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.915748 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 131485 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259512000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259511500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915748 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 131485 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 149430 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52294.227145 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40025.874305 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52294.157340 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40025.851037 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 106453 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2247449000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 2247446000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.287606 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 42977 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1720192000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1720191000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287606 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 42977 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 161214 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 293012 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52103.331958 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40007.015854 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52103.234515 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40007.007257 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 118550 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9090051500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 9090034500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.595409 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 174462 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 6979704000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 6979702500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.595409 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 174462 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.093045 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::0 0.093044 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.476016 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 3048.903015 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15598.107451 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 3048.873160 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15598.097053 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 293012 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52103.331958 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40007.015854 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52103.234515 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40007.007257 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 118550 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9090051500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 9090034500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.595409 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 174462 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 6979704000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 6979702500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.595409 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 174462 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 148090 # number of replacements
system.cpu.l2cache.sampled_refs 173435 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18647.010465 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 18646.970214 # Cycle average of tags in use
system.cpu.l2cache.total_refs 134496 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120516 # number of writebacks
-system.cpu.numCycles 87373938 # number of cpu cycles simulated
+system.cpu.numCycles 87375706 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.runCycles 61786224 # Number of cycles cpu stages are processed.
+system.cpu.runCycles 61787872 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles 42492197 # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles 44881741 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization 51.367424 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles 48180975 # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles 39192963 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization 44.856583 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 46081271 # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles 41292667 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 47.259707 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles 63475501 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles 42493951 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.runCycles 44881755 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-0.utilization 51.366400 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 48181868 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles 39193838 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization 44.856677 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 46079607 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.runCycles 41296099 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-2.utilization 47.262678 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 63477269 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 23898437 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization 27.351906 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles 39335442 # Number of cycles 0 instructions are processed.
-system.cpu.stage-4.runCycles 48038496 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization 54.980349 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles 69006043 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.timesIdled 289198 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.stage-3.utilization 27.351352 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 39338499 # Number of cycles 0 instructions are processed.
+system.cpu.stage-4.runCycles 48037207 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-4.utilization 54.977761 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 69007682 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.timesIdled 289197 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Feb 7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Feb 18 2011 15:40:30
+M5 revision Unknown
+M5 started Feb 18 2011 19:04:15
+M5 executing on m55-001.pool
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 40531473000 because halt instruction encountered
+122 123 124 Exiting @ tick 40531279000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 105929 # Simulator instruction rate (inst/s)
-host_mem_usage 1434716 # Number of bytes of host memory used
-host_seconds 867.59 # Real time elapsed on the host
-host_tick_rate 46717114 # Simulator tick rate (ticks/s)
+host_inst_rate 137731 # Simulator instruction rate (inst/s)
+host_mem_usage 254052 # Number of bytes of host memory used
+host_seconds 667.27 # Real time elapsed on the host
+host_tick_rate 60742348 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91903057 # Number of instructions simulated
+sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.040531 # Number of seconds simulated
-sim_ticks 40531473000 # Number of ticks simulated
+sim_ticks 40531279000 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 27308571 # Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct 59.146475 # BTB Hit Percentage
+system.cpu.Branch-Predictor.BTBHitPct 59.146483 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 4489525 # Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups 7590520 # Number of BTB lookups
+system.cpu.Branch-Predictor.BTBLookups 7590519 # Number of BTB lookups
system.cpu.Branch-Predictor.RASInCorrect 138 # Number of incorrect RAS predictions.
system.cpu.Branch-Predictor.condIncorrect 2806970 # Number of conditional branches incorrect
system.cpu.Branch-Predictor.condPredicted 7883251 # Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups 11539981 # Number of BP lookups
+system.cpu.Branch-Predictor.lookups 11539980 # Number of BP lookups
system.cpu.Branch-Predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken 6626716 # Number of Branches Predicted As Taken (True).
+system.cpu.Branch-Predictor.predictedTaken 6626715 # Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions 66407277 # Number of Instructions Executed.
+system.cpu.Execution-Unit.executions 57928840 # Number of Instructions Executed.
system.cpu.Execution-Unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts
system.cpu.Execution-Unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted 7433715 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 152685933 # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 84258572 # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 152685930 # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 84258569 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards 38185925 # Number of Registers Read Through Forwarding Logic
-system.cpu.activity 91.670105 # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards 38185928 # Number of Registers Read Through Forwarding Logic
+system.cpu.activity 91.670040 # Percentage of cycles cpu is active
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
system.cpu.comInts 43665352 # Number of Integer instructions committed
system.cpu.comLoads 19996198 # Number of Load instructions committed
-system.cpu.comNonSpec 390 # Number of Non-Speculative instructions committed
+system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
system.cpu.comNops 7723346 # Number of Nop instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
-system.cpu.committedInsts 91903057 # Number of Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 91903057 # Number of Instructions Simulated (Total)
+system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.cpi 0.882048 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 0.882048 # CPI: Total CPI of All Threads
+system.cpu.cpi 0.882044 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 0.882044 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 51751.953125 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48809.473684 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 51752.929688 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48810.526316 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19995686 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 26497000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 26497500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 512 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 23184500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 23185000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55922.090261 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52793.478261 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55921.258907 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52792.620137 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6496893 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 235432000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 235428500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000648 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 4210 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 2462 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 92283000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 92281500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1373500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55469.927997 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51942.195232 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 55469.292673 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51941.745389 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26492579 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 261929000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 261926000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000178 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4722 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2499 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 115467500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 115466500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.351931 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 1441.507978 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 1441.508051 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55469.927997 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51942.195232 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55469.292673 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51941.745389 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 26492579 # number of overall hits
-system.cpu.dcache.overall_miss_latency 261929000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 261926000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000178 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4722 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2499 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 115467500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 115466500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1441.507978 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1441.508051 # Cycle average of tags in use
system.cpu.dcache.total_refs 26492579 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107 # number of writebacks
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
-system.cpu.icache.ReadReq_accesses 9759566 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 26777.900606 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.891881 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 9749163 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 278570500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 9759564 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 26779.967317 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.993880 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 9749161 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 278592000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001066 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10403 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 599 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 226863500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 226864500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 9804 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 994.406671 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 994.406467 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 202500 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 9759566 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 26777.900606 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23139.891881 # average overall mshr miss latency
-system.cpu.icache.demand_hits 9749163 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 278570500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 9759564 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 26779.967317 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23139.993880 # average overall mshr miss latency
+system.cpu.icache.demand_hits 9749161 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 278592000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001066 # miss rate for demand accesses
system.cpu.icache.demand_misses 10403 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 599 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 226863500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 226864500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.001005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 9804 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.729171 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1493.341258 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 9759566 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 26777.900606 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23139.891881 # average overall mshr miss latency
+system.cpu.icache.occ_blocks::0 1493.341252 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 9759564 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 26779.967317 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23139.993880 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 9749163 # number of overall hits
-system.cpu.icache.overall_miss_latency 278570500 # number of overall miss cycles
+system.cpu.icache.overall_hits 9749161 # number of overall hits
+system.cpu.icache.overall_miss_latency 278592000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001066 # miss rate for overall accesses
system.cpu.icache.overall_misses 10403 # number of overall misses
system.cpu.icache.overall_mshr_hits 599 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 226863500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 226864500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 9804 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 7919 # number of replacements
system.cpu.icache.sampled_refs 9804 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1493.341258 # Cycle average of tags in use
-system.cpu.icache.total_refs 9749163 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1493.341252 # Cycle average of tags in use
+system.cpu.icache.total_refs 9749161 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 6752458 # Number of cycles cpu's stages were not processed
-system.cpu.ipc 1.133725 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 1.133725 # IPC: Total IPC of All Threads
+system.cpu.idleCycles 6752479 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 1.133730 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 1.133730 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 9759621 # ITB accesses
+system.cpu.itb.fetch_accesses 9759619 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 9759574 # ITB hits
+system.cpu.itb.fetch_hits 9759572 # ITB hits
system.cpu.itb.fetch_misses 47 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.562137 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52355.691057 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40114.401858 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 90158000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 90156500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69077000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 10279 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52322.450249 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40125.777363 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52322.761194 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40125.621891 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7063 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 168269000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 168270000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.312871 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 129044500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 129044000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.312871 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 12027 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52334.345889 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40121.810450 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52334.244633 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40121.709194 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7089 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 258427000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 258426500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.410576 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 198121500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 198121000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.410576 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.066327 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000542 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2173.408404 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 17.762794 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 2173.408531 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 17.762817 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 12027 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52334.345889 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.810450 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52334.244633 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.709194 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 7089 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 258427000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 258426500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.410576 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4938 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 198121500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 198121000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.410576 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2191.171198 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2191.171348 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7072 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 81062947 # number of cpu cycles simulated
+system.cpu.numCycles 81062559 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.runCycles 74310489 # Number of cycles cpu stages are processed.
+system.cpu.runCycles 74310080 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles 27951481 # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles 53111466 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization 65.518795 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles 33263015 # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles 47799932 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization 58.966438 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 32674388 # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles 48388559 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 59.692573 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles 63236669 # Number of cycles 0 instructions are processed.
-system.cpu.stage-3.runCycles 17826278 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization 21.990661 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles 26883449 # Number of cycles 0 instructions are processed.
-system.cpu.stage-4.runCycles 54179498 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization 66.836329 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles 80608290 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.timesIdled 10787 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.stage-0.idleCycles 27951091 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.runCycles 53111468 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-0.utilization 65.519111 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 33262621 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles 47799938 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization 58.966727 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 32674404 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.runCycles 48388155 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-2.utilization 59.692361 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 63236282 # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.runCycles 17826277 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-3.utilization 21.990765 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 26883065 # Number of cycles 0 instructions are processed.
+system.cpu.stage-4.runCycles 54179494 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-4.utilization 66.836644 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 80607865 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.timesIdled 10786 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Feb 7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Feb 18 2011 15:40:30
+M5 revision Unknown
+M5 started Feb 18 2011 18:52:59
+M5 executing on m55-001.pool
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 22288500 because target called exit()
+Exiting @ tick 22294500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 76381 # Simulator instruction rate (inst/s)
-host_mem_usage 190468 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 264969940 # Simulator tick rate (ticks/s)
+host_inst_rate 97475 # Simulator instruction rate (inst/s)
+host_mem_usage 190320 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 337940129 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 22288500 # Number of ticks simulated
-system.cpu.AGEN-Unit.agens 2187 # Number of Address Generations
+sim_ticks 22294500 # Number of ticks simulated
+system.cpu.AGEN-Unit.agens 2186 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 23.015873 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 87 # Number of BTB hits
system.cpu.Branch-Predictor.BTBLookups 378 # Number of BTB lookups
system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect 543 # Number of conditional branches incorrect
+system.cpu.Branch-Predictor.condIncorrect 542 # Number of conditional branches incorrect
system.cpu.Branch-Predictor.condPredicted 995 # Number of conditional branches predicted
system.cpu.Branch-Predictor.lookups 1423 # Number of BP lookups
system.cpu.Branch-Predictor.predictedNotTaken 1183 # Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken 240 # Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions 4617 # Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct 51.615970 # Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted 543 # Number of Branches Incorrectly Predicted
+system.cpu.Execution-Unit.executions 4596 # Number of Instructions Executed.
+system.cpu.Execution-Unit.mispredictPct 51.569933 # Percentage of Incorrect Branches Predicts
+system.cpu.Execution-Unit.mispredicted 542 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted 509 # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect 538 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 537 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.Execution-Unit.predictedTakenIncorrect 5 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 10532 # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 5949 # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 10530 # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 5947 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File
system.cpu.RegFile-Manager.regForwards 2845 # Number of Registers Read Through Forwarding Logic
-system.cpu.activity 16.048275 # Percentage of cycles cpu is active
+system.cpu.activity 16.075353 # Percentage of cycles cpu is active
system.cpu.comBranches 1051 # Number of Branches instructions committed
system.cpu.comFloats 2 # Number of Floating Point instructions committed
system.cpu.comInts 3265 # Number of Integer instructions committed
system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.cpi 6.960962 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 6.960962 # CPI: Total CPI of All Threads
+system.cpu.cpi 6.962836 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 6.962836 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56781.250000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53784.210526 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 56786.458333 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53789.473684 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1089 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 5451000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 5451500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.081013 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 5109500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 5110000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.blocked_cycles::no_targets 162000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56661.157025 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53687.500000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 56663.223140 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53690.476190 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1808 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 13712000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 13712500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.118049 # miss rate for demand accesses
system.cpu.dcache.demand_misses 242 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 74 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9019500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 9020000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.024901 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 101.993452 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.024898 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 101.981030 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56661.157025 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53687.500000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56663.223140 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53690.476190 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1808 # number of overall hits
-system.cpu.dcache.overall_miss_latency 13712000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 13712500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.118049 # miss rate for overall accesses
system.cpu.dcache.overall_misses 242 # number of overall misses
system.cpu.dcache.overall_mshr_hits 74 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 9019500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 9020000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 101.993452 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 101.981030 # Cycle average of tags in use
system.cpu.dcache.total_refs 1808 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.icache.ReadReq_accesses 955 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55326.979472 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 55322.580645 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53094.684385 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 614 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 18866500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 18865000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.357068 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 955 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55326.979472 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency 55322.580645 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency
system.cpu.icache.demand_hits 614 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 18866500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 18865000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.357068 # miss rate for demand accesses
system.cpu.icache.demand_misses 341 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.066887 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 136.984147 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.066877 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 136.964505 # Average occupied blocks per context
system.cpu.icache.overall_accesses 955 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55326.979472 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55322.580645 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 614 # number of overall hits
-system.cpu.icache.overall_miss_latency 18866500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 18865000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.357068 # miss rate for overall accesses
system.cpu.icache.overall_misses 341 # number of overall misses
system.cpu.icache.overall_mshr_hits 40 # number of overall MSHR hits
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 300 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 136.984147 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 136.964505 # Cycle average of tags in use
system.cpu.icache.total_refs 614 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 37424 # Number of cycles cpu's stages were not processed
-system.cpu.ipc 0.143658 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.143658 # IPC: Total IPC of All Threads
+system.cpu.idleCycles 37422 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.143620 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.143620 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.005889 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 192.975400 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.005888 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 192.950109 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 469 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52243.589744 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40087.606838 # average overall mshr miss latency
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 394 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 192.975400 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 192.950109 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 44578 # number of cpu cycles simulated
+system.cpu.numCycles 44590 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.runCycles 7154 # Number of cycles cpu stages are processed.
+system.cpu.runCycles 7168 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles 39836 # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles 4742 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization 10.637534 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles 40747 # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles 3831 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization 8.593925 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 40491 # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles 4087 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 9.168200 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles 43168 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles 39847 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.runCycles 4743 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-0.utilization 10.636914 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 40758 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles 3832 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization 8.593855 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 40488 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.runCycles 4102 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-2.utilization 9.199372 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 43180 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 1410 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization 3.162995 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles 40170 # Number of cycles 0 instructions are processed.
-system.cpu.stage-4.runCycles 4408 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization 9.888286 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles 11304 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-3.utilization 3.162144 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 40181 # Number of cycles 0 instructions are processed.
+system.cpu.stage-4.runCycles 4409 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-4.utilization 9.887867 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 11319 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
All Rights Reserved
-M5 compiled Feb 7 2011 01:55:51
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:56:02
-M5 executing on burrito
+M5 compiled Feb 18 2011 18:35:15
+M5 revision Unknown
+M5 started Feb 18 2011 18:52:36
+M5 executing on m55-001.pool
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 21534000 because target called exit()
+Exiting @ tick 21538000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1339 # Simulator instruction rate (inst/s)
-host_mem_usage 191872 # Number of bytes of host memory used
-host_seconds 4.35 # Real time elapsed on the host
-host_tick_rate 4946645 # Simulator tick rate (ticks/s)
+host_inst_rate 94112 # Simulator instruction rate (inst/s)
+host_mem_usage 191540 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 346291258 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 21534000 # Number of ticks simulated
+sim_ticks 21538000 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 2404 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 14.054054 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 26 # Number of BTB hits
system.cpu.Branch-Predictor.BTBLookups 185 # Number of BTB lookups
system.cpu.Branch-Predictor.RASInCorrect 30 # Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect 845 # Number of conditional branches incorrect
+system.cpu.Branch-Predictor.condIncorrect 844 # Number of conditional branches incorrect
system.cpu.Branch-Predictor.condPredicted 778 # Number of conditional branches predicted
system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups
system.cpu.Branch-Predictor.predictedNotTaken 949 # Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken 117 # Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS 86 # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions 3963 # Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct 92.148310 # Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted 845 # Number of Branches Incorrectly Predicted
+system.cpu.Execution-Unit.executions 3261 # Number of Instructions Executed.
+system.cpu.Execution-Unit.mispredictPct 92.139738 # Percentage of Incorrect Branches Predicts
+system.cpu.Execution-Unit.mispredicted 844 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted 72 # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect 813 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 812 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.Execution-Unit.predictedTakenIncorrect 32 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 10006 # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 6596 # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 10004 # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 6594 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File
system.cpu.RegFile-Manager.regForwards 1378 # Number of Registers Read Through Forwarding Logic
-system.cpu.activity 13.935777 # Percentage of cycles cpu is active
+system.cpu.activity 13.954082 # Percentage of cycles cpu is active
system.cpu.comBranches 916 # Number of Branches instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
system.cpu.comInts 2155 # Number of Integer instructions committed
system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.cpi 7.391282 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 7.391282 # CPI: Total CPI of All Threads
+system.cpu.cpi 7.392655 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 7.392655 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56681.818182 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53683.908046 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 56676.136364 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53678.160920 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4988000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 4987500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.075601 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 4670500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 4670000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.blocked_cycles::no_targets 265500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56298.342541 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 56295.580110 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10190000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 10189500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.086644 # miss rate for demand accesses
system.cpu.dcache.demand_misses 181 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7406000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 7405500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.021745 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 89.066455 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 89.067186 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56298.342541 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56295.580110 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1908 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10190000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 10189500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.086644 # miss rate for overall accesses
system.cpu.dcache.overall_misses 181 # number of overall misses
system.cpu.dcache.overall_mshr_hits 43 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7406000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 7405500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 89.066455 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 89.067186 # Cycle average of tags in use
system.cpu.dcache.total_refs 1908 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 853 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55526.246719 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53153.605016 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 55527.559055 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53156.739812 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 472 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 21155500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 21156000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.446659 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 16956000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 16957000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.373974 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles::no_targets 62000 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 853 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55526.246719 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 55527.559055 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency
system.cpu.icache.demand_hits 472 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 21155500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 21156000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.446659 # miss rate for demand accesses
system.cpu.icache.demand_misses 381 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 62 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 16956000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 16957000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.373974 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.070944 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 145.293265 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.070945 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 145.295903 # Average occupied blocks per context
system.cpu.icache.overall_accesses 853 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55526.246719 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 55527.559055 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 472 # number of overall hits
-system.cpu.icache.overall_miss_latency 21155500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 21156000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.446659 # miss rate for overall accesses
system.cpu.icache.overall_misses 381 # number of overall misses
system.cpu.icache.overall_mshr_hits 62 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 16956000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 16957000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.373974 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 145.293265 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 145.295903 # Cycle average of tags in use
system.cpu.icache.total_refs 472 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 37067 # Number of cycles cpu's stages were not processed
-system.cpu.ipc 0.135295 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.135295 # IPC: Total IPC of All Threads
+system.cpu.idleCycles 37066 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.135269 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.135269 # IPC: Total IPC of All Threads
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52355.198020 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40152.227723 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52357.673267 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40153.465347 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 21151500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 21152500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 16221500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 16222000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52368.131868 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52370.329670 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 23827500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 23828500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 18273500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 18274000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.006169 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 202.148379 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 202.151439 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52368.131868 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52370.329670 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 23827500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 23828500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 455 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 18273500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 18274000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 202.148379 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 202.151439 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 43069 # number of cpu cycles simulated
+system.cpu.numCycles 43077 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.runCycles 6002 # Number of cycles cpu stages are processed.
+system.cpu.runCycles 6011 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles 39196 # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles 3873 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization 8.992547 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles 40152 # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles 2917 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization 6.772853 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 40243 # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles 2826 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 6.561564 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles 41749 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles 39203 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.runCycles 3874 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-0.utilization 8.993198 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 40159 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles 2918 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization 6.773916 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 40245 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.runCycles 2832 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-2.utilization 6.574274 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 41757 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 1320 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization 3.064849 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles 39866 # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization 3.064280 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 39874 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 3203 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization 7.436904 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles 10184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization 7.435522 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 10193 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.timesIdled 427 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
projects / gem5.git / commitdiff