fix some typos

diff --git a/src/openpower/decoder/isa/test_caller_fptrans.py b/src/openpower/decoder/isa/test_caller_fptrans.py
index 69342a6989fcc41e0511791929e1cbb5f8372f02..384571c3683b1be95a7f184fbc52722d2653b5e1 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fptrans.py
+++ b/src/openpower/decoder/isa/test_caller_fptrans.py
@@ -8,7 +8,7 @@ from openpower.test.fptrans.fptrans_cases import FPTransCases
 # writing the test_caller invocation this way makes it work with pytest
 
 
-class TestSVP64ALU(TestRunnerBase):
+class TestFPTrans(TestRunnerBase):
     def __init__(self, test):
         assert test == 'test'
         super().__init__(FPTransCases().test_data, fp=True)

diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py
index b9165b491e2ff41179853d4f9593746aeb134f16..7bc796892f3a2f9dc11eba5db6550750d1497165 100644 (file)
--- a/src/openpower/test/state.py
+++ b/src/openpower/test/state.py
@@ -188,7 +188,7 @@ class State:
 
 class SimState(State):
     """SimState: Obtains registers and memory from an ISACaller object.
-    Note that yields are "faked" to maintain consistency and compatability
+    Note that yields are "faked" to maintain consistency and compatibility
     within the API.
     """
     def __init__(self, sim):