ld/st modes

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 8ae49f789a8572c5ceadcfa572731109a1b3d3eb..721e152aac79931b6a53188cb1753eba1d04e939 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -344,22 +344,20 @@ mask `sv.bc/pm=r3`.
 # LD/ST RM Modes
 
 Traditional Vector ISAs have vastly more (and more complex) addressing
-modes: unit strided, element strided, Indexed, Structure Packing. All
-of these had to be jammed in on top of existing Scalar instructions
-**without modifying or adding new Scalar instructions**.
-A small conceptual
-"cheat" was therefore needed.  The Immediate (D) is in some Modes
-multiplied by the element index, which gives us element-strided.
-For unit-strided the width of the operation (`ld`, 8 byte) is
-multiplied by the element index and *substituted* for "D" when
-the immediate, D, is zero.  Modifications to support this
-"cheat" on top of pre-existing Scalar HDL (and Simulators)
-have both turned out to be minimal.[^mul]
-Also added was the option to perform signed or unsigned Effective
-Address calculation, which comes into play only on LD/ST Indexed,
-when elwidth overrides are used.  Another quirk: `RA` is never
-allowed to have its width altered: it remains 64-bit, as it is
-the Base Address.
+modes than Scalar ISAs: unit strided, element strided, Indexed, Structure
+Packing. All of these had to be jammed in on top of existing Scalar
+instructions **without modifying or adding new Scalar instructions**.
+A small conceptual "cheat" was therefore needed.  The Immediate (D)
+is in some Modes multiplied by the element index, which gives us
+element-strided.  For unit-strided the width of the operation (`ld`,
+8 byte) is multiplied by the element index and *substituted* for "D"
+when the immediate, D, is zero.  Modifications to support this "cheat"
+on top of pre-existing Scalar HDL (and Simulators) have both turned
+out to be minimal.[^mul] Also added was the option to perform signed
+or unsigned Effective Address calculation, which comes into play only
+on LD/ST Indexed, when elwidth overrides are used.  Another quirk:
+`RA` is never allowed to have its width altered: it remains 64-bit,
+as it is the Base Address.
 
 One confusing thing is the unfortunate naming of LD/ST Indexed and
 REMAP Indexed: some care is taken in the spec to discern the two.