read_aiger to also rename 0 index lut when wideports

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 5c862b8f061ccc7ec5a9027bdc6c4186f33b0fc8..426e88e53c8ce407c1925861e1647da6eca4a88d 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -162,9 +162,15 @@ void AigerReader::parse_aiger()
         int width = wp.second + 1;
 
         RTLIL::Wire *wire = module->wire(name);
-        if (wire)
+        if (wire) {
+            RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
+
             module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
 
+            if (driver)
+                module->rename(driver, stringf("%slut", wire->name.c_str()));
+        }
+
         // Do not make ports with a mix of input/output into
         // wide ports
         bool port_input = false, port_output = false;
@@ -408,9 +414,15 @@ void AigerReader::parse_xaiger()
         int width = wp.second + 1;
 
         RTLIL::Wire *wire = module->wire(name);
-        if (wire)
+        if (wire) {
+            RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
+
             module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
 
+            if (driver)
+                module->rename(driver, stringf("%slut", wire->name.c_str()));
+        }
+
         // Do not make ports with a mix of input/output into
         // wide ports
         bool port_input = false, port_output = false;