Use ABC to convert from AIGER to Verilog

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 0a511f29cc84b57e7e0bf3e891abe61ddcbc3402..23964a751fd66f61ceced03e35e42221c6f6f74a 100755 (executable)
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -146,9 +146,10 @@ do
                rm -f ${bn}_ref.fir
                if [[ "$ext" == "v" ]]; then
                        egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
+               elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
+                       "$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v"
                else
-                       "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
-                       frontend="verilog -noblackbox"
+                       cp ../${fn} ${bn}_ref.${ext}
                fi
 
                if [ ! -f ../${bn}_tb.v ]; then