aarch64: Add a _10 suffix to FLD_imm3

SME2 adds various new 3-bit immediate fields, so this patch adds
an lsb position suffix to the name of the field that we already have.

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 7351c2417b235f943bffe3efb10f2bdf16353ee7..5a9ca5a980d21ad64030fccf8f7a5267ef4735d9 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -943,7 +943,7 @@ aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
       ? AARCH64_MOD_UXTW : AARCH64_MOD_UXTX;
   insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
   /* imm3 */
-  insert_field (FLD_imm3, code, info->shifter.amount, 0);
+  insert_field (FLD_imm3_10, code, info->shifter.amount, 0);
 
   return true;
 }
@@ -1016,7 +1016,7 @@ aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
   int factor = 1 + get_operand_specific_data (self);
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   insert_fields (code, info->addr.offset.imm / factor, 0,
-                2, FLD_imm3, FLD_SVE_imm6);
+                2, FLD_imm3_10, FLD_SVE_imm6);
   return true;
 }
 

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index e722514053edbf209be45746e91c05c85f3c7ad5..49bfd46906e05b8a7d1ee1a05de000ec4b05d347 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1395,7 +1395,7 @@ aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
   info->shifter.kind =
     aarch64_get_operand_modifier_from_value (value, true /* extend_p */);
   /* imm3 */
-  info->shifter.amount = extract_field (FLD_imm3, code,  0);
+  info->shifter.amount = extract_field (FLD_imm3_10, code,  0);
 
   /* This makes the constraint checking happy.  */
   info->shifter.operator_present = 1;
@@ -1512,7 +1512,7 @@ aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self,
 {
   int offset;
 
-  offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3);
+  offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3_10);
   offset = (((offset + 256) & 511) - 256);
   return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
 }

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 1d59a8bd332d98e1841b89c23e5bf6c481ee3c5f..fe67dbc9b62c54c0a7df190c2374be3a062869d1 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -214,7 +214,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a 3-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
-  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3_10}, "an 8-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 1a1e1bd22f3f6349dda404543e5df22349b010c7..969362a56cd1fc537857c30f9de9a46b7075d878 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -296,7 +296,7 @@ const aarch64_field fields[] =
     {  0,  4 },        /* cond2: condition in truly conditional-executed inst.  */
     {  5,  5 },        /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate.  */
     { 21,  2 },        /* hw: in move wide constant instructions.  */
-    { 10,  3 },        /* imm3: in add/sub extended reg instructions.  */
+    { 10,  3 },        /* imm3_10: in add/sub extended reg instructions.  */
     {  0,  4 },        /* imm4_0: in rmif instructions.  */
     {  5,  4 }, /* imm4_5: in SME instructions.  */
     { 10,  4 },        /* imm4_10: in adddg/subg instructions.  */

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 3ded6ab7958450c953d32367bf101cc8d39f7453..e142ae6ee76432db89d3030f3822ba1b40a4553b 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -124,7 +124,7 @@ enum aarch64_field_kind
   FLD_cond2,
   FLD_defgh,
   FLD_hw,
-  FLD_imm3,
+  FLD_imm3_10,
   FLD_imm4_0,
   FLD_imm4_5,
   FLD_imm4_10,

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 82f4af2839f1eb39f40d41da23c8b00e30e50517..aa05ca0f4a9617def6e8f79403b23ae376e4cb76 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5863,7 +5863,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
       "a 7-bit unsigned immediate")                                    \
     Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD_SVE_imm8),                 \
       "an 8-bit unsigned immediate")                                   \
-    Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3),         \
+    Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3_10),              \
       "an 8-bit unsigned immediate")                                   \
     Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \
     Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register")  \