add VBLOCK SVP format idea

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index 35d0deed181c8fd3d87852003b938d2f71922b41..9fe4a5722ab90b496d802ca70648e0ae8106a331 100644 (file)
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -1,7 +1,13 @@
 # Alternative (SVPrefix) format
 
 This VBLOCK mode effectively extends [[sv_prefix_proposal]] to cover multiple
-registers.  Its advantage over the main format is that the main format requires
+registers.  The basic principle: the "prefix" specifies which of source and
+destination registers are to be considered "vectors" (or scalars), however
+where in SVPrefix that applies to only one instruction, the "vector" tag
+designations *continue to cascade* into subsequent instructions within the
+VBLOCK.
+
+Its advantage over the main format is that the main format requires
 explicit naming of the registers to be tagged (taking up 5 bits each time).
 
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