sim: Remove redundant export_method_cxx_predecls

The headers declared in export_method_cxx_predecls are redundant since a
SimObject's main header is automatically included.

Change-Id: Ied9e84630b36960e54efe91d16f8c66fba7e0da0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Joe Gross <joseph.gross@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index ac04a56e4179daea20cc4a98a6753c586c4204b3..9100db09ad7f88d709b853b8a53c4ad5139ef2d4 100644 (file)
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -98,10 +98,6 @@ class LinuxArmSystem(GenericArmSystem):
     type = 'LinuxArmSystem'
     cxx_header = "arch/arm/linux/system.hh"
 
-    @classmethod
-    def export_method_cxx_predecls(cls, code):
-        code('#include "arch/arm/linux/system.hh"')
-
     @classmethod
     def export_methods(cls, code):
         code('''void dumpDmesg();''')

diff --git a/src/cpu/kvm/BaseKvmCPU.py b/src/cpu/kvm/BaseKvmCPU.py
index 34ab752de170de17f24764e01eac50537b4bd023..4c64f24ed0d901db2e96f500e89192517599322d 100644 (file)
--- a/src/cpu/kvm/BaseKvmCPU.py
+++ b/src/cpu/kvm/BaseKvmCPU.py
@@ -46,10 +46,6 @@ class BaseKvmCPU(BaseCPU):
     cxx_header = "cpu/kvm/base.hh"
     abstract = True
 
-    @classmethod
-    def export_method_cxx_predecls(cls, code):
-        code('#include "cpu/kvm/base.hh"')
-
     @classmethod
     def export_methods(cls, code):
         code('''

diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index bb834fc0b99f6c22c709af493580f8c70bdffdd5..11f356204f9e957b3a4e8aa8646c862f64277be7 100644 (file)
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -498,8 +498,7 @@ class MetaSimObject(type):
         # suppresses inheritance by substituting in the base (null)
         # versions of these methods unless a different version is
         # explicitly supplied.
-        for method_name in ('export_methods', 'export_method_cxx_predecls',
-                            'export_method_swig_predecls'):
+        for method_name in ('export_methods', 'export_method_swig_predecls'):
             if method_name not in cls.__dict__:
                 base_method = getattr(MetaSimObject, method_name)
                 m = MethodType(base_method, cls, MetaSimObject)
@@ -664,14 +663,6 @@ class MetaSimObject(type):
     def export_methods(cls, code):
         pass
 
-    # Generate the code needed as a prerequisite for the C++ methods
-    # exported via export_methods() to be compiled in the _wrap.cc
-    # file.  Typically generates one or more #include statements.  If
-    # any methods are exported, typically at least the C++ header
-    # declaring the relevant SimObject class must be included.
-    def export_method_cxx_predecls(cls, code):
-        pass
-
     # Generate the code needed as a prerequisite for the C++ methods
     # exported via export_methods() to be processed by SWIG.
     # Typically generates one or more %include or %import statements.
@@ -703,7 +694,6 @@ class MetaSimObject(type):
         for param in params:
             param.cxx_predecls(code)
         code('#include "${{cls.cxx_header}}"')
-        cls.export_method_cxx_predecls(code)
         code('''\
 /**
   * This is a workaround for bug in swig. Prior to gcc 4.6.1 the STL

diff --git a/src/sim/System.py b/src/sim/System.py
index 8ebf7a024fc4026364cd2c410e4e4cc6678548d9..f97096fcc56897ec5719f29d1959b9824878668a 100644 (file)
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -43,10 +43,6 @@ class System(MemObject):
     cxx_header = "sim/system.hh"
     system_port = MasterPort("System port")
 
-    @classmethod
-    def export_method_cxx_predecls(cls, code):
-        code('#include "sim/system.hh"')
-
     @classmethod
     def export_methods(cls, code):
         code('''