ac: add radeon_info::is_amdgpu instead of checking drm_major == 3
authorMarek Olšák <marek.olsak@amd.com>
Wed, 12 Jun 2019 02:49:18 +0000 (22:49 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Fri, 14 Jun 2019 17:31:18 +0000 (13:31 -0400)
and clean up

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
19 files changed:
src/amd/common/ac_gpu_info.c
src/amd/common/ac_gpu_info.h
src/amd/vulkan/radv_debug.c
src/gallium/drivers/r600/r600_buffer_common.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/r600/r600_pipe_common.c
src/gallium/drivers/r600/r600_query.c
src/gallium/drivers/r600/r600_texture.c
src/gallium/drivers/r600/radeon_uvd.c
src/gallium/drivers/r600/radeon_vce.c
src/gallium/drivers/radeon/radeon_uvd.c
src/gallium/drivers/radeon/radeon_vce.c
src/gallium/drivers/radeonsi/si_buffer.c
src/gallium/drivers/radeonsi/si_debug.c
src/gallium/drivers/radeonsi/si_get.c
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/radeonsi/si_query.c
src/gallium/drivers/radeonsi/si_state.c
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

index 13fba8df04792584049efa6c01e65101d02139a1..4de6882f15e72d3de542b649f0af76c4f93f5962 100644 (file)
@@ -117,6 +117,9 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->pci_func = devinfo->businfo.pci->func;
        drmFreeDevice(&devinfo);
 
+       assert(info->drm_major == 3);
+       info->is_amdgpu = true;
+
        /* Query hardware and driver information. */
        r = amdgpu_query_gpu_info(dev, amdinfo);
        if (r) {
@@ -161,7 +164,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                return false;
        }
 
-       if (info->drm_major == 3 && info->drm_minor >= 17) {
+       if (info->drm_minor >= 17) {
                r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
                if (r) {
                        fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
@@ -169,7 +172,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                }
        }
 
-       if (info->drm_major == 3 && info->drm_minor >= 17) {
+       if (info->drm_minor >= 17) {
                r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
                if (r) {
                        fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
@@ -177,7 +180,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                }
        }
 
-       if (info->drm_major == 3 && info->drm_minor >= 17) {
+       if (info->drm_minor >= 17) {
                r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
                if (r) {
                        fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
@@ -185,7 +188,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                }
        }
 
-       if (info->drm_major == 3 && info->drm_minor >= 27) {
+       if (info->drm_minor >= 27) {
                r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
                if (r) {
                        fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
@@ -744,7 +747,7 @@ ac_get_raster_config(struct radeon_info *info,
        /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
         * This decreases performance by up to 50% when the RB is the bottleneck.
         */
-       if (info->family == CHIP_KAVERI && info->drm_major == 2)
+       if (info->family == CHIP_KAVERI && !info->is_amdgpu)
                raster_config = 0x00000000;
 
        /* Fiji: Old kernels have incorrect tiling config. This decreases
index 2adc0e12f1b1c154a42c6eb3db594cdda9c9efbe..2c67cec3ed5692f4610c11ecd979f3f8f833c5a2 100644 (file)
@@ -99,6 +99,7 @@ struct radeon_info {
        uint32_t                    drm_major; /* version */
        uint32_t                    drm_minor;
        uint32_t                    drm_patchlevel;
+       bool                        is_amdgpu;
        bool                        has_userptr;
        bool                        has_syncobj;
        bool                        has_syncobj_wait_for_submit;
index 2177cda0f4a5ed016e2aea5b2ee65cca60a64e63..80d1559912320f57794a4b94bc7aa6d473136afa 100644 (file)
@@ -111,14 +111,11 @@ radv_dump_debug_registers(struct radv_device *device, FILE *f)
 {
        struct radeon_info *info = &device->physical_device->rad_info;
 
-       if (info->drm_major == 2 && info->drm_minor < 42)
-               return; /* no radeon support */
-
        fprintf(f, "Memory-mapped registers:\n");
        radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 
        /* No other registers can be read on DRM < 3.1.0. */
-       if (info->drm_major < 3 || info->drm_minor < 1) {
+       if (info->drm_minor < 1) {
                fprintf(f, "\n");
                return;
        }
index 17a8c3a596ff83c6af0a992adc3acbe876b684da..047394a5297c46cc602ea414a08e935cb61d303d 100644 (file)
@@ -126,8 +126,7 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
                /* Older kernels didn't always flush the HDP cache before
                 * CS execution
                 */
-               if (rscreen->info.drm_major == 2 &&
-                   rscreen->info.drm_minor < 40) {
+               if (rscreen->info.drm_minor < 40) {
                        res->domains = RADEON_DOMAIN_GTT;
                        res->flags |= RADEON_FLAG_GTT_WC;
                        break;
@@ -154,8 +153,7 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
                 * ensures all CPU writes finish before the GPU
                 * executes a command stream.
                 */
-               if (rscreen->info.drm_major == 2 &&
-                   rscreen->info.drm_minor < 40)
+               if (rscreen->info.drm_minor < 40)
                        res->domains = RADEON_DOMAIN_GTT;
        }
 
index 1aa673c0a53971527af17733f089227165f06f8a..2a14aa05ca5b85c8e7538b591dec677f66205ad9 100644 (file)
@@ -322,7 +322,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return 64 * 1024 * 1024;
 
        case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
-               return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
+               return rscreen->b.info.drm_minor >= 43;
 
        case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
                return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
index 5177ff4e1c65514af667a21c4b86fa395bd2cb01..566c63cc4d8f2a3b4d217ba16c377c4d0f9ce021 100644 (file)
@@ -345,48 +345,12 @@ void r600_postflush_resume_features(struct r600_common_context *ctx)
                r600_resume_queries(ctx);
 }
 
-static void r600_add_fence_dependency(struct r600_common_context *rctx,
-                                     struct pipe_fence_handle *fence)
-{
-       struct radeon_winsys *ws = rctx->ws;
-
-       if (rctx->dma.cs)
-               ws->cs_add_fence_dependency(rctx->dma.cs, fence, 0);
-       ws->cs_add_fence_dependency(rctx->gfx.cs, fence, 0);
-}
-
 static void r600_fence_server_sync(struct pipe_context *ctx,
                                   struct pipe_fence_handle *fence)
 {
-       struct r600_common_context *rctx = (struct r600_common_context *)ctx;
-       struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
-
-       /* Only amdgpu needs to handle fence dependencies (for fence imports).
-        * radeon synchronizes all rings by default and will not implement
+       /* radeon synchronizes all rings by default and will not implement
         * fence imports.
         */
-       if (rctx->screen->info.drm_major == 2)
-               return;
-
-       /* Only imported fences need to be handled by fence_server_sync,
-        * because the winsys handles synchronizations automatically for BOs
-        * within the process.
-        *
-        * Simply skip unflushed fences here, and the winsys will drop no-op
-        * dependencies (i.e. dependencies within the same ring).
-        */
-       if (rfence->gfx_unflushed.ctx)
-               return;
-
-       /* All unflushed commands will not start execution before
-        * this fence dependency is signalled.
-        *
-        * Should we flush the context to allow more GPU parallelism?
-        */
-       if (rfence->sdma)
-               r600_add_fence_dependency(rctx, rfence->sdma);
-       if (rfence->gfx)
-               r600_add_fence_dependency(rctx, rfence->gfx);
 }
 
 static void r600_flush_from_st(struct pipe_context *ctx,
@@ -1227,12 +1191,8 @@ static void r600_query_memory_info(struct pipe_screen *screen,
        info->device_memory_evicted =
                ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 
-       if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
-               info->nr_device_memory_evictions =
-                       ws->query_value(ws, RADEON_NUM_EVICTIONS);
-       else
-               /* Just return the number of evicted 64KB pages. */
-               info->nr_device_memory_evictions = info->device_memory_evicted / 64;
+       /* Just return the number of evicted 64KB pages. */
+       info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 }
 
 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
index e7ef34ba41266d91d42e462462079a16198cabbd..ed2226293dd2d3e5fa6f7981e6e01f3e6a4e059f 100644 (file)
@@ -2031,7 +2031,7 @@ static const struct pipe_driver_query_info r600_driver_query_list[] = {
 
 static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
 {
-       if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
+       if (rscreen->info.drm_minor >= 42)
                return ARRAY_SIZE(r600_driver_query_list);
        else
                return ARRAY_SIZE(r600_driver_query_list) - 25;
index 497da0c3dfaa3a3cb92ef8a808603f64a8643a2d..12812e0e39614d49547ea2c5324c8709ec9b0c3b 100644 (file)
@@ -762,7 +762,7 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
        rtex->surface.htile_size = 0;
 
        if (rscreen->chip_class <= EVERGREEN &&
-           rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
+           rscreen->info.drm_minor < 26)
                return;
 
        /* HW bug on R6xx. */
index 5568f2138e483d63549a45354f30e10ff6e89d8e..7f853446b142bcfe382d66f463dbd5292e5ea80a 100644 (file)
@@ -1314,8 +1314,7 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
        if (!dec)
                return NULL;
 
-       if (info.drm_major < 3)
-               dec->use_legacy = true;
+       dec->use_legacy = true;
 
        dec->base = *templ;
        dec->base.context = context;
index e38b927b1d4da22e8a260764683ec93f9a25e8d1..4dae56f95cec1676849c8b9628d525dfdf2dd91f 100644 (file)
@@ -411,10 +411,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
        if (!enc)
                return NULL;
 
-       if (rscreen->info.drm_major == 3)
-               enc->use_vm = true;
-       if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) ||
-            rscreen->info.drm_major == 3)
+       if (rscreen->info.drm_minor >= 42)
                enc->use_vui = true;
 
        enc->base = *templ;
index ca066e898234dd142aaa19dbdbf6724ff4633bcb..6c03c123293288232478df204a1b15c7eb5d4718 100644 (file)
@@ -1250,7 +1250,7 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
        if (!dec)
                return NULL;
 
-       if (sctx->screen->info.drm_major < 3)
+       if (!sctx->screen->info.is_amdgpu)
                dec->use_legacy = true;
 
        dec->base = *templ;
index 94df06e88c6b5334a899109050a400a99d2f374a..264b96b83c98f8f10d7ff01f3887f50bdf9eaa86 100644 (file)
@@ -410,10 +410,10 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
        if (!enc)
                return NULL;
 
-       if (sscreen->info.drm_major == 3)
+       if (sscreen->info.is_amdgpu)
                enc->use_vm = true;
-       if ((sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42) ||
-            sscreen->info.drm_major == 3)
+       if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) ||
+            sscreen->info.is_amdgpu)
                enc->use_vui = true;
        if (sscreen->info.family >= CHIP_TONGA &&
            sscreen->info.family != CHIP_STONEY &&
index 76705937b65fb7844f855f2299186e5f3c955494..614d00b4667177e9a13b7bd890f3ab8243225711 100644 (file)
@@ -155,7 +155,7 @@ void si_init_resource_fields(struct si_screen *sscreen,
                 * persistent buffers into GTT to prevent VRAM CPU page faults.
                 */
                if (!sscreen->info.kernel_flushes_hdp_before_ib ||
-                   sscreen->info.drm_major == 2)
+                   !sscreen->info.is_amdgpu)
                        res->domains = RADEON_DOMAIN_GTT;
        }
 
index 0f2e81dd60034ec4b5c2bb2d2a55c2ff0805b094..4a768ec5a37a6f7900716e02049cd2f1e82e060c 100644 (file)
@@ -322,7 +322,7 @@ static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
        si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
 
        /* No other registers can be read on DRM < 3.1.0. */
-       if (sctx->screen->info.drm_major < 3 ||
+       if (!sctx->screen->info.is_amdgpu ||
            sctx->screen->info.drm_minor < 1) {
                fprintf(f, "\n");
                return;
index 40a54b34c4f25a9e065b214fcd48084ae74df835..c1bddca1a660d5a9cf27e34646d7a4af83af557e 100644 (file)
@@ -628,7 +628,7 @@ static int si_get_video_param(struct pipe_screen *screen,
                                return true;
                        if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
                                return false;
-                       if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
+                       if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
                                RVID_ERR("No MJPEG support for the kernel version\n");
                                return false;
                        }
@@ -920,7 +920,7 @@ static void si_query_memory_info(struct pipe_screen *screen,
        info->device_memory_evicted =
                ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 
-       if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
+       if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
                info->nr_device_memory_evictions =
                        ws->query_value(ws, RADEON_NUM_EVICTIONS);
        else
index 8527999645baaec1a57bb69cb6dcb82a99da3ad9..d0d04bbb3de8462c89a03e806b69f09ed86a317f 100644 (file)
@@ -673,7 +673,7 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
         * implementation for fence_server_sync is incomplete. */
        return threaded_context_create(ctx, &sscreen->pool_transfers,
                                       si_replace_buffer_storage,
-                                      sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
+                                      sscreen->info.is_amdgpu ? si_create_fence : NULL,
                                       &((struct si_context*)ctx)->tc);
 }
 
@@ -1060,7 +1060,7 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
         * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
         * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/
        sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
-                                  sscreen->info.drm_major == 3;
+                                  sscreen->info.is_amdgpu;
 
        sscreen->has_distributed_tess =
                sscreen->info.chip_class >= GFX8 &&
index fd0e07904aaf8c45e329635700badb7dd7f81770..a2b5937d69f295e4ae87724ef92f5834d78c30bc 100644 (file)
@@ -1819,7 +1819,7 @@ static struct pipe_driver_query_info si_driver_query_list[] = {
 static unsigned si_get_num_queries(struct si_screen *sscreen)
 {
        /* amdgpu */
-       if (sscreen->info.drm_major == 3) {
+       if (sscreen->info.is_amdgpu) {
                if (sscreen->info.chip_class >= GFX8)
                        return ARRAY_SIZE(si_driver_query_list);
                else
index 6f98cee8ebd4da2491781cd1006146525d5b7771..fc2e282b82c93eaa1bc62d4e1812b8ecc696eea8 100644 (file)
@@ -4991,7 +4991,7 @@ static void si_init_config(struct si_context *sctx)
 
        /* GFX6, radeon kernel disabled CLEAR_STATE. */
        assert(has_clear_state || sscreen->info.chip_class == GFX6 ||
-              sscreen->info.drm_major != 3);
+              !sscreen->info.is_amdgpu);
 
        if (!pm4)
                return;
index 7aa45b52639d00aa9fceab2a62f7d065bfaccebb..c30b40376a2be7e4e884a82a62930901c286d74c 100644 (file)
@@ -166,6 +166,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.drm_major = version->version_major;
     ws->info.drm_minor = version->version_minor;
     ws->info.drm_patchlevel = version->version_patchlevel;
+    ws->info.is_amdgpu = false;
     drmFreeVersion(version);
 
     /* Get PCI ID. */