info->pci_func = devinfo->businfo.pci->func;
drmFreeDevice(&devinfo);
+ assert(info->drm_major == 3);
+ info->is_amdgpu = true;
+
/* Query hardware and driver information. */
r = amdgpu_query_gpu_info(dev, amdinfo);
if (r) {
return false;
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 27) {
+ if (info->drm_minor >= 27) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
/* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
* This decreases performance by up to 50% when the RB is the bottleneck.
*/
- if (info->family == CHIP_KAVERI && info->drm_major == 2)
+ if (info->family == CHIP_KAVERI && !info->is_amdgpu)
raster_config = 0x00000000;
/* Fiji: Old kernels have incorrect tiling config. This decreases
uint32_t drm_major; /* version */
uint32_t drm_minor;
uint32_t drm_patchlevel;
+ bool is_amdgpu;
bool has_userptr;
bool has_syncobj;
bool has_syncobj_wait_for_submit;
{
struct radeon_info *info = &device->physical_device->rad_info;
- if (info->drm_major == 2 && info->drm_minor < 42)
- return; /* no radeon support */
-
fprintf(f, "Memory-mapped registers:\n");
radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
/* No other registers can be read on DRM < 3.1.0. */
- if (info->drm_major < 3 || info->drm_minor < 1) {
+ if (info->drm_minor < 1) {
fprintf(f, "\n");
return;
}
/* Older kernels didn't always flush the HDP cache before
* CS execution
*/
- if (rscreen->info.drm_major == 2 &&
- rscreen->info.drm_minor < 40) {
+ if (rscreen->info.drm_minor < 40) {
res->domains = RADEON_DOMAIN_GTT;
res->flags |= RADEON_FLAG_GTT_WC;
break;
* ensures all CPU writes finish before the GPU
* executes a command stream.
*/
- if (rscreen->info.drm_major == 2 &&
- rscreen->info.drm_minor < 40)
+ if (rscreen->info.drm_minor < 40)
res->domains = RADEON_DOMAIN_GTT;
}
return 64 * 1024 * 1024;
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
+ return rscreen->b.info.drm_minor >= 43;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
r600_resume_queries(ctx);
}
-static void r600_add_fence_dependency(struct r600_common_context *rctx,
- struct pipe_fence_handle *fence)
-{
- struct radeon_winsys *ws = rctx->ws;
-
- if (rctx->dma.cs)
- ws->cs_add_fence_dependency(rctx->dma.cs, fence, 0);
- ws->cs_add_fence_dependency(rctx->gfx.cs, fence, 0);
-}
-
static void r600_fence_server_sync(struct pipe_context *ctx,
struct pipe_fence_handle *fence)
{
- struct r600_common_context *rctx = (struct r600_common_context *)ctx;
- struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
-
- /* Only amdgpu needs to handle fence dependencies (for fence imports).
- * radeon synchronizes all rings by default and will not implement
+ /* radeon synchronizes all rings by default and will not implement
* fence imports.
*/
- if (rctx->screen->info.drm_major == 2)
- return;
-
- /* Only imported fences need to be handled by fence_server_sync,
- * because the winsys handles synchronizations automatically for BOs
- * within the process.
- *
- * Simply skip unflushed fences here, and the winsys will drop no-op
- * dependencies (i.e. dependencies within the same ring).
- */
- if (rfence->gfx_unflushed.ctx)
- return;
-
- /* All unflushed commands will not start execution before
- * this fence dependency is signalled.
- *
- * Should we flush the context to allow more GPU parallelism?
- */
- if (rfence->sdma)
- r600_add_fence_dependency(rctx, rfence->sdma);
- if (rfence->gfx)
- r600_add_fence_dependency(rctx, rfence->gfx);
}
static void r600_flush_from_st(struct pipe_context *ctx,
info->device_memory_evicted =
ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
- if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
- info->nr_device_memory_evictions =
- ws->query_value(ws, RADEON_NUM_EVICTIONS);
- else
- /* Just return the number of evicted 64KB pages. */
- info->nr_device_memory_evictions = info->device_memory_evicted / 64;
+ /* Just return the number of evicted 64KB pages. */
+ info->nr_device_memory_evictions = info->device_memory_evicted / 64;
}
struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
{
- if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
+ if (rscreen->info.drm_minor >= 42)
return ARRAY_SIZE(r600_driver_query_list);
else
return ARRAY_SIZE(r600_driver_query_list) - 25;
rtex->surface.htile_size = 0;
if (rscreen->chip_class <= EVERGREEN &&
- rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
+ rscreen->info.drm_minor < 26)
return;
/* HW bug on R6xx. */
if (!dec)
return NULL;
- if (info.drm_major < 3)
- dec->use_legacy = true;
+ dec->use_legacy = true;
dec->base = *templ;
dec->base.context = context;
if (!enc)
return NULL;
- if (rscreen->info.drm_major == 3)
- enc->use_vm = true;
- if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) ||
- rscreen->info.drm_major == 3)
+ if (rscreen->info.drm_minor >= 42)
enc->use_vui = true;
enc->base = *templ;
if (!dec)
return NULL;
- if (sctx->screen->info.drm_major < 3)
+ if (!sctx->screen->info.is_amdgpu)
dec->use_legacy = true;
dec->base = *templ;
if (!enc)
return NULL;
- if (sscreen->info.drm_major == 3)
+ if (sscreen->info.is_amdgpu)
enc->use_vm = true;
- if ((sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42) ||
- sscreen->info.drm_major == 3)
+ if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) ||
+ sscreen->info.is_amdgpu)
enc->use_vui = true;
if (sscreen->info.family >= CHIP_TONGA &&
sscreen->info.family != CHIP_STONEY &&
* persistent buffers into GTT to prevent VRAM CPU page faults.
*/
if (!sscreen->info.kernel_flushes_hdp_before_ib ||
- sscreen->info.drm_major == 2)
+ !sscreen->info.is_amdgpu)
res->domains = RADEON_DOMAIN_GTT;
}
si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
/* No other registers can be read on DRM < 3.1.0. */
- if (sctx->screen->info.drm_major < 3 ||
+ if (!sctx->screen->info.is_amdgpu ||
sctx->screen->info.drm_minor < 1) {
fprintf(f, "\n");
return;
return true;
if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
return false;
- if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
+ if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
RVID_ERR("No MJPEG support for the kernel version\n");
return false;
}
info->device_memory_evicted =
ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
- if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
+ if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
info->nr_device_memory_evictions =
ws->query_value(ws, RADEON_NUM_EVICTIONS);
else
* implementation for fence_server_sync is incomplete. */
return threaded_context_create(ctx, &sscreen->pool_transfers,
si_replace_buffer_storage,
- sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
+ sscreen->info.is_amdgpu ? si_create_fence : NULL,
&((struct si_context*)ctx)->tc);
}
* on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
* SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/
sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
- sscreen->info.drm_major == 3;
+ sscreen->info.is_amdgpu;
sscreen->has_distributed_tess =
sscreen->info.chip_class >= GFX8 &&
static unsigned si_get_num_queries(struct si_screen *sscreen)
{
/* amdgpu */
- if (sscreen->info.drm_major == 3) {
+ if (sscreen->info.is_amdgpu) {
if (sscreen->info.chip_class >= GFX8)
return ARRAY_SIZE(si_driver_query_list);
else
/* GFX6, radeon kernel disabled CLEAR_STATE. */
assert(has_clear_state || sscreen->info.chip_class == GFX6 ||
- sscreen->info.drm_major != 3);
+ !sscreen->info.is_amdgpu);
if (!pm4)
return;
ws->info.drm_major = version->version_major;
ws->info.drm_minor = version->version_minor;
ws->info.drm_patchlevel = version->version_patchlevel;
+ ws->info.is_amdgpu = false;
drmFreeVersion(version);
/* Get PCI ID. */