sim: Fix handling of constant-connected cell inputs at startup

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 59bf5a71238d709d9cd0ef43745fa1bbc324e291..03ca42cf3c2ae457f3d3ead8de005d21f05e24b5 100644 (file)
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -128,8 +128,12 @@ struct SimInstance
 
                        for (auto &port : cell->connections()) {
                                if (cell->input(port.first))
-                                       for (auto bit : sigmap(port.second))
+                                       for (auto bit : sigmap(port.second)) {
                                                upd_cells[bit].insert(cell);
+                                               // Make sure cell inputs connected to constants are updated in the first cycle
+                                               if (bit.wire == nullptr)
+                                                       dirty_bits.insert(bit);
+                                       }
                        }
 
                        if (cell->type.in(ID($dff))) {

diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys
new file mode 100644 (file)
index 0000000..d778b92
--- /dev/null
+++ b/tests/various/sim_const.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+
+module top(input clk, output reg [1:0] q);
+       wire [1:0] x = 2'b10;
+       always @(posedge clk)
+               q <= x & 2'b11;
+endmodule
+EOT
+
+proc
+sim -clock clk -n 1 -w top
+select -assert-count 1 a:init=2'b10 top/q %i
+