gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.
authorEric Anholt <eric@anholt.net>
Thu, 27 Jul 2017 19:05:56 +0000 (12:05 -0700)
committerEric Anholt <eric@anholt.net>
Tue, 10 Oct 2017 17:45:22 +0000 (10:45 -0700)
Because vc4 can control the order that tiles are rasterized in, we can use
it to implement overlapping blits using normal drawing and
GL_ARB_texture_barrier, as long as we can tell the kernel what order to
render the tiles in.

This commit introduces the core gallium support, vc4 changes will follow.

v2: Fix on the simulator.
v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
v5: Drop vc4 changes from this commit, for clarity.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)
18 files changed:
src/gallium/docs/source/screen.rst
src/gallium/drivers/etnaviv/etnaviv_screen.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/i915/i915_screen.c
src/gallium/drivers/llvmpipe/lp_screen.c
src/gallium/drivers/nouveau/nv30/nv30_screen.c
src/gallium/drivers/nouveau/nv50/nv50_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/r300/r300_screen.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/softpipe/sp_screen.c
src/gallium/drivers/svga/svga_screen.c
src/gallium/drivers/swr/swr_screen.cpp
src/gallium/drivers/vc4/vc4_screen.c
src/gallium/drivers/virgl/virgl_screen.c
src/gallium/include/pipe/p_defines.h
src/gallium/include/pipe/p_state.h

index b968b8c57333ca0d9ae740a3ca42cb219d7f2367..bc0db429b38435d11d062dbca3a6585f71e7c08d 100644 (file)
@@ -408,6 +408,9 @@ The integer capabilities:
   with constant buffers.
 * ``PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS``: Any TGSI register can be used as
   an address for indirect register indexing.
+* ``PIPE_CAP_TILE_RASTER_ORDER``: Whether the driver supports
+  GL_MESA_tile_raster_order, using the tile_raster_order_* fields in
+  pipe_rasterizer_state.
 
 
 .. _pipe_capf:
index 13258bf3534da60059fd8675fb19262731a8963f..738605a4f302d0033496a86119967aae0666cdc3 100644 (file)
@@ -265,6 +265,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
 
    /* Stream output. */
index 341221f9e31ea0a4860ef5ae53bb33c8c1251095..6de381c8fb8ac96ebbfead7f0c78e7a50e7b724c 100644 (file)
@@ -326,6 +326,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MEMOBJ:
        case PIPE_CAP_LOAD_CONSTBUF:
        case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+       case PIPE_CAP_TILE_RASTER_ORDER:
                return 0;
 
        case PIPE_CAP_MAX_VIEWPORTS:
index 6d74bbfd1629a0ad373d818b78a6987f4d4933ba..8b9574e1415819779e62fba7378e9a0a23ed14f0 100644 (file)
@@ -318,6 +318,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
 
    case PIPE_CAP_MAX_VIEWPORTS:
index 64826575b3d61cbf9140fe51b287dcfde93cc608..bffc6b52792b3f5b25b38f2329a8959220f46eb4 100644 (file)
@@ -361,6 +361,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
    }
    /* should only get here on unhandled cases */
index 0450bbb0f1c02e645a205a9412b8e28de34d808a..fedd3c142fbcdf5585d753c0667e6eec4d45c308 100644 (file)
@@ -225,6 +225,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index b08e5e58d2835f64c69a1d68c7dd6479140c42e5..d1e6e8b5eb51c76684c725b8f09719b69af844f9 100644 (file)
@@ -277,6 +277,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index 3bead857ed4663e620519ec4f39bb936d32545be..d49131c79e3a0a2680416931196e4df0c4f39a4f 100644 (file)
@@ -306,6 +306,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index dc37ab2a5388f1fb787b07c85ee99b98f31a6aad..c0cf6e54468362d8797d1ab5c36581553c5a20d5 100644 (file)
@@ -247,6 +247,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         case PIPE_CAP_MEMOBJ:
         case PIPE_CAP_LOAD_CONSTBUF:
         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+        case PIPE_CAP_TILE_RASTER_ORDER:
             return 0;
 
         /* SWTCL-only features. */
index de87874b565145071eeff3ad58b528193d5f16aa..ffcaa15ec9b3d115dc48910050b17a5cd718c61c 100644 (file)
@@ -403,6 +403,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_MEMOBJ:
        case PIPE_CAP_LOAD_CONSTBUF:
        case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+       case PIPE_CAP_TILE_RASTER_ORDER:
                return 0;
 
        case PIPE_CAP_DOUBLES:
index 43849877e252e860de1429ee638cb2b0e2800a3f..82ed3d7b527417992dbe2a2ffc63d7bef6ed72a2 100644 (file)
@@ -589,6 +589,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_UMA:
        case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
        case PIPE_CAP_POST_DEPTH_COVERAGE:
+       case PIPE_CAP_TILE_RASTER_ORDER:
                return 0;
 
        case PIPE_CAP_QUERY_BUFFER_OBJECT:
index b1010a6cd564ac9f9c9ec72b9c9fadbfbddc72eb..fe354b1c137727b46148997031b7fcc92b64ff14 100644 (file)
@@ -312,6 +312,7 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
       return 4;
index fd9f78b2fc6bf9038ecd11f2eec9106d49c9f41d..ebadf3ed5b1035c9cd7d7bced5106438dcbe8285 100644 (file)
@@ -457,6 +457,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
    }
 
index eeb10a9a4d42623f7dfe66247cad208c10b4b642..639b18f930fc0916f3bc80c2b16c70dbdc363d57 100644 (file)
@@ -343,6 +343,7 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index 6b757532158109f6eff18df99af1771fe4566cac..120e404fa410f8f829dfd6e3a508a91749809545 100644 (file)
@@ -266,6 +266,7 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MEMOBJ:
         case PIPE_CAP_LOAD_CONSTBUF:
        case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+       case PIPE_CAP_TILE_RASTER_ORDER:
                 return 0;
 
                 /* Stream output. */
index e9139cea655dbef1ad0ae44f3ac39f4ff11218a6..28023f81119f9c7c3d8534952cca8dcb85402a72 100644 (file)
@@ -270,6 +270,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MEMOBJ:
    case PIPE_CAP_LOAD_CONSTBUF:
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+   case PIPE_CAP_TILE_RASTER_ORDER:
       return 0;
    case PIPE_CAP_VENDOR_ID:
       return 0x1af4;
index 212c4af8f707251a854ab9ae4211c47f70eec339..11af6c8d0d89f7d78c1be88e21d1eac78601565a 100644 (file)
@@ -778,6 +778,7 @@ enum pipe_cap
    PIPE_CAP_MEMOBJ,
    PIPE_CAP_LOAD_CONSTBUF,
    PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS,
+   PIPE_CAP_TILE_RASTER_ORDER,
 };
 
 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
index 86c7751eb185520f9f38589a2db806108f911faa..10bf678652d5ce69834224d6d085f11195f4d217 100644 (file)
@@ -124,6 +124,16 @@ struct pipe_rasterizer_state
     */
    unsigned rasterizer_discard:1;
 
+   /**
+    * Exposed by PIPE_CAP_TILE_RASTER_ORDER.  When true,
+    * tile_raster_order_increasing_* indicate the order that the rasterizer
+    * should render tiles, to meet the requirements of
+    * GL_MESA_tile_raster_order.
+    */
+   unsigned tile_raster_order_fixed:1;
+   unsigned tile_raster_order_increasing_x:1;
+   unsigned tile_raster_order_increasing_y:1;
+
    /**
     * When false, depth clipping is disabled and the depth value will be
     * clamped later at the per-pixel level before depth testing.