+2019-12-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25274
+ * config/tc-i386.c (optimize_encoding): Also check R12-R15
+ registers for "test $imm7, %r64/%r32/%r16 -> test $imm7, %r8"
+ optimization.
+ * testsuite/gas/i386/x86-64-optimize-3.s: Add tests for test
+ with r12.
+ * testsuite/gas/i386/x86-64-optimize-3.d: Updated.
+ * testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.
+
2019-12-12 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/align-branch-1.s: New file.
i.types[1].bitfield.byte = 1;
/* Ignore the suffix. */
i.suffix = 0;
- if (base_regnum >= 4
- && !(i.op[1].regs->reg_flags & RegRex))
+ if (base_regnum >= 4)
{
- /* Handle SP, BP, SI and DI registers. */
+ /* Handle SP, BP, SI, DI and R12-R15 registers. */
if (i.types[1].bitfield.word)
j = 16;
else if (i.types[1].bitfield.dword)
+[a-f0-9]+: 41 f6 c1 7f test \$0x7f,%r9b
+[a-f0-9]+: 41 f6 c1 7f test \$0x7f,%r9b
+[a-f0-9]+: 41 f6 c1 7f test \$0x7f,%r9b
+ +[a-f0-9]+: 41 f6 c4 7f test \$0x7f,%r12b
+ +[a-f0-9]+: 41 f6 c4 7f test \$0x7f,%r12b
+ +[a-f0-9]+: 41 f6 c4 7f test \$0x7f,%r12b
+ +[a-f0-9]+: 41 f6 c4 7f test \$0x7f,%r12b
+[a-f0-9]+: 20 c9 and %cl,%cl
+[a-f0-9]+: 66 21 d2 and %dx,%dx
+[a-f0-9]+: 21 db and %ebx,%ebx
test $0x7f, %r9d
test $0x7f, %r9w
test $0x7f, %r9b
+ test $0x7f, %r12
+ test $0x7f, %r12d
+ test $0x7f, %r12w
+ test $0x7f, %r12b
and %cl, %cl
and %dx, %dx
+[a-f0-9]+: 41 f7 c1 7f 00 00 00 test \$0x7f,%r9d
+[a-f0-9]+: 66 41 f7 c1 7f 00 test \$0x7f,%r9w
+[a-f0-9]+: 41 f6 c1 7f test \$0x7f,%r9b
+ +[a-f0-9]+: 41 f7 c4 7f 00 00 00 test \$0x7f,%r12d
+ +[a-f0-9]+: 41 f7 c4 7f 00 00 00 test \$0x7f,%r12d
+ +[a-f0-9]+: 66 41 f7 c4 7f 00 test \$0x7f,%r12w
+ +[a-f0-9]+: 41 f6 c4 7f test \$0x7f,%r12b
+[a-f0-9]+: 84 c9 test %cl,%cl
+[a-f0-9]+: 66 85 d2 test %dx,%dx
+[a-f0-9]+: 21 db and %ebx,%ebx