(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index e3def5e060bf966fdb20be0967ead4893f235c5b..4c01dc145e7d140f32fce0816ec55e86e64f614a 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -555,8 +555,10 @@ in the other, or
 not added at all in either.[^whoops]
 
 \newpage{}
-# Potential Opcode allocation solution
+# Potential Opcode allocation solution (superseded)
 
+*Note this scheme is superseded below but kept for completeness as it
+defines terms and context*.
 There are unfortunately some inviolate requirements that directly place
 pressure on the EXT000-EXT063 (32-bit) opcode space to such a degree that
 it risks jeapordising the Power ISA. These requirements are:
@@ -621,9 +623,8 @@ allocation to new POs, `RESERVED2` does not.[^only2]
   it is a pure **Scalar-only** word-length PO Group. It may remain `RESERVED`.
 * **`RESERVED1`:{EXT200-263}** is also a new set of 64 word-length Major
   Opcodes.
-  These opcodes do not *need* to be Simple-V-Augmented
-  *but the option to do so exists* should an Implementor choose to do so.
-  This is unlike `EXT300-363` which may **never** be Simple-V-Augmented
+  These opcodes would be Simple-V-Augmentable
+  unlike `EXT300-363` which may **never** be Simple-V-Augmented
   under any circumstances.
 * **RESERVED3:`SVP64-Single:{EXT200-263}`** - Major opcodes 200-263 with
   Single-Augmentation, providing a one-bit predicate mask, element-width