x, y, z);
}
+void
+radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
+ VkImageAspectFlagBits aspects)
+{
+ cmd_buffer->state.current_event_type = (aspects & VK_IMAGE_ASPECT_COLOR_BIT) ?
+ EventRenderPassColorClear : EventRenderPassDepthStencilClear;
+}
+
+void
+radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer)
+{
+ cmd_buffer->state.current_event_type = EventInternalUnknown;
+}
+
#define EVENT_MARKER(cmd_name, args...) \
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); \
radv_write_begin_general_api_marker(cmd_buffer, ApiCmd##cmd_name); \
.layerCount = cmd_state->framebuffer->layers,
};
+ radv_describe_begin_render_pass_clear(cmd_buffer, clear_att->aspectMask);
+
emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
view_mask & ~attachment->cleared_views, ds_resolve_clear);
if (view_mask)
attachment->cleared_views |= view_mask;
else
attachment->pending_clear_aspects = 0;
+
+ radv_describe_end_render_pass_clear(cmd_buffer);
}
/**
void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
+void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
+ VkImageAspectFlagBits aspects);
+void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
struct radeon_winsys_sem;