radv/sqtt: describe render pass color/depthstencil clears
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 3 Mar 2020 13:06:26 +0000 (14:06 +0100)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 10 Mar 2020 09:05:40 +0000 (10:05 +0100)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>

src/amd/vulkan/layers/radv_sqtt_layer.c
src/amd/vulkan/radv_meta_clear.c
src/amd/vulkan/radv_private.h

index e962b27f65edee438547154c1b100ce0ae4c0897..1d999c5917ffddfad8ae8646fc8ecf94220da3c6 100644 (file)
@@ -398,6 +398,20 @@ radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z)
                                          x, y, z);
 }
 
+void
+radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
+                                     VkImageAspectFlagBits aspects)
+{
+       cmd_buffer->state.current_event_type = (aspects & VK_IMAGE_ASPECT_COLOR_BIT) ?
+               EventRenderPassColorClear : EventRenderPassDepthStencilClear;
+}
+
+void
+radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer)
+{
+       cmd_buffer->state.current_event_type = EventInternalUnknown;
+}
+
 #define EVENT_MARKER(cmd_name, args...) \
        RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); \
        radv_write_begin_general_api_marker(cmd_buffer, ApiCmd##cmd_name); \
index 6a66665d06d4ad0f0b61478744dd9f42b5598596..6d6f11b0662bc2b79ce72e8ac804b1116fa5f372 100644 (file)
@@ -1957,12 +1957,16 @@ radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
                .layerCount = cmd_state->framebuffer->layers,
        };
 
+       radv_describe_begin_render_pass_clear(cmd_buffer, clear_att->aspectMask);
+
        emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
                   view_mask & ~attachment->cleared_views, ds_resolve_clear);
        if (view_mask)
                attachment->cleared_views |= view_mask;
        else
                attachment->pending_clear_aspects = 0;
+
+       radv_describe_end_render_pass_clear(cmd_buffer);
 }
 
 /**
index 8817a743fb3d984e2157b216b588e258cc2a7c7c..e4c6a67032c3644febbb2488d36f7f4e4bb0dbf1 100644 (file)
@@ -2428,6 +2428,9 @@ void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
+void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
+                                          VkImageAspectFlagBits aspects);
+void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
 
 struct radeon_winsys_sem;