ecp5: Fix DPR16X4 sim model.

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 357fd917302935883cfe6f0c351bf4175c2cdd7e..a5f905cf819a19f1928c5b3d233d99fc8b237f2c 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -204,7 +204,7 @@ module TRELLIS_DPR16X4 (
        integer i;
        initial begin
                for (i = 0; i < 16; i = i + 1)
-                       mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
+                       mem[i] <= INITVAL[4*i +: 4];
        end
 
        wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;