Update phase param in the .py file for the cpus

--HG--
extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803

diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 2f702a4bf919803b8f3e184c0e6ac8bec964d70e..8037c90af865d9207a1762f3669f555e9c3d2285 100644 (file)
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -47,6 +47,7 @@ class BaseCPU(SimObject):
         "defer registration with system (for sampling)")
 
     clock = Param.Clock(Parent.clock, "clock speed")
+    phase = Param.Latency("0ns", "clock phase")
 
     _mem_ports = []