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[PATCH][Aarch64][gcc] Fix vld2/3/4 on big endian systems
authorTamar Christina <tamar.christina@arm.com>
Tue, 30 Aug 2016 15:40:19 +0000 (15:40 +0000)
committerJames Greenhalgh <jgreenhalgh@gcc.gnu.org>
Tue, 30 Aug 2016 15:40:19 +0000 (15:40 +0000)
On behalf of Tamar Christina  <tamar.christina@arm.com>

gcc/

* gcc/config/aarch64/aarch64-simd.md
(aarch64_ld2<mode>_dreg_le): New.
(aarch64_ld2<mode>_dreg_be): New.
(aarch64_ld2<mode>_dreg): Removed.
(aarch64_ld3<mode>_dreg_le): New.
(aarch64_ld3<mode>_dreg_be): New.
(aarch64_ld3<mode>_dreg): Removed.
(aarch64_ld4<mode>_dreg_le): New.
(aarch64_ld4<mode>_dreg_be): New.
(aarch64_ld4<mode>_dreg): Removed.
(aarch64_ld<VSTRUCT:nregs><VDC:mode>): Wrapper around _le, _be.

From-SVN: r239865

gcc/ChangeLog patch | blob | history
gcc/config/aarch64/aarch64-simd.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 040c6c37f26d96e74f34002b180f35178f987861..c6bda6055fd394f5f83dce25f391339d68e8088a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2016-08-30  Tamar Christina  <tamar.christina@arm.com>
+
+       * gcc/config/aarch64/aarch64-simd.md
+       (aarch64_ld2<mode>_dreg_le): New.
+       (aarch64_ld2<mode>_dreg_be): New.
+       (aarch64_ld2<mode>_dreg): Removed.
+       (aarch64_ld3<mode>_dreg_le): New.
+       (aarch64_ld3<mode>_dreg_be): New.
+       (aarch64_ld3<mode>_dreg): Removed.
+       (aarch64_ld4<mode>_dreg_le): New.
+       (aarch64_ld4<mode>_dreg_be): New.
+       (aarch64_ld4<mode>_dreg): Removed.
+       (aarch64_ld<VSTRUCT:nregs><VDC:mode>): Wrapper around _le, _be.
+
 2016-08-30  David Malcolm  <dmalcolm@redhat.com>
 
        * diagnostic-show-locus.c (test_one_liner_fixit_insert): Remove
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 70140744bb5a7b6dded304c16291cfdce4375c10..f942a54a7abbe5dca30fb37f0e1360f7b623601c 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4901,7 +4901,7 @@
   DONE;
 })
 
-(define_insn "aarch64_ld2<mode>_dreg"
+(define_insn "aarch64_ld2<mode>_dreg_le"
   [(set (match_operand:OI 0 "register_operand" "=w")
        (subreg:OI
          (vec_concat:<VRL2>
@@ -4914,12 +4914,30 @@
             (unspec:VD [(match_dup 1)]
                        UNSPEC_LD2)
             (vec_duplicate:VD (const_int 0)))) 0))]
-  "TARGET_SIMD"
+  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+  "ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
+  [(set_attr "type" "neon_load2_2reg<q>")]
+)
+
+(define_insn "aarch64_ld2<mode>_dreg_be"
+  [(set (match_operand:OI 0 "register_operand" "=w")
+       (subreg:OI
+         (vec_concat:<VRL2>
+           (vec_concat:<VDBL>
+            (vec_duplicate:VD (const_int 0))
+            (unspec:VD
+               [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
+               UNSPEC_LD2))
+           (vec_concat:<VDBL>
+            (vec_duplicate:VD (const_int 0))
+            (unspec:VD [(match_dup 1)]
+                       UNSPEC_LD2))) 0))]
+  "TARGET_SIMD && BYTES_BIG_ENDIAN"
   "ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
   [(set_attr "type" "neon_load2_2reg<q>")]
 )
 
-(define_insn "aarch64_ld2<mode>_dreg"
+(define_insn "aarch64_ld2<mode>_dreg_le"
   [(set (match_operand:OI 0 "register_operand" "=w")
        (subreg:OI
          (vec_concat:<VRL2>
@@ -4932,12 +4950,30 @@
             (unspec:DX [(match_dup 1)]
                        UNSPEC_LD2)
             (const_int 0))) 0))]
-  "TARGET_SIMD"
+  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
   "ld1\\t{%S0.1d - %T0.1d}, %1"
   [(set_attr "type" "neon_load1_2reg<q>")]
 )
 
-(define_insn "aarch64_ld3<mode>_dreg"
+(define_insn "aarch64_ld2<mode>_dreg_be"
+  [(set (match_operand:OI 0 "register_operand" "=w")
+       (subreg:OI
+         (vec_concat:<VRL2>
+           (vec_concat:<VDBL>
+            (const_int 0)
+            (unspec:DX
+               [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
+               UNSPEC_LD2))
+           (vec_concat:<VDBL>
+            (const_int 0)
+            (unspec:DX [(match_dup 1)]
+                       UNSPEC_LD2))) 0))]
+  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+  "ld1\\t{%S0.1d - %T0.1d}, %1"
+  [(set_attr "type" "neon_load1_2reg<q>")]
+)
+
+(define_insn "aarch64_ld3<mode>_dreg_le"
   [(set (match_operand:CI 0 "register_operand" "=w")
        (subreg:CI
         (vec_concat:<VRL3>
@@ -4955,12 +4991,35 @@
             (unspec:VD [(match_dup 1)]
                        UNSPEC_LD3)
             (vec_duplicate:VD (const_int 0)))) 0))]
-  "TARGET_SIMD"
+  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
   "ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
   [(set_attr "type" "neon_load3_3reg<q>")]
 )
 
-(define_insn "aarch64_ld3<mode>_dreg"
+(define_insn "aarch64_ld3<mode>_dreg_be"
+  [(set (match_operand:CI 0 "register_operand" "=w")
+       (subreg:CI
+        (vec_concat:<VRL3>
+         (vec_concat:<VRL2>
+           (vec_concat:<VDBL>
+            (vec_duplicate:VD (const_int 0))
+            (unspec:VD
+               [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
+               UNSPEC_LD3))
+           (vec_concat:<VDBL>
+            (vec_duplicate:VD (const_int 0))
+            (unspec:VD [(match_dup 1)]
+                       UNSPEC_LD3)))
+         (vec_concat:<VDBL>
+            (vec_duplicate:VD (const_int 0))
+            (unspec:VD [(match_dup 1)]
+                       UNSPEC_LD3))) 0))]
+  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+  "ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
+  [(set_attr "type" "neon_load3_3reg<q>")]
+)
+
+(define_insn "aarch64_ld3<mode>_dreg_le"
   [(set (match_operand:CI 0 "register_operand" "=w")
        (subreg:CI
         (vec_concat:<VRL3>
@@ -4978,12 +5037,35 @@
             (unspec:DX [(match_dup 1)]
                        UNSPEC_LD3)
             (const_int 0))) 0))]
-  "TARGET_SIMD"
+  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+  "ld1\\t{%S0.1d - %U0.1d}, %1"
+  [(set_attr "type" "neon_load1_3reg<q>")]
+)
+
+(define_insn "aarch64_ld3<mode>_dreg_be"
+  [(set (match_operand:CI 0 "register_operand" "=w")
+       (subreg:CI
+        (vec_concat:<VRL3>
+         (vec_concat:<VRL2>
+           (vec_concat:<VDBL>
+            (const_int 0)
+            (unspec:DX
+               [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
+               UNSPEC_LD3))
+           (vec_concat:<VDBL>
+            (const_int 0)
+            (unspec:DX [(match_dup 1)]
+                       UNSPEC_LD3)))
+         (vec_concat:<VDBL>
+            (const_int 0)
+            (unspec:DX [(match_dup 1)]
+                       UNSPEC_LD3))) 0))]
+  "TARGET_SIMD && BYTES_BIG_ENDIAN"
   "ld1\\t{%S0.1d - %U0.1d}, %1"
   [(set_attr "type" "neon_load1_3reg<q>")]
 )
 
-(define_insn "aarch64_ld4<mode>_dreg"
+(define_insn "aarch64_ld4<mode>_dreg_le"
   [(set (match_operand:XI 0 "register_operand" "=w")
        (subreg:XI
         (vec_concat:<VRL4>
@@ -4994,9 +5076,9 @@
                UNSPEC_LD4)
               (vec_duplicate:VD (const_int 0)))
              (vec_concat:<VDBL>
-               (unspec:VD [(match_dup 1)]
+               (unspec:VD [(match_dup 1)]
                        UNSPEC_LD4)
-               (vec_duplicate:VD (const_int 0))))
+               (vec_duplicate:VD (const_int 0))))
           (vec_concat:<VRL2>
             (vec_concat:<VDBL>
               (unspec:VD [(match_dup 1)]
@@ -5006,12 +5088,40 @@
               (unspec:VD [(match_dup 1)]
                        UNSPEC_LD4)
               (vec_duplicate:VD (const_int 0))))) 0))]
-  "TARGET_SIMD"
+  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
   "ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
   [(set_attr "type" "neon_load4_4reg<q>")]
 )
 
-(define_insn "aarch64_ld4<mode>_dreg"
+(define_insn "aarch64_ld4<mode>_dreg_be"
+  [(set (match_operand:XI 0 "register_operand" "=w")
+       (subreg:XI
+        (vec_concat:<VRL4>
+          (vec_concat:<VRL2>
+            (vec_concat:<VDBL>
+              (vec_duplicate:VD (const_int 0))
+              (unspec:VD
+               [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
+               UNSPEC_LD4))
+             (vec_concat:<VDBL>
+               (vec_duplicate:VD (const_int 0))
+               (unspec:VD [(match_dup 1)]
+                       UNSPEC_LD4)))
+          (vec_concat:<VRL2>
+            (vec_concat:<VDBL>
+              (vec_duplicate:VD (const_int 0))
+              (unspec:VD [(match_dup 1)]
+                       UNSPEC_LD4))
+            (vec_concat:<VDBL>
+              (vec_duplicate:VD (const_int 0))
+              (unspec:VD [(match_dup 1)]
+                       UNSPEC_LD4)))) 0))]
+  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+  "ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
+  [(set_attr "type" "neon_load4_4reg<q>")]
+)
+
+(define_insn "aarch64_ld4<mode>_dreg_le"
   [(set (match_operand:XI 0 "register_operand" "=w")
        (subreg:XI
         (vec_concat:<VRL4>
@@ -5024,7 +5134,7 @@
              (vec_concat:<VDBL>
                (unspec:DX [(match_dup 1)]
                        UNSPEC_LD4)
-               (const_int 0)))
+               (const_int 0)))
           (vec_concat:<VRL2>
             (vec_concat:<VDBL>
               (unspec:DX [(match_dup 1)]
@@ -5034,7 +5144,35 @@
               (unspec:DX [(match_dup 1)]
                        UNSPEC_LD4)
               (const_int 0)))) 0))]
-  "TARGET_SIMD"
+  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+  "ld1\\t{%S0.1d - %V0.1d}, %1"
+  [(set_attr "type" "neon_load1_4reg<q>")]
+)
+
+(define_insn "aarch64_ld4<mode>_dreg_be"
+  [(set (match_operand:XI 0 "register_operand" "=w")
+       (subreg:XI
+        (vec_concat:<VRL4>
+          (vec_concat:<VRL2>
+            (vec_concat:<VDBL>
+              (const_int 0)
+              (unspec:DX
+               [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
+               UNSPEC_LD4))
+             (vec_concat:<VDBL>
+               (const_int 0)
+               (unspec:DX [(match_dup 1)]
+                       UNSPEC_LD4)))
+          (vec_concat:<VRL2>
+            (vec_concat:<VDBL>
+              (const_int 0)
+              (unspec:DX [(match_dup 1)]
+                       UNSPEC_LD4))
+            (vec_concat:<VDBL>
+              (const_int 0)
+              (unspec:DX [(match_dup 1)]
+                       UNSPEC_LD4)))) 0))]
+  "TARGET_SIMD && BYTES_BIG_ENDIAN"
   "ld1\\t{%S0.1d - %V0.1d}, %1"
   [(set_attr "type" "neon_load1_4reg<q>")]
 )
@@ -5048,7 +5186,12 @@
   rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
   set_mem_size (mem, <VSTRUCT:nregs> * 8);
 
-  emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg (operands[0], mem));
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg_be (operands[0],
+                                                               mem));
+  else
+    emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg_le (operands[0],
+                                                               mem));
   DONE;
 })