litedram: Update yaml files

Update the litedram yaml files based on latest upstream.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/litedram/gen-src/acorn-cle-215.yml b/litedram/gen-src/acorn-cle-215.yml
index bce467bdd3159429b5f1444472b77a00cbdc4462..0e3e9eb99ae8226f4b19efb5319cee7e45b6cd6f 100644 (file)
--- a/litedram/gen-src/acorn-cle-215.yml
+++ b/litedram/gen-src/acorn-cle-215.yml
@@ -3,13 +3,11 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -2,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
     # PHY ----------------------------------------------------------------------
-    "cmd_delay":       0,             # Command additional delay (in taps)
     "cmd_latency":     0,             # Command additional latency
     "sdram_module":    "MT41K512M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 2,             # Number of byte groups
@@ -35,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }

diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml
index 4472d5673f31695a19cc9a0637d684b03f6f6c4d..22a01907c7f558f08ba4539511cbae72cdb81731 100644 (file)
--- a/litedram/gen-src/arty.yml
+++ b/litedram/gen-src/arty.yml
@@ -3,13 +3,11 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
     # PHY ----------------------------------------------------------------------
-    "cmd_delay":       0,             # Command additional delay (in taps)
     "cmd_latency":     0,             # Command additional latency
     "sdram_module":    "MT41K128M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 2,             # Number of byte groups
@@ -35,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }

diff --git a/litedram/gen-src/genesys2.yml b/litedram/gen-src/genesys2.yml
index 6cf8ac1e6d03ca9727116b0cd0928ae4c0ee81a8..ac1deeb6605a03f203309572b740401a3e656e06 100644 (file)
--- a/litedram/gen-src/genesys2.yml
+++ b/litedram/gen-src/genesys2.yml
@@ -3,8 +3,7 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -2,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
@@ -13,12 +12,12 @@
     "sdram_module":    "MT41J256M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 4,             # Number of byte groups
     "sdram_rank_nb":   1,             # Number of ranks
-    "sdram_phy":       K7DDRPHY,      # Type of FPGA PHY
+    "sdram_phy":       "K7DDRPHY",    # Type of FPGA PHY
 
     # Electrical ---------------------------------------------------------------
-    "rtt_nom": "60ohm", # Nominal termination
-    "rtt_wr":  "60ohm", # Write termination
-    "ron":     "34ohm", # Output driver impedance
+    "rtt_nom": "60ohm",  # Nominal termination
+    "rtt_wr":  "60ohm",  # Write termination
+    "ron":     "34ohm",  # Output driver impedance
 
     # Frequency ----------------------------------------------------------------
     "input_clk_freq":   200e6, # Input clock frequency
@@ -34,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }

diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml
index 287f2f24aa83afa39870d55d61a1ea81585e79fb..375210482c70865fa5419ac9e333a5a62221e557 100644 (file)
--- a/litedram/gen-src/nexys-video.yml
+++ b/litedram/gen-src/nexys-video.yml
@@ -3,13 +3,11 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
     # PHY ----------------------------------------------------------------------
-    "cmd_delay":       0,             # Command additional delay (in taps)
     "cmd_latency":     0,             # Command additional latency
     "sdram_module":    "MT41K256M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 2,             # Number of byte groups
@@ -35,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }

diff --git a/litedram/gen-src/sim.yml b/litedram/gen-src/sim.yml
index 0160000b4716c43bc737d183177c7447531e2ef4..22a01907c7f558f08ba4539511cbae72cdb81731 100644 (file)
--- a/litedram/gen-src/sim.yml
+++ b/litedram/gen-src/sim.yml
@@ -3,14 +3,11 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
-    "sim" : "True",
 
     # PHY ----------------------------------------------------------------------
-    "cmd_delay":       0,             # Command additional delay (in taps)
     "cmd_latency":     0,             # Command additional latency
     "sdram_module":    "MT41K128M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 2,             # Number of byte groups
@@ -36,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }