Fix multiple driver issue
authorEddie Hung <eddie@fpgeh.com>
Wed, 27 Nov 2019 21:21:59 +0000 (13:21 -0800)
committerEddie Hung <eddie@fpgeh.com>
Wed, 27 Nov 2019 21:21:59 +0000 (13:21 -0800)
passes/hierarchy/submod.cc

index b21b0de017fa3e857572e53749926bdbd6346244..839f8561cd418a407116c78cc0e5a9339f0c59a0 100644 (file)
@@ -228,11 +228,16 @@ struct SubmodWorker
                                RTLIL::SigSpec old_sig = sigmap(it.first);
                                RTLIL::Wire *new_wire = it.second.new_wire;
                                if (new_wire->port_id > 0) {
-                                       // Prevents "ERROR: Mismatch in directionality ..." when flattening
                                        if (new_wire->port_output)
-                                               for (auto &b : old_sig)
+                                               for (int i = 0; i < GetSize(old_sig); i++) {
+                                                       auto &b = old_sig[i];
+                                                       // Prevents "ERROR: Mismatch in directionality ..." when flattening
                                                        if (!b.wire)
                                                                b = module->addWire(NEW_ID);
+                                                       // Prevents "Warning: multiple conflicting drivers ..."
+                                                       else if (!it.second.is_int_driven[i])
+                                                               b = module->addWire(NEW_ID);
+                                               }
                                        new_cell->setPort(new_wire->name, old_sig);
                                }
                        }