#define CONST_OK_FOR_LETTER_P(VALUE, C) \
( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
- : (C) == 'J' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff0000u)) == 0 \
+ : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000u)) == 0 \
: (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
: (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
&& ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
/* The current return address is in link register (65). The return address
of anything farther back is accessed normally at an offset of 8 from the
frame pointer. */
-#define RETURN_ADDR_RTX(count, frame) \
- ((count == -1) \
+#define RETURN_ADDR_RTX(COUNT, FRAME) \
+ (((COUNT) == -1) \
? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) \
: gen_rtx_MEM (Pmode, \
memory_address \
plus_constant (copy_to_reg \
(gen_rtx_MEM (Pmode, \
memory_address (Pmode, \
- frame))), \
+ (FRAME)))), \
RETURN_ADDRESS_OFFSET))))
\f
/* Definitions for register eliminations.
{ \
HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
- HOST_WIDE_INT high \
- = (((val - low) & 0xffffffffu) ^ 0x80000000u) - 0x80000000u; \
+ unsigned HOST_WIDE_INT high \
+ = (((val - low) & 0xffffffffu) ^ 0x80000000u) - 0x80000000u; \
\
/* Check for 32-bit overflow. */ \
if (high + low != val) \
}
}")
-(define_insn ""
+(define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
(match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
"gpc_reg_operand (operands[0], SImode)
operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
}")
-(define_insn ""
+(define_insn "*movsi_internal2"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
(const_int 0)))
}
}")
-(define_insn "*movdi_32"
+(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
(match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
"! TARGET_POWERPC64
operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
}")
-(define_insn "*movdi_64"
+(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
(match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
"TARGET_POWERPC64
#endif
}")
-(define_insn ""
+(define_insn "*movdi_internal2"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
(const_int 0)))
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
-\f
+
(define_split
[(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
(compare:CC (match_dup 0)
(const_int 0)))]
"")
-
+\f
;; TImode is similar, except that we usually want to compute the address into
;; a register and use lsi/stsi (the exception is during reload). MQ is also
;; clobbered in stsi for POWER, so we need a SCRATCH for it.
}")
\f
;; Here are the actual compare insns.
-(define_insn ""
+(define_insn "*cmpsi_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
"{cmp%I2|cmpw%I2} %0,%1,%2"
[(set_attr "type" "compare")])
-(define_insn ""
+(define_insn "*cmpdi_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
operands[5] = GEN_INT (sextc);
}")
-(define_insn ""
+(define_insn "*cmpsi_internal2"
[(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
"{cmpl%I2|cmplw%I2} %0,%1,%W2"
[(set_attr "type" "compare")])
-(define_insn ""
+(define_insn "*cmpdi_internal2"
[(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
(compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
[(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
-(define_insn ""
+(define_insn "*cmpsf_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"fcmpu %0,%1,%2"
[(set_attr "type" "fpcompare")])
-(define_insn ""
+(define_insn "*cmpdf_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]