Fix invalid verilog syntax

diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v
index 99c123f4a3ac098b5d941145c791064937c05de3..15cea3d8d5b0d00f0aca2a5a827a4f3168f8941d 100644 (file)
--- a/techlibs/common/gate2lut.v
+++ b/techlibs/common/gate2lut.v
@@ -79,7 +79,7 @@ module _90_lut_mux (A, B, S, Y);
         //     A 1010 1010
         //     B 1100 1100
         //     S 1111 0000
-        .LUT(8'b_1100_1010)
+        .LUT(8'b 1100_1010)
     ) lut (
         .A(AA),
         .Y(Y)