Allow initial blocks to be disabled during tests

Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.

diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
index 576bd81a6521ee26a2a04ac52ec0640db2cd9e61..966e7c2b87fdedbe2773ad5ab90471f07bccf66a 100644 (file)
--- a/tests/arch/common/adffs.v
+++ b/tests/arch/common/adffs.v
@@ -1,7 +1,9 @@
 module adff( input d, clk, clr, output reg q );
+`ifndef NO_INIT
     initial begin
         q = 0;
     end
+`endif
          always @( posedge clk, posedge clr )
       if ( clr )
         q <= 1'b0;
@@ -10,9 +12,11 @@ module adff( input d, clk, clr, output reg q );
 endmodule
 
 module adffn( input d, clk, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
          always @( posedge clk, negedge clr )
                  if ( !clr )
                          q <= 1'b0;
@@ -21,9 +25,11 @@ module adffn( input d, clk, clr, output reg q );
 endmodule
 
 module dffs( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
     always @( posedge clk )
       if ( pre )
         q <= 1'b1;
@@ -32,9 +38,11 @@ module dffs( input d, clk, pre, clr, output reg q );
 endmodule
 
 module ndffnr( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
     always @( negedge clk )
       if ( !clr )
         q <= 1'b0;

diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v
index 636252d16374d7d36ee8ce84ff66c2c7981475b0..0c607af5040b9184b8e3ea4800f76179c011ca98 100644 (file)
--- a/tests/arch/common/dffs.v
+++ b/tests/arch/common/dffs.v
@@ -4,9 +4,11 @@ module dff ( input d, clk, output reg q );
 endmodule
 
 module dffe( input d, clk, en, output reg q );
+`ifndef NO_INIT
     initial begin
         q = 0;
     end
+`endif
          always @( posedge clk )
         if ( en )
               q <= d;

diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v
index 3030608abb201c4b33f6b77dce3e24dc3637faaa..06e63c9af69319e24d53897b14694ce8d8113229 100644 (file)
--- a/tests/arch/common/shifter.v
+++ b/tests/arch/common/shifter.v
@@ -1,7 +1,13 @@
 module top(out, clk, in);
     output [7:0] out;
     input signed clk, in;
-    reg signed [7:0] out = 0;
+    reg signed [7:0] out;
+
+`ifndef NO_INIT
+    initial begin
+        out = 0;
+    end
+`endif
 
     always @(posedge clk)
        begin

diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys
index 7bba699f6564184c12b584fa450e907a6c30884f..3f9401d689e123bf06f895f503a5799e292dd516 100644 (file)
--- a/tests/arch/gatemate/adffs.ys
+++ b/tests/arch/gatemate/adffs.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/adffs.v
+read_verilog -D NO_INIT ../common/adffs.v
 design -save read
 
 hierarchy -top adff

diff --git a/tests/arch/gatemate/dffs.ys b/tests/arch/gatemate/dffs.ys
index 0a3944e50d1981190faf5250557be027e619a86d..0223224192a6e91fdf1d874e8e76296f95f8db90 100644 (file)
--- a/tests/arch/gatemate/dffs.ys
+++ b/tests/arch/gatemate/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/dffs.v
+read_verilog -D NO_INIT ../common/dffs.v
 design -save read
 
 hierarchy -top dff

diff --git a/tests/arch/gatemate/shifter.ys b/tests/arch/gatemate/shifter.ys
index 03df36ebc700ed7871b52277a39182e4f35c9d8d..0006a298a97deb0a11ff2a33206ddbb4d73b7393 100644 (file)
--- a/tests/arch/gatemate/shifter.ys
+++ b/tests/arch/gatemate/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/shifter.v
+read_verilog -D NO_INIT ../common/shifter.v
 hierarchy -top top
 proc
 flatten