Add POR start/end logging in simsoc testbench

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index 4c1cabf35a5d4d568373584fe713cbd239b2e8a8..984984533fd42fe7614e496d3e226a5e6269603e 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -112,7 +112,9 @@ module simsoctb;
   initial
     begin
       uart_rx <= 1'b1;
+      $display("[%t] Starting POR",$time);
       #700000; // POR is ~700us
+      $display("[%t] POR complete",$time);
 
       // Software control
       wishbone_write(32'h00009000 >> 2, 8'h0E); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE