(pushdi): Allow "i" for operand 1.

(extendqidi2): Improve 68000 code generation.
(adddi_lshrdi_63): New pattern.

From-SVN: r10988

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 98d860213b3e774d85c943f84d5f656081fb12d2..e8f58075d3ef98d7cee175f7d18d228130c3530b 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -1,5 +1,5 @@
 ;;- Machine description for GNU compiler, Motorola 68000 Version
-;;  Copyright (C) 1987, 1988, 1993, 1994, 1995 Free Software Foundation, Inc.
+;;  Copyright (C) 1987, 88, 93, 94, 95, 1996 Free Software Foundation, Inc.
 
 ;; This file is part of GNU CC.
 
@@ -269,9 +269,9 @@
   return output_move_double (operands);
 }")
 
-(define_insn ""
+(define_insn "pushdi"
   [(set (match_operand:DI 0 "push_operand" "=m")
-       (match_operand:DI 1 "general_operand" "ro<>Fy"))]
+       (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
   ""
   "*
 {
@@ -1624,7 +1624,7 @@
   if (TARGET_68020)
     return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
   else
-    return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
+    return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
 }")
 
 (define_insn "extendhidi2"
@@ -1980,6 +1980,40 @@
 \f
 ;; add instructions
 
+(define_insn "adddi_lshrdi_63"
+  [(set (match_operand:DI 0 "general_operand" "=d")
+    (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
+            (const_int 63))
+        (match_dup 1)))
+   (clobber (match_scratch:SI 2 "=d"))]
+  ""
+  "*
+{
+  operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+  if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
+    return
+    \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
+  if (GET_CODE (operands[1]) == REG)
+    operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
+        || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
+    operands[4] = operands[1];
+  else
+    operands[4] = adj_offsettable_operand (operands[1], 4);
+  if (GET_CODE (operands[1]) == MEM
+   && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
+    output_asm_insn (\"move%.l %4,%3\", operands);
+  output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
+  if (TARGET_68020)
+    output_asm_insn (\"extb%.l %2\", operands);
+  else
+    output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
+  if (GET_CODE (operands[1]) != MEM
+   || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
+    output_asm_insn (\"move%.l %4,%3\", operands);
+  return \"sub%.l %2,%3\;subx%.l %2,%0\";
+}")
+
 (define_insn "adddia_sexthishl32"
   [(set (match_operand:DI 0 "register_operand" "+a")
     (plus:DI (ashift:DI (sign_extend:DI