Make the floating point zero register special handling only apply for ALPHA.

--HG--
extra : convert_revision : 4f393a5471656b29cecbacfcb337992239775915

diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index c669b0b34f6268b885b4377ff227f0b30133419d..42fc0c533a94d7ab7ea400edd78b47b83cb5483e 100644 (file)
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -168,7 +168,9 @@ SimpleFreeList::addReg(PhysRegIndex freed_reg)
         if (freed_reg != TheISA::ZeroReg)
             freeIntRegs.push(freed_reg);
     } else if (freed_reg < numPhysicalRegs) {
+#if THE_ISA == ALPHA_ISA
         if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs))
+#endif
             freeFloatRegs.push(freed_reg);
     }
 }

diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index b5b1cd021492a94a4e82564d934f259f2600274a..75d3fa6eb63502aaaae5078be65578d083ba98e0 100644 (file)
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -179,7 +179,9 @@ class PhysRegFile
         DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
                 int(reg_idx), (uint64_t)val);
 
+#if THE_ISA == ALPHA_ISA
         if (reg_idx != TheISA::ZeroReg)
+#endif
             floatRegFile[reg_idx].d = val;
     }
 
@@ -194,7 +196,9 @@ class PhysRegFile
         DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
                 int(reg_idx), (uint64_t)val);
 
+#if THE_ISA == ALPHA_ISA
         if (reg_idx != TheISA::ZeroReg)
+#endif
             floatRegFile[reg_idx].d = val;
     }
 

diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index b436ec1c3b91cf4b76c588e4afea2b6e6236d7d4..e6649ce3e3abc354b9c9cf9e15cd781189f508cb 100644 (file)
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -165,17 +165,21 @@ SimpleRenameMap::rename(RegIndex arch_reg)
 
         // If it's not referencing the zero register, then rename the
         // register.
+#if THE_ISA == ALPHA_ISA
         if (arch_reg != floatZeroReg) {
+#endif
             renamed_reg = freeList->getFloatReg();
 
             floatRenameMap[arch_reg].physical_reg = renamed_reg;
 
             assert(renamed_reg < numPhysicalRegs &&
                    renamed_reg >= numPhysicalIntRegs);
+#if THE_ISA == ALPHA_ISA
         } else {
             // Otherwise return the zero register so nothing bad happens.
             renamed_reg = floatZeroReg;
         }
+#endif
     } else {
         // Subtract off the base offset for miscellaneous registers.
         arch_reg = arch_reg - numLogicalRegs;

diff --git a/src/cpu/o3/scoreboard.cc b/src/cpu/o3/scoreboard.cc
index 1859b35a4e8532c2a00ae24ac4580ce48feae4b6..e7f8b7949f37e9061722080052b5b88bdb365898 100644 (file)
--- a/src/cpu/o3/scoreboard.cc
+++ b/src/cpu/o3/scoreboard.cc
@@ -29,6 +29,7 @@
  *          Kevin Lim
  */
 
+#include "arch/isa_specific.hh"
 #include "cpu/o3/scoreboard.hh"
 
 Scoreboard::Scoreboard(unsigned activeThreads,
@@ -79,11 +80,18 @@ Scoreboard::name() const
 bool
 Scoreboard::getReg(PhysRegIndex phys_reg)
 {
+#if THE_ISA == ALPHA_ISA
     // Always ready if int or fp zero reg.
     if (phys_reg == zeroRegIdx ||
         phys_reg == (zeroRegIdx + numPhysicalIntRegs)) {
         return 1;
     }
+#else
+    // Always ready if int zero reg.
+    if (phys_reg == zeroRegIdx) {
+        return 1;
+    }
+#endif
 
     return regScoreBoard[phys_reg];
 }
@@ -99,11 +107,18 @@ Scoreboard::setReg(PhysRegIndex phys_reg)
 void
 Scoreboard::unsetReg(PhysRegIndex ready_reg)
 {
+#if THE_ISA == ALPHA_ISA
     if (ready_reg == zeroRegIdx ||
         ready_reg == (zeroRegIdx + numPhysicalIntRegs)) {
         // Don't do anything if int or fp zero reg.
         return;
     }
+#else
+    if (ready_reg == zeroRegIdx) {
+        // Don't do anything if int zero reg.
+        return;
+    }
+#endif
 
     regScoreBoard[ready_reg] = 0;
 }