Rename from cke to clk_en

diff --git a/gram/core/multiplexer.py b/gram/core/multiplexer.py
index 90c566853b49a495e76133c04458fc05faa80242..f1d25487839564552d30c28256db8d10ac52e25d 100644 (file)
--- a/gram/core/multiplexer.py
+++ b/gram/core/multiplexer.py
@@ -168,7 +168,7 @@ class _Steerer(Elaboratable):
             rankbits = log2_int(nranks)
             if hasattr(phase, "reset_n"):
                 m.d.comb += phase.reset_n.eq(1)
-            m.d.comb += phase.cke.eq(Repl(Signal(reset=1), nranks))
+            m.d.comb += phase.clk_en.eq(Repl(Signal(reset=1), nranks))
             if hasattr(phase, "odt"):
                 # FIXME: add dynamic drive for multi-rank (will be needed for high frequencies)
                 m.d.comb += phase.odt.eq(Repl(Signal(reset=1), nranks))

diff --git a/gram/dfii.py b/gram/dfii.py
index 53053fe42a791c986a410549d81dbcea77954ba1..5b9664cca4076785db138103f13f25d1f50e7e81 100644 (file)
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -65,7 +65,7 @@ class DFIInjector(Elaboratable):
         self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
         self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
 
-        self._control = csr_bank.csr(4, "w")  # sel, cke, odt, reset_n
+        self._control = csr_bank.csr(4, "w")  # sel, clk_en, odt, reset_n
 
         self._phases = []
         for n, phase in enumerate(self._inti.phases):
@@ -83,7 +83,7 @@ class DFIInjector(Elaboratable):
             m.d.comb += self._inti.connect(self.master)
 
         for i in range(self._nranks):
-            m.d.comb += [phase.cke[i].eq(self._control.w_data[1])
+            m.d.comb += [phase.clk_en[i].eq(self._control.w_data[1])
                          for phase in self._inti.phases]
             m.d.comb += [phase.odt[i].eq(self._control.w_data[2])
                          for phase in self._inti.phases if hasattr(phase, "odt")]

diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py
index 0f6f4ae2dc669a00b79bc5d3dbc4cae89f48634e..dd3bc372fe8b23a2bfb88dd88d4633206fd67613 100644 (file)
--- a/gram/phy/dfi.py
+++ b/gram/phy/dfi.py
@@ -16,7 +16,7 @@ def phase_description(addressbits, bankbits, nranks, databits):
         ("cs_n",         nranks, DIR_FANOUT),
         ("ras_n",             1, DIR_FANOUT),
         ("we_n",              1, DIR_FANOUT),
-        ("cke",          nranks, DIR_FANOUT),
+        ("clk_en",          nranks, DIR_FANOUT),
         ("odt",          nranks, DIR_FANOUT),
         ("reset_n",           1, DIR_FANOUT),
         ("act_n",             1, DIR_FANOUT),

diff --git a/gram/simulation/icarusecpix5platform.py b/gram/simulation/icarusecpix5platform.py
index 1f0c9c6433772ece82a1964b6fbd072201a1e9fb..9296f4555021ba13052f94cfe281a3decabf3297 100644 (file)
--- a/gram/simulation/icarusecpix5platform.py
+++ b/gram/simulation/icarusecpix5platform.py
@@ -67,7 +67,7 @@ class IcarusECPIX5Platform(LatticeECP5Platform):
         Resource("ddr3", 0,
                  Subsignal("clk", Pins("H3", dir="o")),
                  #Subsignal("clk",    DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")),
-                 Subsignal("cke", Pins("P1", dir="o")),
+                 Subsignal("clk_en", Pins("P1", dir="o")),
                  Subsignal("we_n", Pins("R3", dir="o")),
                  Subsignal("ras_n", Pins("T3", dir="o")),
                  Subsignal("cas_n", Pins("P2", dir="o")),