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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index efcf9a761bad21527c7cbf1b002b0f307689c8ae..9abaed8a6a966dc013f3b86fa13586365dab92de 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -186,7 +186,7 @@ These are the modes:
 * **ffirst** or data-dependent fail-on-first: see separate section.  the vector may be truncated depending on certain criteria.
   *VL is altered as a result*.
 * **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping. 
-* **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see separate section below.
+* **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see [[appendix]]
   note that there are comprehensive caveats when using this mode.
 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero.  When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed.  This scheme does not apply to crops (crand, cror).  See appendix for details.
 
@@ -454,7 +454,7 @@ or EXTRA3 field from the SV Prefix.  The prefixing is arranged so that
 interoperability between prefixing and nonprefixing of scalar registers
 is direct and convenient (when the EXTRA field is all zeros).
 
-A pseudocode algorithm explains the relationship, for INT/FP (see separate section for CRs)
+A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
 
     if extra3_mode:
         spec = EXTRA3